mesa.git
7 years agoi965: Make unsynchronized maps unsynchronized on non-LLC
Matt Turner [Thu, 1 Jun 2017 04:14:15 +0000 (21:14 -0700)]
i965: Make unsynchronized maps unsynchronized on non-LLC

On Broxton, the performance of Unigine Valley 1.0 is improved by
13.3067% +/- 0.144322% (n=40) at 1280x720/QUALITY_LOW, and by
1.68478% +/- 0.484226% (n=3) at 1920x1080/QUALITY_LOW.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
7 years agoi965: Implement brw_bo_map_unsynchronized() with MAP_ASYNC
Matt Turner [Thu, 1 Jun 2017 04:12:01 +0000 (21:12 -0700)]
i965: Implement brw_bo_map_unsynchronized() with MAP_ASYNC

This way we can let brw_bo_map() choose the best mapping type.

Part of the patch inlines map_gtt() into brw_bo_map_gtt() (and removes
map_gtt()). brw_bo_map_gtt() just wrapped map_gtt() with locking and a
call to set_domain(). map_gtt() is called by brw_bo_map_unsynchronized()
to avoid the call to set_domain(). With the MAP_ASYNC flag, we now have
the same behavior previously provided by brw_bo_map_unsynchronized().

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
7 years agoi965: Elide call to set_domain() if MAP_ASYNC
Matt Turner [Thu, 1 Jun 2017 04:06:18 +0000 (21:06 -0700)]
i965: Elide call to set_domain() if MAP_ASYNC

No functional change (no callers currently pass MAP_ASYNC)

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
7 years agoi965: Add and use brw_bo_map()
Matt Turner [Thu, 18 May 2017 18:26:08 +0000 (11:26 -0700)]
i965: Add and use brw_bo_map()

We can encapsulate the logic for choosing the mapping type. This will
also help when we add WC mappings.

A few functional changes are made in this patch. On non-LLC, what were
previously WB mappings are now GTT mappings (in the prefilling debug
code in brw_performance_query.c; the shader_time code in brw_program.c;
and in the case of an RW mapping in intel_buffer_objects.c).

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
7 years agoi965: Drop MAP_READ from some write-only mappings
Matt Turner [Thu, 18 May 2017 18:29:00 +0000 (11:29 -0700)]
i965: Drop MAP_READ from some write-only mappings

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
7 years agoi965: Pass flags to brw_bo_map_*
Matt Turner [Thu, 18 May 2017 17:59:23 +0000 (10:59 -0700)]
i965: Pass flags to brw_bo_map_*

brw_bo_map_cpu() took a write_enable arg, but it wasn't always clear
whether we were also planning to read from the buffer. I kept everything
semantically identical by passing only MAP_READ or MAP_READ | MAP_WRITE
depending on the write_enable argument.

The other flags are not used yet, but MAP_ASYNC for instance, will be
used in a later patch to remove the need for a separate
brw_bo_map_unsynchronized() function.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
7 years agoi965: Rename brw_bo_map() -> brw_bo_map_cpu()
Matt Turner [Wed, 17 May 2017 22:44:30 +0000 (15:44 -0700)]
i965: Rename brw_bo_map() -> brw_bo_map_cpu()

I'm going to make a new function named brw_bo_map() in a later patch
that is responsible for choosing the mapping type, so this patch clears
the way.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
7 years agoi965: Rename *_virtual -> map_*
Matt Turner [Wed, 17 May 2017 18:41:40 +0000 (11:41 -0700)]
i965: Rename *_virtual -> map_*

I think these are better names, and it reduces the delta between
upstream and Chris Wilson's brw-batch branch.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
7 years agoi965: Pass the map-mode along to intel_mipmap_tree_map_raw()
Chris Wilson [Wed, 6 May 2015 10:19:44 +0000 (11:19 +0100)]
i965: Pass the map-mode along to intel_mipmap_tree_map_raw()

Since we can distinguish when mapping between READ and WRITE, we can
pass along the map mode to avoid stalls and flushes where possible.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Matt Turner <mattst88@gmail.com>
7 years agoi965: Add a cache_coherent field to brw_bo
Matt Turner [Thu, 18 May 2017 19:02:39 +0000 (12:02 -0700)]
i965: Add a cache_coherent field to brw_bo

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
7 years agoi965: Remove unused 'use_resource_streamer' field
Matt Turner [Thu, 11 May 2017 18:53:27 +0000 (11:53 -0700)]
i965: Remove unused 'use_resource_streamer' field

Missing in the resource streamer removal of commit 951f56cd43bc.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
7 years agoi965: Remove brw_bo's virtual member
Matt Turner [Fri, 5 May 2017 18:20:05 +0000 (11:20 -0700)]
i965: Remove brw_bo's virtual member

Just return the map from brw_map_bo_*

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
7 years agoi965: Remove unused brw_bo_map__* functions
Matt Turner [Wed, 3 May 2017 21:19:11 +0000 (14:19 -0700)]
i965: Remove unused brw_bo_map__* functions

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
7 years agoanv: Set better descriptor set limits
Alex Smith [Mon, 5 Jun 2017 14:49:05 +0000 (15:49 +0100)]
anv: Set better descriptor set limits

Based on discussions with Jason, Ivy Bridge and Bay Trail only actually
support 16 samplers, while newer hardware can support more than the
current limit of 64. Therefore set the lower limit where needed, and
bump up to 128 for everything else. There is also a limit on the total
number of other resources of around 250.

This allows Dawn of War III to render correctly on ANV.

Signed-off-by: Alex Smith <asmith@feralinteractive.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
7 years agoanv: Set driver version to Mesa version
Alex Smith [Tue, 6 Jun 2017 09:42:41 +0000 (10:42 +0100)]
anv: Set driver version to Mesa version

As already done by RADV.

v2: Move version calculation function to src/vulkan/util to share with
    RADV.

Signed-off-by: Alex Smith <asmith@feralinteractive.com>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
Reviewed-by: Eric Engestrom <eric.engestrom@imgtec.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
7 years agoradv/vulkan: Move radv_get_driver_version to src/vulkan/util
Alex Smith [Tue, 6 Jun 2017 15:09:07 +0000 (16:09 +0100)]
radv/vulkan: Move radv_get_driver_version to src/vulkan/util

This means it can be reused for other Vulkan drivers. Also fix up a
typo, need to search for '.' in the version string rather than ','.

v2: Remove unneeded temporary version variable (Emil, Eric)

Signed-off-by: Alex Smith <asmith@feralinteractive.com>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
Reviewed-by: Eric Engestrom <eric.engestrom@imgtec.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
7 years agoutil/vulkan: Move Vulkan utilities to src/vulkan/util
Alex Smith [Tue, 6 Jun 2017 11:31:05 +0000 (12:31 +0100)]
util/vulkan: Move Vulkan utilities to src/vulkan/util

We have Vulkan utilities in both src/util and src/vulkan/util. The
latter seems a more appropriate place for Vulkan-specific things, so
move them there.

v2: Android build system changes (from Tapani Pälli)

Signed-off-by: Alex Smith <asmith@feralinteractive.com>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
Reviewed-by: Eric Engestrom <eric.engestrom@imgtec.com>
Acked-by: Jason Ekstrand <jason@jlekstrand.net>
7 years agointel: gen-decoder: rework how we handle groups
Lionel Landwerlin [Tue, 30 May 2017 19:06:48 +0000 (20:06 +0100)]
intel: gen-decoder: rework how we handle groups

The current way of handling groups doesn't seem to be able to handle
MI_LOAD_REGISTER_* with more than one register. This change reworks
the way we handle groups by building a traversal list on loading the
GENXML files.

Let's say you have

Instruction {
  Field0
  Field1
  Field2
  Group0 (count=2) {
    Field0-0
    Field0-1
  }
  Group1 (count=4) {
    Field1-0
    Field1-1
  }
}

We build of linked on load that goes :

Instruction -> Group0 -> Group1

All of those are gen_group structures, making the traversal trivial.
We just need to iterate groups for the right number of timers (count
field in genxml).

The more fancy case is when you have only a single group of unknown
size (count=0). In that case we keep on reading that group for as long
as we're within the DWordLength of that instruction.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Rafael Antognolli <rafael.antognolli@intel.com>
7 years agoradeonsi: fix a GPU hang with tessellation on 2-CU configs
Marek Olšák [Tue, 23 May 2017 19:52:11 +0000 (21:52 +0200)]
radeonsi: fix a GPU hang with tessellation on 2-CU configs

Only harvested Stoney has 2 CUs. Tested on 2-CU Stoney and Fiji forced
to 2 CUs.

Cc: 17.0 17.1 <mesa-stable@lists.freedesktop.org>
Tested-by: Edmondo Tommasina <edmondo.tommasina@gmail.com>
Tested-by: Dieter Nützel <Dieter@nuetzel-hh.de>
7 years agomesa: make use of NewWindowRectangles driver flags
Samuel Pitoiset [Fri, 2 Jun 2017 12:31:49 +0000 (14:31 +0200)]
mesa: make use of NewWindowRectangles driver flags

Now, st_update_window_rectangles() won't be called when the
scissor is going to be updated.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
7 years agomesa: add new gl_driver_flags::NewWindowRectangles
Samuel Pitoiset [Fri, 2 Jun 2017 12:31:48 +0000 (14:31 +0200)]
mesa: add new gl_driver_flags::NewWindowRectangles

This new driver flag will replace _NEW_SCISSOR which is
emitted when setting new window rectangles but it actually
triggers useless changes in the state tracker (like scissor
and rasterizer).

EXT_window_rectangles is currently only supported by Nouveau.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
7 years agomesa: remove call to Driver.Scissor() in _mesa_WindowRectanglesEXT()
Samuel Pitoiset [Fri, 2 Jun 2017 12:31:47 +0000 (14:31 +0200)]
mesa: remove call to Driver.Scissor() in _mesa_WindowRectanglesEXT()

This is actually useless because this driver call is only used
by the classic DRI drivers which don't support that extension
and probably won't never support it.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
7 years agomesa: only emit _NEW_MULTISAMPLE when min sample shading changes
Samuel Pitoiset [Fri, 2 Jun 2017 15:52:49 +0000 (17:52 +0200)]
mesa: only emit _NEW_MULTISAMPLE when min sample shading changes

We usually check that given parameters are different before
updating the state.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
7 years agomesa: only emit _NEW_MULTISAMPLE when sample mask changes
Samuel Pitoiset [Fri, 2 Jun 2017 15:52:48 +0000 (17:52 +0200)]
mesa: only emit _NEW_MULTISAMPLE when sample mask changes

We usually check that given parameters are different before
updating the state.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
7 years agomesa: only emit _NEW_MULTISAMPLE when coverage parameters change
Samuel Pitoiset [Fri, 2 Jun 2017 15:52:47 +0000 (17:52 +0200)]
mesa: only emit _NEW_MULTISAMPLE when coverage parameters change

We usually check that given parameters are different before
updating the state.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
7 years agoi965: Change INTEL_DEBUG=vec4 to INTEL_SCALAR_VS for consistency.
Kenneth Graunke [Sat, 3 Jun 2017 19:26:29 +0000 (12:26 -0700)]
i965: Change INTEL_DEBUG=vec4 to INTEL_SCALAR_VS for consistency.

We moved to INTEL_SCALAR_* when we added more than a single stage, but
never went back and converted the VS to work that way.  Be consistent.

Also update the documentation to actually mention these debug variables.

Acked-by: Jason Ekstrand <jason@jlekstrand.net>
7 years agoradv: expose integrated device type for APUs.
Dave Airlie [Mon, 15 May 2017 01:27:10 +0000 (11:27 +1000)]
radv: expose integrated device type for APUs.

This just sets the vulkan device type depending on whether
this is an APU or GPU.

Signed-off-by: Dave Airlie <airlied@redhat.com>
Fixes: f4e499ec791 "radv: add initial non-conformant radv vulkan driver"
7 years agoac/surface: Fix HTILE for radv.
Bas Nieuwenhuizen [Sun, 21 May 2017 21:40:54 +0000 (23:40 +0200)]
ac/surface: Fix HTILE for radv.

We always compute HTILE size using addrlib, even when not TC compatible.

Signed-off-by: Bas Nieuwenhuizen <basni@google.com>
Reviewed-by: Dave Airlied <airlied@redhat.com>
7 years agoradv: fix write event eop on vega.
Dave Airlie [Tue, 6 Jun 2017 00:39:16 +0000 (10:39 +1000)]
radv: fix write event eop on vega.

Typo here, fixes command submission hangs on vega

7 years agoradv: enable GFX9 on radv
Dave Airlie [Mon, 5 Jun 2017 23:06:57 +0000 (09:06 +1000)]
radv: enable GFX9 on radv

I'm open to reverting this closer to release if bad things
happen, but it might be easier to debugging to leave it for now.

Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Signed-off-by: Dave Airlie <airlied@redhat.com>
7 years agoradv: turn off geom/tess for gfx9.
Dave Airlie [Mon, 5 Jun 2017 23:06:41 +0000 (09:06 +1000)]
radv: turn off geom/tess for gfx9.

We don't support these yet, and it'll take a bit of work to do so.

Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Signed-off-by: Dave Airlie <airlied@redhat.com>
7 years agoradv: misc GFX9 changes.
Dave Airlie [Mon, 5 Jun 2017 23:06:21 +0000 (09:06 +1000)]
radv: misc GFX9 changes.

These are just some register changes ported from radeonsi for gfx9.

Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Signed-off-by: Dave Airlie <airlied@redhat.com>
7 years agoradv: add some GFX9 specific events.
Dave Airlie [Mon, 5 Jun 2017 23:05:47 +0000 (09:05 +1000)]
radv: add some GFX9 specific events.

These are ported from radeonsi, don't know all the rules for
when they should be inserted.

Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Signed-off-by: Dave Airlie <airlied@redhat.com>
7 years agoradv: add IA_MULTI_VGT_PARAM support for GFX9.
Dave Airlie [Mon, 5 Jun 2017 23:05:12 +0000 (09:05 +1000)]
radv: add IA_MULTI_VGT_PARAM support for GFX9.

Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Signed-off-by: Dave Airlie <airlied@redhat.com>
7 years agoradv: add rb+ support for GFX9
Dave Airlie [Mon, 5 Jun 2017 23:03:55 +0000 (09:03 +1000)]
radv: add rb+ support for GFX9

This adds some rb+ support, as on GFX9 we have to disable
it as per radeonsi.

Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Signed-off-by: Dave Airlie <airlied@redhat.com>
7 years agoradv: add GFX9 cache flushing support.
Dave Airlie [Mon, 5 Jun 2017 23:01:48 +0000 (09:01 +1000)]
radv: add GFX9 cache flushing support.

GFX9 needs to write event EOP to a fence buffer, allocate some
space for this, and just write an ever increasing number to it,
this isn't exactly what radeonsi does, but it seems to work.

Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Signed-off-by: Dave Airlie <airlied@redhat.com>
7 years agoradv: add texture descriptor/fmask/cmask support for GFX9
Dave Airlie [Mon, 5 Jun 2017 22:54:38 +0000 (08:54 +1000)]
radv: add texture descriptor/fmask/cmask support for GFX9

This adds gfx9 support for the texture descriptor along
with the fmask/cmask allocation routines.

Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Signed-off-by: Dave Airlie <airlied@redhat.com>
7 years agoradv: add GFX9 to initialisation cmd buffer.
Dave Airlie [Mon, 5 Jun 2017 22:50:14 +0000 (08:50 +1000)]
radv: add GFX9 to initialisation cmd buffer.

This just adds support for initialising some GFX9 registers,
and handles the different init for the VGT reuse reg.

Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Signed-off-by: Dave Airlie <airlied@redhat.com>
7 years agoradv: don't setup raster_config on gfx9.
Dave Airlie [Mon, 5 Jun 2017 22:48:25 +0000 (08:48 +1000)]
radv: don't setup raster_config on gfx9.

Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Signed-off-by: Dave Airlie <airlied@redhat.com>
7 years agoradv: add gfx9 cp dma support.
Dave Airlie [Mon, 5 Jun 2017 22:47:22 +0000 (08:47 +1000)]
radv: add gfx9 cp dma support.

This adds support to the CP dma code for GFX9, ported from
radeonsi.

Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Signed-off-by: Dave Airlie <airlied@redhat.com>
7 years agoradv: add gfx9 depth/stencil surface support.
Dave Airlie [Mon, 5 Jun 2017 22:39:44 +0000 (08:39 +1000)]
radv: add gfx9 depth/stencil surface support.

This is ported from radeonsi.

Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Signed-off-by: Dave Airlie <airlied@redhat.com>
7 years agoradv: add GFX9 support for color surfaces.
Dave Airlie [Mon, 5 Jun 2017 22:38:36 +0000 (08:38 +1000)]
radv: add GFX9 support for color surfaces.

This is ported from radeonsi.

Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Signed-off-by: Dave Airlie <airlied@redhat.com>
7 years agoradv: add some misc gfx9 pieces.
Dave Airlie [Mon, 5 Jun 2017 22:33:53 +0000 (08:33 +1000)]
radv: add some misc gfx9 pieces.

This just adds the strings and includes the gfx9 register defs
in some files that we need them in.

Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Signed-off-by: Dave Airlie <airlied@redhat.com>
7 years agoradv: set offchip hs param like radeonsi.
Dave Airlie [Mon, 5 Jun 2017 22:36:24 +0000 (08:36 +1000)]
radv: set offchip hs param like radeonsi.

radeonsi never uses 512 here anymore.

Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Signed-off-by: Dave Airlie <airlied@redhat.com>
7 years agoradv: fix typo in comment.
Dave Airlie [Mon, 5 Jun 2017 22:58:54 +0000 (08:58 +1000)]
radv: fix typo in comment.

7 years agoradv: add a comment from radeonsi before cp dma function.
Dave Airlie [Mon, 5 Jun 2017 22:43:38 +0000 (08:43 +1000)]
radv: add a comment from radeonsi before cp dma function.

This is just copied over.

Signed-off-by: Dave Airlie <airlied@redhat.com>
7 years agoradv: remove doubled up prototype.
Dave Airlie [Mon, 5 Jun 2017 22:27:35 +0000 (08:27 +1000)]
radv: remove doubled up prototype.

Must have snuck in during a rebase.

7 years agoradv: split metadata struct into legacy/gfx9 parts.
Dave Airlie [Wed, 24 May 2017 01:37:06 +0000 (11:37 +1000)]
radv: split metadata struct into legacy/gfx9 parts.

This is just ported from radeonsi.

Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Signed-off-by: Dave Airlie <airlied@redhat.com>
7 years agoradv: refactor some texture descriptor state.
Dave Airlie [Mon, 5 Jun 2017 01:09:30 +0000 (02:09 +0100)]
radv: refactor some texture descriptor state.

This just splits out some non-gfx9 bits in advance to avoid
regressions.

Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Signed-off-by: Dave Airlie <airlied@redhat.com>
7 years agoradv: refactor color surface init before gfx9.
Dave Airlie [Mon, 5 Jun 2017 01:05:59 +0000 (02:05 +0100)]
radv: refactor color surface init before gfx9.

This just moves the code around in preparation for gfx9 support.

Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Signed-off-by: Dave Airlie <airlied@redhat.com>
7 years agoradv: refactor depth/stencil state setup
Dave Airlie [Mon, 5 Jun 2017 01:01:10 +0000 (02:01 +0100)]
radv: refactor depth/stencil state setup

In advance of GFX9 to reduce chances for regression, refactor
this code out so adding the GFX9 changes will be more obvious.

Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Signed-off-by: Dave Airlie <airlied@redhat.com>
7 years agoradv: use radv_foreach_stage in a couple of places.
Dave Airlie [Mon, 5 Jun 2017 02:07:26 +0000 (12:07 +1000)]
radv: use radv_foreach_stage in a couple of places.

This just collapses a few per-stage things into a loop,
shouldn't affect anything.

Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Signed-off-by: Dave Airlie <airlied@redhat.com>
7 years agoradeon: remove out of date LLVM_REVISION.txt
Emil Velikov [Wed, 31 May 2017 20:08:45 +0000 (15:08 -0500)]
radeon: remove out of date LLVM_REVISION.txt

The file was introduced to track which LLVM revision was required, yet
that has quickly gone out of shape.

It has seen no updates since 2013.

Cc: Nicolai Hähnle <nicolai.haehnle@amd.com>
Cc: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
Reviewed-by: Aaron Watry <awatry@gmail.com>
7 years agodocs: update calendar, add news item and link release notes for 17.1.2
Juan A. Suarez Romero [Mon, 5 Jun 2017 21:21:35 +0000 (21:21 +0000)]
docs: update calendar, add news item and link release notes for 17.1.2

Signed-off-by: Juan A. Suarez Romero <jasuarez@igalia.com>
7 years agodocs: add sha256 checksums for 17.1.2
Juan A. Suarez Romero [Mon, 5 Jun 2017 21:15:43 +0000 (21:15 +0000)]
docs: add sha256 checksums for 17.1.2

Signed-off-by: Juan A. Suarez Romero <jasuarez@igalia.com>
(cherry picked from commit 4908b1e909ba4cfd5391f61ea551d21cccb52e2f)

7 years agodocs: add release notes for 17.1.2
Juan A. Suarez Romero [Mon, 5 Jun 2017 20:27:24 +0000 (20:27 +0000)]
docs: add release notes for 17.1.2

Signed-off-by: Juan A. Suarez Romero <jasuarez@igalia.com>
(cherry picked from commit 97f6404e50212fb65fe047e467f5497bcba5b8ac)

7 years agogallium/u_threaded: fixes for MSVC
Brian Paul [Mon, 5 Jun 2017 20:13:14 +0000 (14:13 -0600)]
gallium/u_threaded: fixes for MSVC

Replace some static assertions with runtime assertions.  The static
asserts don't work/fail on MSVC, despite the offsets being multiples
of 16 (checked with softpipe).

Use correct parameter types for a few gallium context functions.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
7 years agor600: refactor out some compressed resource state code.
Dave Airlie [Mon, 5 Jun 2017 03:34:05 +0000 (13:34 +1000)]
r600: refactor out some compressed resource state code.

This just takes this out to a separate function as it will
get more complex with images.

Reviewed-by: Glenn Kennard <glenn.kennard@gmail.com>
7 years agor600: document some of the missing shader constants.
Dave Airlie [Mon, 5 Jun 2017 03:25:29 +0000 (13:25 +1000)]
r600: document some of the missing shader constants.

These are used for fragment shader thread calculations.

Reviewed-by: Glenn Kennard <glenn.kennard@gmail.com>
7 years agor600: add register info for atomic counters.
Dave Airlie [Mon, 5 Jun 2017 03:24:12 +0000 (13:24 +1000)]
r600: add register info for atomic counters.

The atomic counters on evergreen are implemented via append/consume
UAV counters. This just adds the register info for them. The EOS
packets are used to get the atomic totals extracted post shader
execution for storing into a buffer.

Reviewed-by: Glenn Kennard <glenn.kennard@gmail.com>
7 years agor600: add missing RAT registers and operations.
Dave Airlie [Mon, 5 Jun 2017 03:22:07 +0000 (13:22 +1000)]
r600: add missing RAT registers and operations.

This just documents in the headers the RAT operation list,
and the RAT encoding for exports.

The immediate registers are used to point to buffers for the
RAT return values (_RTN instructions).

Reviewed-by: Glenn Kennard <glenn.kennard@gmail.com>
7 years agor600/sb: fix typo in field definitions
Dave Airlie [Mon, 5 Jun 2017 19:38:34 +0000 (05:38 +1000)]
r600/sb: fix typo in field definitions

Pointed out by glennk.

7 years agotgsi/scan: fix scanning fragment shaders with PrimID and Position/Face
Marek Olšák [Tue, 30 May 2017 00:04:29 +0000 (02:04 +0200)]
tgsi/scan: fix scanning fragment shaders with PrimID and Position/Face

Not relevant to radeonsi, because Position/Face are system values
with radeonsi, while this codepath is for drivers where Position and
Face are ordinary inputs.

Reviewed-by: Brian Paul <brianp@vmware.com>
7 years agoi965: Finalize miptrees before prepare_texture
Jason Ekstrand [Fri, 26 May 2017 17:57:33 +0000 (10:57 -0700)]
i965: Finalize miptrees before prepare_texture

In order to do resolves for texture views with different formats, we
need intel_texture_object::_Format to be valid.  Calling
intel_finalize_mipmap_tree can safely be done multiple times in a row
and should be a fairly cheap operation.

Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
7 years agogallium/u_threaded: remove 16 bytes from tc_batch
Marek Olšák [Tue, 30 May 2017 23:46:40 +0000 (01:46 +0200)]
gallium/u_threaded: remove 16 bytes from tc_batch

All other sentinels occupy what is otherwise unused space.

Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
7 years agogallium/u_threaded: align batches and call slots to 16 bytes
Marek Olšák [Tue, 30 May 2017 23:32:01 +0000 (01:32 +0200)]
gallium/u_threaded: align batches and call slots to 16 bytes

not sure if this helps

Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
7 years agost/mesa: don't load cached TGSI shaders on demand
Marek Olšák [Wed, 31 May 2017 11:07:04 +0000 (13:07 +0200)]
st/mesa: don't load cached TGSI shaders on demand

This fixes a performance issue with the shader cache that delayed Gallium
shader create calls until draw calls.

I'd like this in stable, but it's not a showstopper.

Cc: 17.1 <mesa-stable@lists.freedesktop.org>
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
7 years agoAndroid: use bionic pthread_barrier_* if possible
Chih-Wei Huang [Sun, 4 Jun 2017 04:53:01 +0000 (12:53 +0800)]
Android: use bionic pthread_barrier_* if possible

The pthread_barrier_* functions were introduced to bionic
since Nougat.

Signed-off-by: Chih-Wei Huang <cwhuang@linux.org.tw>
Acked-by: Tapani Pälli <tapani.palli@intel.com>
Acked-by: Emil Velikov <emil.velikov@collabora.com>
7 years agor600: fix incorrect and missing bit field in register headers.
Dave Airlie [Mon, 5 Jun 2017 03:19:18 +0000 (13:19 +1000)]
r600: fix incorrect and missing bit field in register headers.

The compression field was incorrect, and we were missing the
depth before shader field.

7 years agoradv: use ac_compute_surface
Nicolai Hähnle [Thu, 11 May 2017 23:46:46 +0000 (01:46 +0200)]
radv: use ac_compute_surface

Reviewed-by: Dave Airlie <airlied@redhat.com>
7 years agoradv: prepare fmask surface creation
Dave Airlie [Sun, 14 May 2017 23:43:25 +0000 (09:43 +1000)]
radv: prepare fmask surface creation

The old code copied over all the surface info from the image
surface, we only want some bits of it, and to modify the flags.

This prevents a regression in dEQP-VK.api.copy_and_blit.resolve_image.*
and others in the subsequent switch to ac_compute_surface.

v2:
- also disable opt4Space in radv_amdgpu_surface, so that we can
  apply this patch separately *before* switching to ac_compute_surface
  and hopefully avoid intermittent regressions (Nicolai)

Signed-off-by: Dave Airlie <airlied@redhat.com>
Reviewed-by: Dave Airlie <airlied@redhat.com>
Signed-off-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
7 years agoradv: use amdgpu_addr_create
Nicolai Hähnle [Thu, 11 May 2017 23:38:49 +0000 (01:38 +0200)]
radv: use amdgpu_addr_create

Reviewed-by: Dave Airlie <airlied@redhat.com>
7 years agoradv: stop using radv_amdgpu_winsys::family
Nicolai Hähnle [Thu, 11 May 2017 23:38:30 +0000 (01:38 +0200)]
radv: stop using radv_amdgpu_winsys::family

Reviewed-by: Dave Airlie <airlied@redhat.com>
7 years agoradv: use ac_gpu_info
Nicolai Hähnle [Thu, 11 May 2017 23:11:27 +0000 (01:11 +0200)]
radv: use ac_gpu_info

Reviewed-by: Dave Airlie <airlied@redhat.com>
7 years agoradv: remove radeon_info::name
Nicolai Hähnle [Thu, 11 May 2017 22:56:06 +0000 (00:56 +0200)]
radv: remove radeon_info::name

Reviewed-by: Dave Airlie <airlied@redhat.com>
7 years agoradv: use ac_surface data structures
Nicolai Hähnle [Wed, 10 May 2017 21:01:00 +0000 (23:01 +0200)]
radv: use ac_surface data structures

This is mostly mechanical changes of renaming types and introducing
"legacy" everywhere.

It doesn't use the ac_surface computation functions yet.

Reviewed-by: Dave Airlie <airlied@redhat.com>
7 years agoradv: rename radeon_surf::bo_{size,alignment} to surf_{size,alignment}
Nicolai Hähnle [Wed, 10 May 2017 20:41:36 +0000 (22:41 +0200)]
radv: rename radeon_surf::bo_{size,alignment} to surf_{size,alignment}

To match radeonsi / ac_surface.

Reviewed-by: Dave Airlie <airlied@redhat.com>
7 years agoradv: remove unused RADEON_SURF_HAS_SBUFFER_MIPTREE
Nicolai Hähnle [Wed, 10 May 2017 20:33:13 +0000 (22:33 +0200)]
radv: remove unused RADEON_SURF_HAS_SBUFFER_MIPTREE

Reviewed-by: Dave Airlie <airlied@redhat.com>
7 years agoradv: remove radeon_surf_level::nblk_z
Nicolai Hähnle [Wed, 10 May 2017 20:25:15 +0000 (22:25 +0200)]
radv: remove radeon_surf_level::nblk_z

We're not using thick tiling modes, so we can just derive the value
ourselves.

Reviewed-by: Dave Airlie <airlied@redhat.com>
7 years agoradv: remove radeon_surf_level::dcc_enabled
Nicolai Hähnle [Wed, 10 May 2017 20:20:37 +0000 (22:20 +0200)]
radv: remove radeon_surf_level::dcc_enabled

Like radeonsi; replace with radeon_surf::num_dcc_levels.

Reviewed-by: Dave Airlie <airlied@redhat.com>
7 years agoradv: remove radeon_surf_level::pitch_bytes
Nicolai Hähnle [Wed, 10 May 2017 20:14:39 +0000 (22:14 +0200)]
radv: remove radeon_surf_level::pitch_bytes

Like radeonsi. This saves memory, and the information can easily be
recomputed on the fly where necessary.

Reviewed-by: Dave Airlie <airlied@redhat.com>
7 years agoradv: add surface helper variable in radv_GetImageSubresourceLayout
Nicolai Hähnle [Wed, 10 May 2017 20:05:52 +0000 (22:05 +0200)]
radv: add surface helper variable in radv_GetImageSubresourceLayout

Reviewed-by: Dave Airlie <airlied@redhat.com>
7 years agoradv: fewer than 8 RBs are possible
Nicolai Hähnle [Tue, 16 May 2017 15:05:02 +0000 (17:05 +0200)]
radv: fewer than 8 RBs are possible

This fixes the subsequent assertion on Bonaire.

Reviewed-by: Dave Airlie <airlied@redhat.com>
7 years agoac/surface/gfx6: explicitly support S8 surfaces
Nicolai Hähnle [Tue, 16 May 2017 14:38:27 +0000 (16:38 +0200)]
ac/surface/gfx6: explicitly support S8 surfaces

This is needed by radv for dEQP-VK.renderpass.simple.stencil

Reviewed-by: Dave Airlie <airlied@redhat.com>
7 years agoac/nir: set workgroup size attribute to correct value.
Dave Airlie [Mon, 5 Jun 2017 00:20:48 +0000 (01:20 +0100)]
ac/nir: set workgroup size attribute to correct value.

This ports: 55445ff1891724c78e6573d2f8c721e14c0449fc from radeonsi

    radeonsi: tell LLVM not to remove s_barrier instructions

    LLVM 5.0 removes s_barrier instructions if the max-work-group-size
    attribute is not set. What a surprise.

Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Signed-off-by: Dave Airlie <airlied@redhat.com>
7 years agoac: add new helper function to add a integer target dependent function attr.
Dave Airlie [Mon, 5 Jun 2017 00:20:10 +0000 (01:20 +0100)]
ac: add new helper function to add a integer target dependent function attr.

This is needed to add the max workgroup size attribute.

Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Signed-off-by: Dave Airlie <airlied@redhat.com>
7 years agoradv: add external memory support.
Dave Airlie [Thu, 3 Nov 2016 04:16:43 +0000 (04:16 +0000)]
radv: add external memory support.

This adds support for exporting 2D images, to an
opaque fd.

This implements the:
VK_KHX_external_memory_capabilities
VK_KHX_external_memory
VK_KHX_external_memory_fd

extensions.

These are used by SteamVR, we should work with anv
to decide if we should ship these under an env
var or something.

v2 (Bas): - Don't expose the semaphore ext without implementing it.
          - Only export the capabilities ext as instance ext.
          - Implement radv_GetPhysicalDeviceExternalBufferPropertiesKHX.

Signed-off-by: Dave Airlie <airlied@redhat.com>
Signed-off-by: Bas Nieuwenhuizen <basni@google.com>
7 years agoradv: Add VkPhysicalDeviceIDProperties support.
Bas Nieuwenhuizen [Tue, 23 May 2017 07:22:09 +0000 (09:22 +0200)]
radv: Add VkPhysicalDeviceIDProperties support.

Signed-off-by: Bas Nieuwenhuizen <basni@google.com>
Reviewed-by: Dave Airlie <airlied@redhat.com>
7 years agoradv: Add support for external queue family.
Bas Nieuwenhuizen [Mon, 22 May 2017 21:50:13 +0000 (23:50 +0200)]
radv: Add support for external queue family.

Signed-off-by: Bas Nieuwenhuizen <basni@google.com>
Reviewed-by: Dave Airlie <airlied@redhat.com>
7 years agoradv/formats: reverse how the image format properties KHR2 is handled
Dave Airlie [Tue, 14 Mar 2017 23:40:17 +0000 (23:40 +0000)]
radv/formats: reverse how the image format properties KHR2 is handled

This just aligns with how anv does it.

Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Signed-off-by: Dave Airlie <airlied@redhat.com>
7 years agoradv: Dirty all descriptors sets when changing the pipeline.
Bas Nieuwenhuizen [Fri, 2 Jun 2017 22:01:36 +0000 (00:01 +0200)]
radv: Dirty all descriptors sets when changing the pipeline.

Sets could have been ignored during previous descriptor set flush
due to the shader not using them and therefore no SGPR being assigned.

Signed-off-by: Bas Nieuwenhuizen <basni@google.com>
Reviewed-by: Dave Airlie <airlied@redhat.com>
Fixes: ae61ddabe8c "radv: move userdata sgpr ownership to compiler side."
7 years agoradv: Set both compute and graphics SGPRS on descriptor set flush.
Bas Nieuwenhuizen [Fri, 2 Jun 2017 21:51:50 +0000 (23:51 +0200)]
radv: Set both compute and graphics SGPRS on descriptor set flush.

We clear the descriptors_dirty array afterwards, so the SGPRs for
the other pipeline don't get updated on the flush for that other
draw/dispatch, so we have to make sure we do it immediately.

Signed-off-by: Bas Nieuwenhuizen <basni@google.com>
Reviewed-by: Dave Airlie <airlied@redhat.com>
Fixes: ae61ddabe8c "radv: move userdata sgpr ownership to compiler side."
7 years agoi965: Order write of query availablity with earlier writes
Chris Wilson [Thu, 6 Oct 2016 20:07:18 +0000 (21:07 +0100)]
i965: Order write of query availablity with earlier writes

Currently we signal the availabilty of the query result using an
unordered pipe-control write. As it is unordered, it may be executed
before the write of the query result itself - and so an observer may
read the query result too early. Fix this by requesting that the write
of the availablity flag is ordered after earlier pipe control writes.

Testcase: piglit/arb_query_buffer_object-qbo/*async*
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
7 years agonvc0: Add support for ARB_post_depth_coverage
Lyude [Wed, 24 May 2017 19:42:41 +0000 (15:42 -0400)]
nvc0: Add support for ARB_post_depth_coverage

Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
7 years agost/mesa: Add support for ARB_post_depth_coverage
Lyude [Wed, 24 May 2017 19:42:40 +0000 (15:42 -0400)]
st/mesa: Add support for ARB_post_depth_coverage

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
7 years agogallium: Add a cap to check if the driver supports ARB_post_depth_coverage
Lyude [Wed, 24 May 2017 19:42:39 +0000 (15:42 -0400)]
gallium: Add a cap to check if the driver supports ARB_post_depth_coverage

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
7 years agogallium: Add TGSI shader token for ARB_post_depth_coverage
Lyude [Wed, 24 May 2017 19:42:38 +0000 (15:42 -0400)]
gallium: Add TGSI shader token for ARB_post_depth_coverage

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
7 years agonvc0: disable BGRA8 images on Fermi
Lyude [Sat, 3 Jun 2017 00:45:36 +0000 (20:45 -0400)]
nvc0: disable BGRA8 images on Fermi

BGRA8 image stores on Fermi don't work, which results in breaking
PBO downloads, such that they always return 0x0. Discovered this
through a glamor bug, and confirmed it does indeed break a good number
of piglit tests such as spec/arb_pixel_buffer_object/pbo-read-argb8888

Fixes: 8e7893eb53213 ("nvc0: add support for BGRA8 images")
Signed-off-by: Lyude <lyude@redhat.com>
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
Cc: mesa-stable@lists.freedesktop.org
7 years agoi965: Simplify l3 way size computations
Anuj Phogat [Thu, 1 Jun 2017 23:36:39 +0000 (16:36 -0700)]
i965: Simplify l3 way size computations

By making use of l3_banks field in gen_device_info struct
l3_way_size for gen7+ = 2 * l3_banks.

V2: Keep the get_l3_way_size() function.

Suggested-by: Francisco Jerez <currojerez@riseup.net>
Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com>
Reviewed-by: Francisco Jerez <currojerez@riseup.net>
7 years agoi965: Add and initialize l3_banks field for gen7+
Anuj Phogat [Thu, 1 Jun 2017 16:28:04 +0000 (09:28 -0700)]
i965: Add and initialize l3_banks field for gen7+

This new field helps simplify l3 way size computations
in next patch.

V2: Initialize the l3_banks to 0 in macros.

Suggested-by: Francisco Jerez <currojerez@riseup.net>
Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com>
Reviewed-by: Francisco Jerez <currojerez@riseup.net>