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Luke Kenneth Casson Leighton [Mon, 12 Oct 2020 11:58:34 +0000 (12:58 +0100)]
use unittest.TestCase rather than FHDLTestCase
Jacob Lifshay [Wed, 7 Oct 2020 02:36:11 +0000 (19:36 -0700)]
add overflow detection to DIVS
overflow shouldn't occur when calling DIVS since it should have been
detected in the code calling DIVS to properly handle edge cases.
Jacob Lifshay [Wed, 7 Oct 2020 02:33:07 +0000 (19:33 -0700)]
format code
Cesar Strauss [Sun, 27 Sep 2020 21:31:29 +0000 (18:31 -0300)]
Report cxxsim selected, only when using the new API
Cesar Strauss [Thu, 24 Sep 2020 22:26:16 +0000 (19:26 -0300)]
Add a few extra imports for convenience
Cesar Strauss [Thu, 24 Sep 2020 11:41:29 +0000 (08:41 -0300)]
Run-time selecion of simulator engine
Allows alternating between cxxsim and pysim at run-time, with minimal
code changes to its users.
Luke Kenneth Casson Leighton [Mon, 14 Sep 2020 15:54:40 +0000 (16:54 +0100)]
add extra name in plru for debugging
Luke Kenneth Casson Leighton [Mon, 14 Sep 2020 13:48:29 +0000 (14:48 +0100)]
switch off print statements
Luke Kenneth Casson Leighton [Mon, 14 Sep 2020 13:44:51 +0000 (14:44 +0100)]
add pseudo-plru from ariane
Luke Kenneth Casson Leighton [Sun, 13 Sep 2020 13:39:57 +0000 (14:39 +0100)]
add masked util function
Luke Kenneth Casson Leighton [Sun, 13 Sep 2020 13:11:12 +0000 (14:11 +0100)]
add dummy Display function
Luke Kenneth Casson Leighton [Sun, 13 Sep 2020 13:05:53 +0000 (14:05 +0100)]
syntax error in byterev
Cesar Strauss [Tue, 1 Sep 2020 11:14:13 +0000 (08:14 -0300)]
Make GTKWave example self-contained
As a tutorial, it should be as simple as possible.
Do not attempt to be compliant with the CompALU API anymore, use plain
signals at the interface.
Cesar Strauss [Sat, 29 Aug 2020 22:30:42 +0000 (19:30 -0300)]
Simplify example, focusing on write_gtkw
Complete Shifter example remains at soc.experiment.alu_fsm.
Cesar Strauss [Sat, 29 Aug 2020 20:52:58 +0000 (17:52 -0300)]
Move write_gtkw from soc.experiment.alu_fsm
Move implementation to nmutil.gtkw.
Move example to a separate file.
Luke Kenneth Casson Leighton [Sat, 29 Aug 2020 13:51:52 +0000 (14:51 +0100)]
add reversal and lsb/msb mode to PriorityPicker
Luke Kenneth Casson Leighton [Wed, 26 Aug 2020 14:26:09 +0000 (15:26 +0100)]
sorting out div/mod routines, bug in simulator
Luke Kenneth Casson Leighton [Wed, 19 Aug 2020 04:44:20 +0000 (05:44 +0100)]
1 extra bit on mask shift size needed, to allow ">" to work
Luke Kenneth Casson Leighton [Mon, 17 Aug 2020 11:11:05 +0000 (12:11 +0100)]
allow byterev to accept a scalar int
Luke Kenneth Casson Leighton [Mon, 17 Aug 2020 11:10:51 +0000 (12:10 +0100)]
add Mask class
Luke Kenneth Casson Leighton [Sun, 9 Aug 2020 18:44:09 +0000 (19:44 +0100)]
add rising edge function for generating pulse
Luke Kenneth Casson Leighton [Tue, 28 Jul 2020 10:36:40 +0000 (11:36 +0100)]
disable very verbose debug printing
Luke Kenneth Casson Leighton [Tue, 28 Jul 2020 10:35:49 +0000 (11:35 +0100)]
move "wrap" function into nmutil.util
Luke Kenneth Casson Leighton [Tue, 21 Jul 2020 11:20:28 +0000 (12:20 +0100)]
missed en_o on list of ports in PriorityPicker
Samuel A. Falvo II [Fri, 17 Jul 2020 23:27:03 +0000 (16:27 -0700)]
Check equality between two PipeContext instances.
Luke Kenneth Casson Leighton [Wed, 15 Jul 2020 13:56:02 +0000 (14:56 +0100)]
missed critical functions in cut/paste copy of PipeContext
Luke Kenneth Casson Leighton [Wed, 15 Jul 2020 13:51:32 +0000 (14:51 +0100)]
missing Signal import
Luke Kenneth Casson Leighton [Wed, 15 Jul 2020 13:41:35 +0000 (14:41 +0100)]
move FPPipeContext to concurrentunit: rename to PipeContext
see https://bugs.libre-soc.org/show_bug.cgi?id=431
Luke Kenneth Casson Leighton [Mon, 13 Jul 2020 18:12:22 +0000 (19:12 +0100)]
import globally not locally.
relative imports only work when the cwd from which they are run
is the top-level directory
Luke Kenneth Casson Leighton [Fri, 10 Jul 2020 19:49:49 +0000 (20:49 +0100)]
rename trunc_div/rem to trunc_divs
Luke Kenneth Casson Leighton [Thu, 9 Jul 2020 12:32:04 +0000 (13:32 +0100)]
cheat in trunch_rem, truncate result of multiply
Luke Kenneth Casson Leighton [Thu, 9 Jul 2020 12:28:42 +0000 (13:28 +0100)]
whoops trunc_div returning neg/neg result rather than abs/abs
Luke Kenneth Casson Leighton [Mon, 6 Jul 2020 15:58:07 +0000 (16:58 +0100)]
whoops missed Mux
Luke Kenneth Casson Leighton [Mon, 6 Jul 2020 15:55:56 +0000 (16:55 +0100)]
add eq32 helper
Luke Kenneth Casson Leighton [Sun, 5 Jul 2020 19:01:59 +0000 (20:01 +0100)]
remove unneeded imports
Luke Kenneth Casson Leighton [Sat, 4 Jul 2020 10:48:47 +0000 (11:48 +0100)]
add feedback_width option (unused) to concurrentunit pipeline
Luke Kenneth Casson Leighton [Thu, 2 Jul 2020 21:30:43 +0000 (22:30 +0100)]
use Mux in latchregister, try to break "loops"
Luke Kenneth Casson Leighton [Sat, 27 Jun 2020 18:23:41 +0000 (19:23 +0100)]
use prefix where it exists
Luke Kenneth Casson Leighton [Fri, 26 Jun 2020 22:31:33 +0000 (23:31 +0100)]
fix prefixes on RecordObject
Michael Nolan [Fri, 26 Jun 2020 17:53:35 +0000 (13:53 -0400)]
Remove print statements from recordobject
Luke Kenneth Casson Leighton [Thu, 25 Jun 2020 09:31:35 +0000 (10:31 +0100)]
update docstring on add_prefix_to_record_signals
Michael Nolan [Wed, 24 Jun 2020 20:03:10 +0000 (16:03 -0400)]
Modify RecordObject to prefix all signal names with the record name
Luke Kenneth Casson Leighton [Mon, 22 Jun 2020 10:30:57 +0000 (11:30 +0100)]
add byte-reverse helper function
Luke Kenneth Casson Leighton [Fri, 19 Jun 2020 21:16:07 +0000 (22:16 +0100)]
add trunc_div and trunc_rem functions
Luke Kenneth Casson Leighton [Thu, 4 Jun 2020 12:45:56 +0000 (13:45 +0100)]
add copy of FHDLTestCase from nmigen
Luke Kenneth Casson Leighton [Tue, 26 May 2020 12:45:32 +0000 (13:45 +0100)]
whoops
Luke Kenneth Casson Leighton [Tue, 26 May 2020 12:43:36 +0000 (13:43 +0100)]
generic-ify treereduce
Luke Kenneth Casson Leighton [Tue, 26 May 2020 12:36:09 +0000 (13:36 +0100)]
add treereduce function
Luke Kenneth Casson Leighton [Wed, 20 May 2020 13:28:03 +0000 (14:28 +0100)]
add sign/zero extending utilities
Luke Kenneth Casson Leighton [Tue, 19 May 2020 17:55:25 +0000 (18:55 +0100)]
minor whitespace, comment clz
Luke Kenneth Casson Leighton [Tue, 19 May 2020 16:27:31 +0000 (17:27 +0100)]
note that clz is identical to PriorityEncoder (which already exists)
Michael Nolan [Tue, 5 May 2020 15:15:43 +0000 (11:15 -0400)]
Add Count Leading Zeros module to nmutil
Michael Nolan [Tue, 5 May 2020 13:09:49 +0000 (09:09 -0400)]
Revert "Flatten the output of RecordObject.ports()"
This reverts commit
c2da46e377fbf04488622dbf33aa240988b1dd9e.
Michael Nolan [Mon, 4 May 2020 17:07:07 +0000 (13:07 -0400)]
Flatten the output of RecordObject.ports()
If a record contains records, calling ports on it will give a result
that cannot be passed to the nmigen simulation backend. This flattens
it, so that ports() will just return signals
Luke Kenneth Casson Leighton [Mon, 4 May 2020 12:53:05 +0000 (13:53 +0100)]
add docstring to latchregister
Luke Kenneth Casson Leighton [Fri, 1 May 2020 13:32:21 +0000 (14:32 +0100)]
add note about flatten function (one already exists in nmigen)
Luke Kenneth Casson Leighton [Fri, 1 May 2020 13:29:49 +0000 (14:29 +0100)]
add ripple.py to nmutil
Jacob Lifshay [Fri, 17 Apr 2020 03:28:51 +0000 (20:28 -0700)]
add flatten function
Luke Kenneth Casson Leighton [Thu, 16 Apr 2020 15:11:51 +0000 (16:11 +0100)]
adjust multi priority picker to accept multiple inputs
Luke Kenneth Casson Leighton [Thu, 16 Apr 2020 14:46:02 +0000 (15:46 +0100)]
whitespace
Luke Kenneth Casson Leighton [Mon, 13 Apr 2020 17:21:01 +0000 (18:21 +0100)]
detect if data_o or data_i is iterable in NextControl and PrevControl
Jacob Lifshay [Fri, 3 Apr 2020 04:49:56 +0000 (21:49 -0700)]
add build caching using ccache
Jacob Lifshay [Fri, 3 Apr 2020 03:48:58 +0000 (20:48 -0700)]
tests pass
Jacob Lifshay [Wed, 1 Apr 2020 03:48:55 +0000 (20:48 -0700)]
move clone paths to inside current directory
Jacob Lifshay [Wed, 1 Apr 2020 03:23:14 +0000 (20:23 -0700)]
add test case for https://github.com/nmigen/nmigen/issues/344
Jacob Lifshay [Wed, 1 Apr 2020 02:48:44 +0000 (19:48 -0700)]
switch nmigen upstream and add --depth 1
Jacob Lifshay [Wed, 1 Apr 2020 02:48:12 +0000 (19:48 -0700)]
reformat apt-get command
Jacob Lifshay [Thu, 26 Mar 2020 05:30:07 +0000 (22:30 -0700)]
add .gitlab-ci.yml
Luke Kenneth Casson Leighton [Wed, 25 Mar 2020 16:11:05 +0000 (16:11 +0000)]
grr fix more names thanks to nmigen renaming
Luke Kenneth Casson Leighton [Sun, 22 Mar 2020 14:30:29 +0000 (14:30 +0000)]
dont have to but test latchregister incoming is a Record
Luke Kenneth Casson Leighton [Sun, 22 Mar 2020 10:12:38 +0000 (10:12 +0000)]
comment latchregister
Luke Kenneth Casson Leighton [Sat, 21 Mar 2020 16:31:04 +0000 (16:31 +0000)]
sigh, rename of signals needed for nmigen compatibility with FIFOInterface
Luke Kenneth Casson Leighton [Wed, 18 Mar 2020 11:27:47 +0000 (11:27 +0000)]
realised that the enable lines will act just as well as port-enable lines
from MultiPriorityPicker, so make the binary-indices optional but
the enable-outputs mandatory
Luke Kenneth Casson Leighton [Tue, 17 Mar 2020 22:21:02 +0000 (22:21 +0000)]
realised that the MultiPriorityPicker only needs a 1D array of inputs
not a 2D array of input bits. input is chain-cascaded from previous
PriorityPicker after masking
Luke Kenneth Casson Leighton [Tue, 17 Mar 2020 21:36:50 +0000 (21:36 +0000)]
add indices output to MultiPriorityPicker
Luke Kenneth Casson Leighton [Tue, 17 Mar 2020 17:57:48 +0000 (17:57 +0000)]
create MultiPriorityPicker which can mutually-exclusively select M outputs from
Mx N-way inputs
to be used for example to ensure that M "things" seeking access to M
"other things" do not conflict: that only one "thing" at a time gets access
to the
other "things"
Luke Kenneth Casson Leighton [Mon, 9 Mar 2020 20:31:27 +0000 (20:31 +0000)]
allow name on latchregister
Luke Kenneth Casson Leighton [Sun, 9 Feb 2020 20:11:26 +0000 (20:11 +0000)]
refer to nlnet grant and to top-level bugreport
Luke Kenneth Casson Leighton [Sun, 9 Feb 2020 20:02:52 +0000 (20:02 +0000)]
whoops wrong name
Luke Kenneth Casson Leighton [Sun, 9 Feb 2020 19:55:13 +0000 (19:55 +0000)]
add empty news for now
Luke Kenneth Casson Leighton [Sun, 9 Feb 2020 19:54:38 +0000 (19:54 +0000)]
split out nmutil library based on ieee754fpu code
Luke Kenneth Casson Leighton [Sun, 9 Feb 2020 19:48:22 +0000 (19:48 +0000)]
first empty commit