soc.git
3 years agoDecode and fetch integer predicate registers
Cesar Strauss [Mon, 22 Mar 2021 00:26:11 +0000 (21:26 -0300)]
Decode and fetch integer predicate registers

3 years agoFix typo
Cesar Strauss [Sun, 21 Mar 2021 21:41:06 +0000 (18:41 -0300)]
Fix typo

3 years agoAdd unique name to decoded predication signals
Cesar Strauss [Sun, 21 Mar 2021 21:14:54 +0000 (18:14 -0300)]
Add unique name to decoded predication signals

3 years agoRevert removal of *.value from Enums
Cesar Strauss [Sun, 21 Mar 2021 20:53:21 +0000 (17:53 -0300)]
Revert removal of *.value from Enums

3 years agoFix syntax
Cesar Strauss [Sun, 21 Mar 2021 18:03:28 +0000 (15:03 -0300)]
Fix syntax

3 years agomore TODO comments
Luke Kenneth Casson Leighton [Sun, 21 Mar 2021 18:03:29 +0000 (18:03 +0000)]
more TODO comments

3 years agoadd for-loop pseudocode for CR predicate mask reading
Luke Kenneth Casson Leighton [Sun, 21 Mar 2021 14:48:01 +0000 (14:48 +0000)]
add for-loop pseudocode for CR predicate mask reading

3 years agocode comments in TestIssuer
Luke Kenneth Casson Leighton [Sun, 21 Mar 2021 13:25:26 +0000 (13:25 +0000)]
code comments in TestIssuer

3 years agoadjust syntax of SVP64 predicate test cas
Luke Kenneth Casson Leighton [Sun, 21 Mar 2021 13:18:30 +0000 (13:18 +0000)]
adjust syntax of SVP64 predicate test cas

3 years agonaah. back to "sv." syntax for SVP64 assembly
Luke Kenneth Casson Leighton [Sun, 21 Mar 2021 13:17:26 +0000 (13:17 +0000)]
naah.  back to "sv." syntax for SVP64 assembly

3 years agoStart work on the predicate fetch FSM
Cesar Strauss [Sun, 21 Mar 2021 13:02:19 +0000 (10:02 -0300)]
Start work on the predicate fetch FSM

After an instruction arrives, it will decode the SVP64 mask part
and will fetch the masks from the register files.
At the moment, it just returns the all ones mask.
The Issue FSM calls it, after receiving an instruction from Fetch, and
before entering execution vector loop.

3 years agoAdd predication test case, initially disabled
Cesar Strauss [Sun, 21 Mar 2021 11:44:09 +0000 (08:44 -0300)]
Add predication test case, initially disabled

Directly derived from a test in test_caller_svp64_predication.py
The goal is to incrementally develop the TestIssuer FSMs, until it passes.

3 years agoadd override for build commands powerpc64-linux-gnu-{ENVVAR}
Luke Kenneth Casson Leighton [Sun, 21 Mar 2021 11:07:59 +0000 (11:07 +0000)]
add override for build commands powerpc64-linux-gnu-{ENVVAR}

3 years agoenable -mregnames in assembly syntax for unit tests
Luke Kenneth Casson Leighton [Sun, 21 Mar 2021 10:55:01 +0000 (10:55 +0000)]
enable -mregnames in assembly syntax for unit tests

3 years agomore pseudocode in TestIssuer
Luke Kenneth Casson Leighton [Sat, 20 Mar 2021 18:58:54 +0000 (18:58 +0000)]
more pseudocode in TestIssuer

3 years agomove radixmmu to unit test format
Luke Kenneth Casson Leighton [Sat, 20 Mar 2021 18:51:41 +0000 (18:51 +0000)]
move radixmmu to unit test format

3 years agoadd harmless code and commented-out pseudocode for predication in TestIssuer
Luke Kenneth Casson Leighton [Sat, 20 Mar 2021 18:29:01 +0000 (18:29 +0000)]
add harmless code and commented-out pseudocode for predication in TestIssuer

3 years agosort out predicate zeroing in ISACaller
Luke Kenneth Casson Leighton [Sat, 20 Mar 2021 11:22:23 +0000 (11:22 +0000)]
sort out predicate zeroing in ISACaller

3 years agoattempting to add src/dest-zeroing to ISACaller
Luke Kenneth Casson Leighton [Sat, 20 Mar 2021 00:12:06 +0000 (00:12 +0000)]
attempting to add src/dest-zeroing to ISACaller

3 years agomore comments for TestIssuer when adding predication
Luke Kenneth Casson Leighton [Fri, 19 Mar 2021 23:40:38 +0000 (23:40 +0000)]
more comments for TestIssuer when adding predication

3 years agotestcase for _get_pgtable_addr
Tobias Platen [Fri, 19 Mar 2021 19:33:22 +0000 (20:33 +0100)]
testcase for _get_pgtable_addr

3 years agodecode predicate src/dest zeroing in SVP64RMModeDecode
Luke Kenneth Casson Leighton [Fri, 19 Mar 2021 19:12:11 +0000 (19:12 +0000)]
decode predicate src/dest zeroing in SVP64RMModeDecode

3 years agocomments for TestIssuer get_predint and get_predcr
Luke Kenneth Casson Leighton [Fri, 19 Mar 2021 14:45:01 +0000 (14:45 +0000)]
comments for TestIssuer get_predint and get_predcr

3 years agoadd more pieces of predication reading puzzle to TestIssuer
Luke Kenneth Casson Leighton [Fri, 19 Mar 2021 14:37:17 +0000 (14:37 +0000)]
add more pieces of predication reading puzzle to TestIssuer

3 years agocleanup TestIssuer (comments)
Luke Kenneth Casson Leighton [Fri, 19 Mar 2021 14:17:00 +0000 (14:17 +0000)]
cleanup TestIssuer (comments)

3 years agospelling
Luke Kenneth Casson Leighton [Fri, 19 Mar 2021 14:14:10 +0000 (14:14 +0000)]
spelling

3 years agocode-shuffle in TestIssuer, split out setting up peripherals
Luke Kenneth Casson Leighton [Fri, 19 Mar 2021 14:12:44 +0000 (14:12 +0000)]
code-shuffle in TestIssuer, split out setting up peripherals

3 years agomove duplicated code to a function in TestIssuer
Luke Kenneth Casson Leighton [Fri, 19 Mar 2021 14:04:23 +0000 (14:04 +0000)]
move duplicated code to a function in TestIssuer

3 years agomore hint/comments
Luke Kenneth Casson Leighton [Thu, 18 Mar 2021 21:26:04 +0000 (21:26 +0000)]
more hint/comments

3 years agocomments / code-shuffle
Luke Kenneth Casson Leighton [Thu, 18 Mar 2021 21:23:53 +0000 (21:23 +0000)]
comments / code-shuffle

3 years agoupdate TestIssuer comments
Luke Kenneth Casson Leighton [Thu, 18 Mar 2021 21:16:21 +0000 (21:16 +0000)]
update TestIssuer comments

3 years agoadd comments on most likely place to put predicate mask read-firing
Luke Kenneth Casson Leighton [Thu, 18 Mar 2021 20:02:32 +0000 (20:02 +0000)]
add comments on most likely place to put predicate mask read-firing

3 years agocomments TestIssuer, add a stub FSM
Luke Kenneth Casson Leighton [Thu, 18 Mar 2021 19:15:38 +0000 (19:15 +0000)]
comments TestIssuer, add a stub FSM

3 years agoadd MSR PR read in RADIXMMU ISACaller
Luke Kenneth Casson Leighton [Thu, 18 Mar 2021 18:45:38 +0000 (18:45 +0000)]
add MSR PR read in RADIXMMU ISACaller

3 years agore-add auto-generated file simplev.py to gitignore
Luke Kenneth Casson Leighton [Thu, 18 Mar 2021 18:34:07 +0000 (18:34 +0000)]
re-add auto-generated file simplev.py to gitignore
https://git.libre-soc.org/?p=soc.git;a=commitdiff;h=d3767842a2f8f66f9e3de882a36592bfa3d344b8;hp=3f8a17ca49a1cc9636b85b41b84a0a88476cbdf8

3 years agore-add nmigen-type-annotations with libre-soc url
Jacob Lifshay [Thu, 18 Mar 2021 16:42:45 +0000 (09:42 -0700)]
re-add nmigen-type-annotations with libre-soc url

3 years agoexperiment in radixmmu with returning addr_next (and some error messages)
Luke Kenneth Casson Leighton [Thu, 18 Mar 2021 14:42:40 +0000 (14:42 +0000)]
experiment in radixmmu with returning addr_next (and some error messages)

3 years agoadd sv_out2 to PowerDecode and PowerDecoder2
Luke Kenneth Casson Leighton [Thu, 18 Mar 2021 12:24:54 +0000 (12:24 +0000)]
add sv_out2 to PowerDecode and PowerDecoder2
used for 2nd write (currently LD/ST update only)

3 years agocross-reference to bug #619
Luke Kenneth Casson Leighton [Thu, 18 Mar 2021 12:15:00 +0000 (12:15 +0000)]
cross-reference to bug #619

3 years agoadd auto-generation of out2 column in SVP64RM
Luke Kenneth Casson Leighton [Thu, 18 Mar 2021 12:13:20 +0000 (12:13 +0000)]
add auto-generation of out2 column in SVP64RM
needed for PowerDecoder2 as well as microwatt svp64 vhdl generation

3 years agoremove nmigen-type-annotations temporarily
Luke Kenneth Casson Leighton [Thu, 18 Mar 2021 11:48:14 +0000 (11:48 +0000)]
remove nmigen-type-annotations temporarily

3 years agoremove nmigen-type-annotations temporarily
Luke Kenneth Casson Leighton [Thu, 18 Mar 2021 11:47:07 +0000 (11:47 +0000)]
remove nmigen-type-annotations temporarily

3 years agoadd option to move RS in CSV file reading, for compatibility with microwatt
Luke Kenneth Casson Leighton [Thu, 18 Mar 2021 11:22:05 +0000 (11:22 +0000)]
add option to move RS in CSV file reading, for compatibility with microwatt
decode1.vhdl;

3 years agocorrect comments
Luke Kenneth Casson Leighton [Wed, 17 Mar 2021 22:33:15 +0000 (22:33 +0000)]
correct comments

3 years agore-enable SVP64 ISACaller predicate tests
Luke Kenneth Casson Leighton [Wed, 17 Mar 2021 22:29:07 +0000 (22:29 +0000)]
re-enable SVP64 ISACaller predicate tests

3 years agoadd ascii graphic for extsw svp64 operation
Luke Kenneth Casson Leighton [Wed, 17 Mar 2021 22:25:21 +0000 (22:25 +0000)]
add ascii graphic for extsw svp64 operation

3 years agoadd more explanatory comments
Luke Kenneth Casson Leighton [Wed, 17 Mar 2021 22:21:12 +0000 (22:21 +0000)]
add more explanatory comments

3 years agoadd twin-predicated extsw SVP64 ISACaller unit test
Luke Kenneth Casson Leighton [Wed, 17 Mar 2021 22:15:58 +0000 (22:15 +0000)]
add twin-predicated extsw SVP64 ISACaller unit test

3 years agoadd SVP64 dststep incrementing in PowerDecoder2, Testissuer and ISACaller
Luke Kenneth Casson Leighton [Wed, 17 Mar 2021 21:29:49 +0000 (21:29 +0000)]
add SVP64 dststep incrementing in PowerDecoder2, Testissuer and ISACaller

3 years agoadd CR-based predication to ISACaller
Luke Kenneth Casson Leighton [Wed, 17 Mar 2021 20:40:49 +0000 (20:40 +0000)]
add CR-based predication to ISACaller

3 years agocleanup raduxmmu._walk_tree
Tobias Platen [Wed, 17 Mar 2021 19:13:40 +0000 (20:13 +0100)]
cleanup raduxmmu._walk_tree

3 years agocreate iterative mmu lookup loop
Tobias Platen [Wed, 17 Mar 2021 18:59:12 +0000 (19:59 +0100)]
create iterative mmu lookup loop

3 years agoadd SVP64 INT-style predication to ISACaller
Luke Kenneth Casson Leighton [Wed, 17 Mar 2021 15:20:02 +0000 (15:20 +0000)]
add SVP64 INT-style predication to ISACaller

3 years agoadd predication SVP64 unit test
Luke Kenneth Casson Leighton [Wed, 17 Mar 2021 14:13:02 +0000 (14:13 +0000)]
add predication SVP64 unit test

3 years agoadd predication read ports (CR and INT)
Luke Kenneth Casson Leighton [Wed, 17 Mar 2021 13:21:25 +0000 (13:21 +0000)]
add predication read ports (CR and INT)

3 years agowhoops shift has to be done at same bitwidth
Luke Kenneth Casson Leighton [Wed, 17 Mar 2021 13:16:24 +0000 (13:16 +0000)]
whoops shift has to be done at same bitwidth

3 years agosplit out new_lookup function
Luke Kenneth Casson Leighton [Wed, 17 Mar 2021 13:14:07 +0000 (13:14 +0000)]
split out new_lookup function

3 years agolink up SVP64 RM Mode decoding into PowerDecoder2
Luke Kenneth Casson Leighton [Wed, 17 Mar 2021 13:00:28 +0000 (13:00 +0000)]
link up SVP64 RM Mode decoding into PowerDecoder2

3 years agoadd priv and mode to RADIXMMU
Luke Kenneth Casson Leighton [Wed, 17 Mar 2021 12:46:54 +0000 (12:46 +0000)]
add priv and mode to RADIXMMU

3 years agoadd instr_fetch mode to ISACaller Mem and RADIXMMU
Luke Kenneth Casson Leighton [Wed, 17 Mar 2021 12:34:04 +0000 (12:34 +0000)]
add instr_fetch mode to ISACaller Mem and RADIXMMU

3 years agowhitespace
Luke Kenneth Casson Leighton [Wed, 17 Mar 2021 12:22:44 +0000 (12:22 +0000)]
whitespace

3 years agoadd in SVP64 RM Mode decoder
Luke Kenneth Casson Leighton [Wed, 17 Mar 2021 12:19:06 +0000 (12:19 +0000)]
add in SVP64 RM Mode decoder

3 years agoradixmmu: detect badtree
Tobias Platen [Tue, 16 Mar 2021 18:49:20 +0000 (19:49 +0100)]
radixmmu: detect badtree

3 years agoadd valid, leaf to loop
Tobias Platen [Tue, 16 Mar 2021 17:35:35 +0000 (18:35 +0100)]
add valid, leaf to loop

3 years agoUse symbolic values for subfields and bits
Cesar Strauss [Tue, 16 Mar 2021 10:55:48 +0000 (07:55 -0300)]
Use symbolic values for subfields and bits

3 years agoAdd subfield and bit definitions for the SVP64 RM mode field
Cesar Strauss [Tue, 16 Mar 2021 10:48:05 +0000 (07:48 -0300)]
Add subfield and bit definitions for the SVP64 RM mode field

3 years agoDefine and initialise the mode variable, to be used later on
Cesar Strauss [Tue, 16 Mar 2021 00:12:11 +0000 (21:12 -0300)]
Define and initialise the mode variable, to be used later on

3 years agoRename class so it does not clash with the enum
Cesar Strauss [Tue, 16 Mar 2021 00:02:28 +0000 (21:02 -0300)]
Rename class so it does not clash with the enum

3 years agoFix import
Cesar Strauss [Mon, 15 Mar 2021 22:33:34 +0000 (19:33 -0300)]
Fix import

3 years agoadd rpte bitfields valid and leaf
Tobias Platen [Mon, 15 Mar 2021 18:49:44 +0000 (19:49 +0100)]
add rpte bitfields valid and leaf

3 years agoremove "sv." and replace with "sv" in all SVP64Asm
Luke Kenneth Casson Leighton [Sun, 14 Mar 2021 14:55:28 +0000 (14:55 +0000)]
remove "sv." and replace with "sv" in all SVP64Asm

3 years agoremove "sv." and replace with "sv" in all SVP64Asm
Luke Kenneth Casson Leighton [Sun, 14 Mar 2021 14:54:45 +0000 (14:54 +0000)]
remove "sv." and replace with "sv" in all SVP64Asm

3 years agoActivate the VL==0 loop with any SVP64 prefix whatsoever
Cesar Strauss [Sun, 14 Mar 2021 13:46:08 +0000 (10:46 -0300)]
Activate the VL==0 loop with any SVP64 prefix whatsoever

Besides agreeing with documentation, this will ease doing the VL==0
loop entirely on the Fetch FSM, since no opcode decoding is needed.

3 years agoadd setvl unit test assertions, add 2nd test
Luke Kenneth Casson Leighton [Sat, 13 Mar 2021 17:07:09 +0000 (17:07 +0000)]
add setvl unit test assertions, add 2nd test

3 years agoget first revision setvl operational in ISACaller
Luke Kenneth Casson Leighton [Sat, 13 Mar 2021 16:10:02 +0000 (16:10 +0000)]
get first revision setvl operational in ISACaller

3 years agoadd setvl-to-long converter in SVP64Asm (sigh)
Luke Kenneth Casson Leighton [Sat, 13 Mar 2021 13:35:30 +0000 (13:35 +0000)]
add setvl-to-long converter in SVP64Asm (sigh)

3 years agoadd setvl unit test
Luke Kenneth Casson Leighton [Sat, 13 Mar 2021 12:22:16 +0000 (12:22 +0000)]
add setvl unit test

3 years agoupdate submodule to include simplev setvl
Luke Kenneth Casson Leighton [Sat, 13 Mar 2021 12:20:02 +0000 (12:20 +0000)]
update submodule to include simplev setvl

3 years agoinclude SVSTATE in namespace, passing to ISACaller
Luke Kenneth Casson Leighton [Sat, 13 Mar 2021 11:33:53 +0000 (11:33 +0000)]
include SVSTATE in namespace, passing to ISACaller

3 years agoupdate submodule
Jacob Lifshay [Fri, 12 Mar 2021 22:55:24 +0000 (14:55 -0800)]
update submodule

3 years agoadd setvl to decoder
Jacob Lifshay [Fri, 12 Mar 2021 22:52:16 +0000 (14:52 -0800)]
add setvl to decoder

3 years agoautoformat code
Jacob Lifshay [Fri, 12 Mar 2021 22:50:01 +0000 (14:50 -0800)]
autoformat code

3 years agoadd OP_SETVL to MicrOp in power_enums.py
Luke Kenneth Casson Leighton [Fri, 12 Mar 2021 21:50:44 +0000 (21:50 +0000)]
add OP_SETVL to MicrOp in power_enums.py

3 years agoadd ability to set and distinguish RT=0 (RT_OR_ZERO) to OutSel enum
Luke Kenneth Casson Leighton [Fri, 12 Mar 2021 21:41:57 +0000 (21:41 +0000)]
add ability to set and distinguish RT=0 (RT_OR_ZERO) to OutSel enum

3 years agouse PowerDecoder2.loop_continue instead of no_out_vec
Luke Kenneth Casson Leighton [Fri, 12 Mar 2021 15:02:06 +0000 (15:02 +0000)]
use PowerDecoder2.loop_continue instead of no_out_vec

3 years agoremove old code
Luke Kenneth Casson Leighton [Fri, 12 Mar 2021 14:17:17 +0000 (14:17 +0000)]
remove old code

3 years agoremove old code
Luke Kenneth Casson Leighton [Fri, 12 Mar 2021 14:16:10 +0000 (14:16 +0000)]
remove old code

3 years agoremove old code
Luke Kenneth Casson Leighton [Fri, 12 Mar 2021 14:12:41 +0000 (14:12 +0000)]
remove old code

3 years agoadd more sophisticated checking of whether SVP64 loop should continue
Luke Kenneth Casson Leighton [Fri, 12 Mar 2021 12:13:58 +0000 (12:13 +0000)]
add more sophisticated checking of whether SVP64 loop should continue
PowerDecoder2

3 years ago**FOR NOW** LD/ST relies on detection of twin-predication to determine
Luke Kenneth Casson Leighton [Fri, 12 Mar 2021 12:03:39 +0000 (12:03 +0000)]
**FOR NOW** LD/ST relies on detection of twin-predication to determine
if it should continue looping.
this needs double-checking

3 years agodecoding of svp64 reg by name has to occur after immediate is extracted
Luke Kenneth Casson Leighton [Fri, 12 Mar 2021 12:00:58 +0000 (12:00 +0000)]
decoding of svp64 reg by name has to occur after immediate is extracted
otherwise tries to identify D(RA) as a GPR which of course fails

3 years agoadd forgotten PO (primary opcode) field to DecodeFields
Jacob Lifshay [Fri, 12 Mar 2021 05:50:42 +0000 (21:50 -0800)]
add forgotten PO (primary opcode) field to DecodeFields

3 years agoBring a few test cases from test_caller_64.py
Cesar Strauss [Thu, 11 Mar 2021 22:52:52 +0000 (19:52 -0300)]
Bring a few test cases from test_caller_64.py

1) Test early out when destination is not a vector
2) Do not increment source register number for scalar operand

3 years agoTest case for two successive SV instructions
Cesar Strauss [Thu, 11 Mar 2021 22:40:47 +0000 (19:40 -0300)]
Test case for two successive SV instructions

This checks that SRCSTEP is reset properly between instructions.

3 years agoadd link of RA_OR_ZERO SVP64 detection
Luke Kenneth Casson Leighton [Thu, 11 Mar 2021 20:01:47 +0000 (20:01 +0000)]
add link of RA_OR_ZERO SVP64 detection

3 years agoadd detection of whether *full* 7-bit of RA is zero/non-zero
Luke Kenneth Casson Leighton [Thu, 11 Mar 2021 19:50:19 +0000 (19:50 +0000)]
add detection of whether *full* 7-bit of RA is zero/non-zero
this because RA_OR_ZERO in PowerDecoder2 needs to test if the full
SVP64-extended register is zero

3 years agoadd in SVP64 LD/ST basic test for ISACaller
Luke Kenneth Casson Leighton [Thu, 11 Mar 2021 18:32:51 +0000 (18:32 +0000)]
add in SVP64 LD/ST basic test for ISACaller

3 years agowhoops sort out when svstate not active in ISACaller
Luke Kenneth Casson Leighton [Thu, 11 Mar 2021 18:29:26 +0000 (18:29 +0000)]
whoops sort out when svstate not active in ISACaller

3 years agowhoops PIDR is defined as 32-bits in SPRs.csv (and spec)
Luke Kenneth Casson Leighton [Thu, 11 Mar 2021 18:19:43 +0000 (18:19 +0000)]
whoops PIDR is defined as 32-bits in SPRs.csv (and spec)

3 years agoadd understanding of LDST immediates to SVP64ASM
Luke Kenneth Casson Leighton [Thu, 11 Mar 2021 18:15:06 +0000 (18:15 +0000)]
add understanding of LDST immediates to SVP64ASM