radeon/uvd: set correct vega10 db pitch alignment

Create new function to get correct alignment based on Asics, and change
the corresponding decode message buffer and dpb buffer size calculations

Signed-off-by: Boyuan Zhang <boyuan.zhang@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>

radeon/vce: add vce support for firmware 53.19.4

v2: squashed with other similar commits

Signed-off-by: Leo Liu <leo.liu@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>

radeon/vce: adapt gfx9 surface to vce

Signed-off-by: Leo Liu <leo.liu@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>

winsys/surface: add height pitch for gfx9

Signed-off-by: Leo Liu <leo.liu@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>

radeon/uvd: clear message buffer when reuse

As required by firmware

Signed-off-by: Leo Liu <leo.liu@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>

radeon/uvd: adapt gfx9 surface to uvd

Signed-off-by: Leo Liu <leo.liu@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>

radeon/uvd: add uvd soc15 register

Signed-off-by: Leo Liu <leo.liu@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>

radeonsi/gfx9: disable features that don't work

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

radeonsi/gfx9: only allow GL 3.1

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

radeonsi/gfx9: add linear address computations for texture transfers

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

radeonsi/gfx9: don't generate LS and ES states

these shaders don't exist on GFX9

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

radeonsi/gfx9: SPI_SHADER_USER_DATA changes

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

winsys/amdgpu: set/get BO tiling flags for GFX9

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

radeonsi/gfx9: handle pitch and offset overrides for texture_from_handle

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

radeonsi/gfx9: set/validate GFX9 BO metadata

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

radeonsi/gfx9: add radeon_surf.gfx9.surf_offset

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

radeonsi/gfx9: don't write mipmap level offsets to BO metadata

GFX9 doesn't have (usable) mipmap offsets.

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

radeonsi/gfx9: flush CB & DB caches with an EOP TS event

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

radeonsi/gfx9: use ACQUIRE_MEM

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

radeonsi/gfx9: only use CE RAM for most-used descriptors

because the CE RAM size decreased to 4 KB.

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

radeonsi/gfx9: emit FLUSH_DFSM where required

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

radeonsi/gfx9: emit BREAK_BATCH in emit_framebuffer_state

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

radeonsi/gfx9: fix MIP0_WIDTH & MIP0_HEIGHT for compressed texture blits

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

radeonsi/gfx9: fix textureSize/imageSize for 1D textures

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

radeonsi/gfx9: add a workaround for 1D depth textures

The same workaround is used by Vulkan.

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

radeonsi/gfx9: enable clamping for Z UNORM formats promoted to Z32F

so that shaders don't have to do it.

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

radeonsi/gfx9: image descriptor changes in mutable fields

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

radeonsi/gfx9: FMASK image descriptor changes

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

radeonsi/gfx9: image descriptor changes in immutable fields

The border color swizzle logic was copied from Vulkan. It doesn't make any
sense to me, but it passes all piglits except the stencil ones.

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

radeonsi/gfx9: DB changes

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

radeonsi/gfx9: CB changes

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

radeonsi/gfx9: do DCC clears on non-mipmapped textures only

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

radeonsi/gfx9: update can_sample_z/s flags

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

radeonsi/gfx9: pass correct parameters to buffer_get_handle

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

radeonsi/gfx9: update si_set_optimal_micro_tile_mode

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

radeonsi/gfx9: don't check array_mode for allowing TC-compatible HTILE

GFX9 supports this with all modes except linear.

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

radeonsi/gfx9: update HTILE/CMASK/FMASK allocators

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

radeonsi/gfx9: stub testdma - array_mode_to_string

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

radeonsi/gfx9: update r600_print_texture_info

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

gallium/radeon: move pre-GFX9 radeon_bo_metadata.* to u.legacy.*

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

winsys/amdgpu: set num_tile_pipes, pipe_interleave_bytes for GFX9

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

winsys/amdgpu: wire up new addrlib for GFX9

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

winsys/amdgpu: update amdgpu_addr_create for GFX9

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

winsys/amdgpu: rename GFX6 surface functions

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

gallium/radeon: add GFX9 surface info to radeon_surf

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

gallium/radeon: move pre-GFX9 radeon_surf.* members to radeon_surf.u.legacy.*

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

radeonsi/gfx9: allow Z16_UNORM for TC-compatible HTILE

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

radeonsi/gfx9: draw changes

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

radeonsi/gfx9: pad shader binaries by 128 bytes

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

radeonsi/gfx9: trivial shader and ring changes

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

radeonsi/gfx9: sampler state changes

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

radeonsi/gfx9: add a scissor bug workaround

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

radeonsi/gfx9: rasterizer changes

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

radeonsi/gfx9: disable the 2-bit format fetch fix

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

radeonsi/gfx9: set NUM_RECORDS correctly

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

radeonsi/gfx9: ELEMENT_SIZE change

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

radeonsi/gfx9: enable ETC2

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

radeonsi/gfx9: disable RB+ on Vega10

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

radeonsi/gfx9: init_config changes

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

radeonsi/gfx9: don't set PA_SC_RASTER_CONFIG*

The registers don't exist on GFX9.

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

radeonsi/gfx9: Gather4 no longer needs the workaround

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

radeonsi/gfx9: CP DMA changes

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

radeonsi/gfx9: query changes - EVENT_WRITE and SET_PREDICATION

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

radeonsi/gfx9: EVENT_WRITE_EOP -> RELEASE_MEM

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

radeonsi/gfx9: INDIRECT_BUFFER change

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

radeonsi/gfx9: enable SDMA buffer copying & clearing

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

radeonsi/gfx9: handle GFX9 in a few places

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

radeonsi/gfx9: don't read back non-existent SRBM registers

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

radeonsi/gfx9: add IB parser support

Both GFX6 and GFX9 fields are printed next to each other in parsed IBs.

The Python script parses both headers like one stream and tries to merge
all definitions.

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

radeonsi/gfx9: set the LLVM processor, require LLVM 5.0

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

radeonsi/gfx9: add GFX9 and VEGA10 enums

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

amd: GFX9 packet changes

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

amd: define event types for GFX9

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

amd: add texture format definitions for GFX9

the DATA_FORMAT and NUM_FORMAT fields are the same, but some of the enums
differ, thus add GFX6 and GFX9 suffixes, so that the IB parser can show
enums for both.

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

amd: resolve remaining definition conflicts with gfx9d.h

Add _GFX6 and _GFX9 suffixes to conflicting definitions.

sid.h and gfx9d.h can now be included in the same file.

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

amd: normalize register definition formatting

This resolves trivial conflicts with gfx9d.h caused by different formatting.
Some fields are also renamed.

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

amd: import GFX9 register definitions

Acked-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

radeonsi: code shuffling in si_init_depth_surface

use fewer local variables, re-order the assignments, so that the GFX9 diff
is smaller here.

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

amd/addrlib: silence warnings

amd/addrlib: import gfx9 support

amd/addrlib: Not all ETC2 formats are 128bpp... add new ETC2 formats to differentiate between 64 and 128bpp formats.

amd/addrlib: Fix selection of swizzle modes for 3D compressed images.

amd/addrlib: Add support for ETC2 and ASTC formats.

amd/addrlib: Bump version to 6.02

amd/addrlib: Adjust slie size after pitch and actual height adjustment

amd/addrlib: Apply input pitch after internal pitch aligning

amdgpu/addrlib: Bump version to 6.01

Signed-off-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

amdgpu/addrlib: Seperate 2 dcc related workarounds by different flags

1) dccCompatible for padding MSAA surface to support fast clear
2) dccPipeWorkaround for padding surface to support dcc

amdgpu/addrlib: Fix the issue that tcCompatible HTILE slice size is not calculated correctly

amdgpu/addrlib: Add a new output flag to notify client that the returned tile index is for PRT on SI

If this flag is set for mip0, client should set prt flag for sub mips,
so that address lib can select the correct tile index for sub mips.

amdgpu/addrlib: add matchStencilTileCfg and tcCompatible fixes

The usage should be client first call AddrComputeSurfaceInfo() on
depth surface with flag "matchStencilTilecfg", AddrLib will use
2DThin1 tile index for depth as much as possible and do not down grade
unless alignment requirement cannot be met.

1. If there is a matched 2DThin1 tile index for stencil which make
sure they will share same tile config parameters, then return the
stencil 2DThin1 tile index as well.
2. If using 2DThin1 tile mode cannot make sure such thing happen, and
TcCompatible flag was set, then ignore this flag then try 2DThin1 tile
mode for depth and stencil again.
3. If 2DThin1 tile mode cannot make sure depth and stencil to have
same tile config parameters, then down grade depth surface tile mode
to 1DThin1.
4. If depth surface's tile mode was 1DThin1, then return 1DThin1 tile
index for stencil.
5. If depth surface's tile mode is PRT, then return invalid tile index
to stencil since their tile config parameters will never be met.

Client driver then check the returned tile index of stencil -- if it
is not invalid tile index, then call AddrComputeSurfaceInfo() on
stencil surface with the returned stencil tile index to get full
output information. Please note, client needs to set flag
"useTileIndex" when AddrLib get created.

amdgpu/addrlib: Adjust bank equation bit order based on macro tile aspect ratio settings

By this way, we can have valid equation for 2D_THIN1 tile mode.
Add flag "preferEquation" to return equation index without adjusting
input tile mode.

amdgpu/addrlib: do some tile mode conversions to display surface

amdgpu/addrlib: Check prt flag for PRT_THIN1 extra padding for DCC.

amdgpu/addrlib: Add new flags minimizePadding and maxBaseAlign

1) minimizePadding - Use 1D tile mode if padded size of 2D is bigger
than 1D
2) maxBaseAlign - Force PRT tile mode if macro block size is bigger than
requested alignment.

Also, related changes to tile mode optimization for needEquation.

amdgpu/addrlib: Always returns pixelPitch in original pixels

amdgpu/addrlib: fix crash on allocation failure

amdgpu/addrlib: Add flag to report if a surface can have dcc ram

amdgpu/addrlib: support non-power2 height alignment (for linear surface)

amdgpu/addrlib: Fix family setting for VI and CZ ASICs