radeonsi: change PIPE_SHADER to MESA_SHADER (si_shader_dump_disassembly)

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6340>

radeonsi: remove unused si_shader_context::type

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6340>

radeonsi: change PIPE_SHADER to MESA_SHADER (si_get_shader_part)

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6340>

radeonsi: change PIPE_SHADER to MESA_SHADER (si_compile_llvm)

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6340>

radeonsi: change PIPE_SHADER to MESA_SHADER (debug flags)

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6340>

radeonsi: change PIPE_SHADER to MESA_SHADER (si_shader_context::type)

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6340>

radeonsi: change PIPE_SHADER to MESA_SHADER (si_shader_selector::type)

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6340>

radeonsi: simplify handling color interp modes in si_emit_spi_map

Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6340>

radeonsi: don't execute LDS stores for TCS outputs that are never read

This is a per-component version of the previous mechanism.

Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6340>

radeonsi: don't lower indirect IO in GLSL

Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Reviewed-by: Connor Abbott <cwabbott0@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6445>

radeonsi: remove in/out/uniform variables from NIR after lowering IO

Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Reviewed-by: Connor Abbott <cwabbott0@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6445>

radeonsi: lower IO intrinsics - complete rewrite of input/output scanning

Input and output info is gathered from intrinsics. nir_variables are
ignored (and we'll remove them anyway).

This is a prerequisite for ACO, but also makes the IR prettier.
The ac_nir_to_llvm change has to be in this commit.

Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Reviewed-by: Connor Abbott <cwabbott0@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6445>

ac/nir: handle all lowered IO intrinsics

Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Connor Abbott <cwabbott0@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6445>

radeonsi: clean up code for loading VS inputs

Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Reviewed-by: Connor Abbott <cwabbott0@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6445>

radeonsi: get color interpolation info from shader_info

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Reviewed-by: Connor Abbott <cwabbott0@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6445>

radeonsi: don't crash if input_usage_mask is 0 for a VS input

This will start happening with the lowered IO intrinstics and new scanning
code.

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Reviewed-by: Connor Abbott <cwabbott0@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6445>

freedreno: fence_server_sync() fixes

Two potential problems, batch re-ordering doesn't really play nicely
with fence_server_sync(), so when we switch away from one batch, detect
the case that we need to sync, and if so flush.  The alternative of
trying to track that later batches depend on an earlier batch that had
an in-fence is hairy, and the normal use-case would be to sync at the
beginning of the frame.

But this brings up the second problem, which is that typically we'll get
told to sync on an in-fence before the first draw, which means before
mesa/st flushes down the framebuffer state to the driver.  Which means
we don't yet have the correct batch to attach the fence to.  So we need
to track the in-fence on the context, and transfer it to the batch
before draws, etc.

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6575>

freedreno: Fix missing rsc->seqno updates

There were a couple paths where we weren't getting valid seqno's, which
are supposed to be updated whenever the backing bo is set/changed.  So
wrap that up in a helper to make it harder to mess up.

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6575>

docs: shift 20.2 rc dates by two weeks to match reality

The release candidates have slipped by a couple of weeks, so let's fix
the dates in the calendar.

Signed-off-by: Eric Engestrom <eric@engestrom.ch>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6574>

docs: update calendar and link releases notes for 20.1.7

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6573>

docs: add release notes for 20.1.7

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6573>

iris: Re-emit push constants if we have a varying workgroup size

Fixes: 33c61eb2f10526 "iris: Implement ARB_compute_variable_group_size"
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6570>

intel/nir: Lower load_num_work_groups to 32-bit if needed

For OpenCL-style kernels, this builtin is 64-bit.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6570>

intel/fs: Use a single untyped surface read for load_num_work_groups

There's no good reason to split this into three.  Sure, CS indirects are
only guaranteed by the spec to be DWORD aligned, but that's all untyped
surface reads require anyway.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6570>

intel/fs: Don't copy-propagate stride=0 sources into ddx/ddy

This can come up if, for instance, the shader does a derivative of a
uniform or flat input.  Ideally, NIR would use divergence analysis to
get rid of the derivative in this case but it doesn't right now.  This
fixes a crash in F1 2017.

Cc: mesa-stable@lists.freedesktop.org
Reported-by: Marcin Ślusarz <marcin.slusarz@intel.com>
Tested-by: Marcin Ślusarz <marcin.slusarz@intel.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6564>

st/mesa: fix lowered IO - don't call st_nir_assign_vs_in_locations twice

If IO is lowered, the second call is a no-op, which breaks:
   spec@!opengl 1.1@gl-1.1-color-material-unused-normal-array

Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6540>

nir: fix a bug in is_dual_slot in nir_io_add_const_offset_to_base

Fixes: 01ab308edc "nir: update IO semantics in nir_io_add_const_offset_to_base"
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6540>

iris: Patch constant data pointers into shaders

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6244>

anv: Patch constant data pointers into shaders with using softpin

When we have softpin, we know the address of the shader constant data at
shader upload time because it's sitting at the end of the shader.  This
commit changes ANV to use patch constants to embed the address in the
shader patch the right address in at upload time.  This allows us to
avoid having to set up a UBO binding on-the-fly for shader constants.

This commit uses an A64 message but it's quite possible that we could
also use an A32 message and make the dataport do the 64-bit add for us.
However, load_global is what we have right now so it was easier to just
use that.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6244>

nir/builder: Add load/store_global helpers

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6244>

anv: Properly cache brw_stage_prog_data::relocs

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6244>

intel/fs: Add support for a new load_reloc_const intrinsic

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6244>

intel/eu: Add a mechanism for emitting relocatable constant MOVs

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6244>

intel/eu: Include brw_compiler.h in brw_eu.h

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6244>

anv: Stop storing the shader constant data side-band

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6244>

intel/fs,vec4: Stuff the constant data from NIR in the end of the program

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6244>

intel/eu: Add some new helpers

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6244>

iris: Use gen_disassemble

This one doesn't require the program size and so it won't mess up if we
have a bunch of constant data at the end.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6244>

intel/compiler: Get rid of struct gen_disasm

It's just a container around a devinfo.  The one useful purpose it did
serve is that gen_disasm_create initialized the compaction table
singletons.  Now that those no longer exist, this isn't necessary.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6244>

intel/compiler: Get rid of the global compaction table pointers

With discrete GPUs, it's going to be possible to have GPUs from two
different hardware generations in the machine at the same time.  Global
singletons like this aren't going to fly.  Have a struct containing the
pointers which gets initialized once per shader disassemble instead.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6244>

spirv: Deal with glslang not setting NonUniform on constructors.

Especially a problem for OpImage/OpSampledImage. Note that the problem
doesn't seem to be propagation through glslang, but only in emitting
the SPIR-V. So it is fine if we are somewhat lossy in handling this, as
long as direct Op(Sampled)Image -> texture op chains work.

Fixes: af81486a8cd "spirv: Simplify our handling of NonUniform"
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/3406
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6451>

spirv: Deal with glslang bug not setting the decoration for stores.

Fixes: af81486a8cd "spirv: Simplify our handling of NonUniform"
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6451>

radv: Avoid deadlock on bo_list.

With the kernel timeline sysncobj changes, the kernel submits do
not necessarily happen in global vkQueueSubmit order. Which should
be fine, we added the appropriate waits for that. (See
DRM_SYNCOBJ_WAIT_FLAGS_WAIT_FOR_SUBMIT in the winsys)

However, all kernel submissions take a lock on the bo_list mutex,
and since we do the wait in the winsys, we wait while having the
bo_list mutex held. This means that as soon as a wait and a signal
submission are out of order we have a deadlock on the bo_list mutex
and the wait.

Solution is to use a shared reader lock during the kernel submission,
as we only need read access for the submission.

Fixes: 6bc5ce7a91d "radv: Add timeline syncobj for timeline semaphores."
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/3446
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6478>

radv: Fix threading issue with submission refcounts.

If decrement == 0 then:

- it isn't safe to access the submission
- even if it is, checking that the result of the atomic_sub is 0
  doesn't given an unique owner anymore.

So skip it. The submission always starts out with refcount >= 1,
so first one to decrement to 0 still get dibs on executing it.

Fixes: 4aa75bb3bdd "radv: Add wait-before-submit support for timelines."
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6478>

intel/tools: Disassemble WAIT's argument as a destination

WAIT takes a notification register as a destination and a src0 argument.
Since the same notification register is specified in both fields, we
treat it as a special case and disassemble it only once.

If we disassemble it as if it is a source register, its scalar region
will be printed as <0,1,0>. This causes difficulties round-tripping
through the assembler <-> disassembler because that is not an acceptable
destination region. If we instead disassemble the destination, we
instead get a <1> region which is an acceptable and equivalent region
for source and destination.

The test .asm files are regenerated by round-tripping them through the
assembler/disassembler. Note that the <0> region in the tests was a
harmless mistake: the compiler translated it to a <0,1,0> source region
and a <1> destination region, since <0> isn't valid.

Reviewed-by: Sagar Ghuge <sagar.ghuge@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6543>

gallium/tgsi_exec: Fix up NumOutputs counting

We can get duplicate declarations for an index (for example dvec3 + float
packed into 2 vec4s, the second one won't pack into the first's array
decl), and we'd end up stepping by the wrong amount in GS vtx/prim emit.

Fixes vs-gs-fs-double, sso-vs-gs-fs-array-interleave piglit tests.

Fixes: 49155c3264d0 ("draw/tgsi: fix geometry shader input/output swizzling")
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6567>

gallium/tgsi_exec: Add missing DFLR opcode support.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6567>

nir/clone: Add a helper for cloning most instruction types

@anholt needed it for nir_to_tgsi, and the desire comes up frequently.

Reviewed-by: Eric Anholt <eric@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6567>

nir/opt_vectorize: Add a callback for filtering of vectorizing.

For NIR-to-TGSI, we don't want to revectorize 64-bit ops that we split to
scalar beyond vec2 width.  We even have some ops that we would rather
retain as scalar due to TGSI opcodes being scalar, or having more unusual
requirements.

This could be used to do the vectorize_vec2_16bit filtering, but that
shader compiler option is also used in algebraic so leave it in place for
now.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6567>

nir: Add simplistic lowering for bany_equal/ball_inequal.

It would be nice if we could do swizzling of an expression on the
replacement side so that we could have a single ieq/ine of the vector
after CSE.  However, if you do want vector operations, nir_opt_vectorize()
does just fine.

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6567>

gallium/ureg: Set the next shader stage from the shader info.

Saves a loop over the linked shaders in glsl_to_tgsi which the GLSL linker
has already done for us.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6567>

gallium/tgsi: Add a helper for initializing ureg from a shader_info.

This moves a bunch of code from glsl_to_tgsi that will be reused by
tgsi-to-nir.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6567>

gallium/tgsi: Add some missing opcodes to tgsi_ureg.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6567>

gallium/tgsi: Add support for PRIMITIVEID as a system value.

NIR always represents this as a system value, so for NIR-to-TGSI we need
this support.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6567>

gallivm: Report the unsupported intrinsic instead of just assert(0);

Tripped over this in rendermode with softpipe NIR.

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6567>

ci: Do not create manual test-docs job in post-merge pipelines

Only in pre-merge pipelines for MRs, or in pipelines for forked project
branches.

Having the manual job in post-merge pipelines prevented the pages job
from running automatically as well, which could prevent the public
website from getting updated.

Acked-by: Daniel Stone <daniels@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6534>

intel/fs,vec4: remove unused assignments

Reported by Coverity.

Signed-off-by: Marcin Ślusarz <marcin.slusarz@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6126>

intel/compiler: mark debug constant as const

Should quiet Coverity's "'Constant' variable guards dead code".

Signed-off-by: Marcin Ślusarz <marcin.slusarz@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6126>

intel/compiler/test: use TEST_DEBUG env var consistently

Other tests use the same environment variable to decide whether they
should print debugging information.

Will quiet Coverity's "'Constant' variable guards dead code".

Signed-off-by: Marcin Ślusarz <marcin.slusarz@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6126>

intel/perf: don't generate logically dead code

When divisor is constant integer != 0 there's no point in checking
whether it's 0.

Complained about by Coverity.

Signed-off-by: Marcin Ślusarz <marcin.slusarz@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6126>

i965: verify format width in blorp_get_client_bo

Coverity complains about possible "Division or modulo by zero".

Signed-off-by: Marcin Ślusarz <marcin.slusarz@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6126>

iris: verify color component width in convert_fast_clear_color

Coverity complains about possible 2^32-1 bit shift.

Signed-off-by: Marcin Ślusarz <marcin.slusarz@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6126>

iris: handle os_dupfd_cloexec failure

Found by Coverity.

Signed-off-by: Marcin Ślusarz <marcin.slusarz@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6126>

freedreno/computerator: Use a render node

Fixes headless systems.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6562>

intel/compiler: Fix pointer arithmetic when reading shader assembly

start_offset is a byte offset.

Fixes: 04a995158084acbd1917b4c7e0f8d381e1c9222d
Signed-off-by: Danylo Piliaiev <danylo.piliaiev@globallogic.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6557>

mesa/st: Don't set alpha if ALPHA_TEST is lowered

When PIPE_CAP_ALPHA_TEST is zero, the driver does not support alpha
testing, so alpha shouldn't be set. In particular, alpha.enable should
be zero, since logically alpha testing is not used in the ZSA CSO when
it's lowered in the fragment shader key.

Fixes failing asserts in kicad, rvgl, etc with Panfrost since 6afd4ad.
(We could remove the assert in panfrost instead, but logically setting
alpha.enabled on top of lowering the shader seems wrong?)

As Erik pointed out, this should improve CSO cache behaviour.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reported-by: Icecream95 <ixn@keemail.me>
Tested-by: Urja Rannikko <urjaman@gmail.com>
Tested-by: Robin Murphy <robin.murphy@arm.com>
Reviewed-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Fixes: 6afd4addefa ("panfrost: Simplify depth/stencil/alpha")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6523>

turnip: Implement VK_EXT_host_query_reset

Signed-off-by: Hyunjun Ko <zzoon@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6299>

turnip: Support pipeline statistics query

Signed-off-by: Hyunjun Ko <zzoon@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6299>

turnip: Refactor structs of tu_query

Since there are different number of results depending on query types,
this patch removes the result field out of the common struct and defines
query-specific results in each type of query struct.

Signed-off-by: Hyunjun Ko <zzoon@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6299>

intel/assembler: Add labels support

Use labels instead of numeric JIP/UIP offsets.
Works for gen6+.

v2:
 - Change asm tests to use labels on gen6+
 - Remove usage of relative offsets on gen6+
 - Consider brw_jump_scale when setting relative offset
 - Return error if there is a JIP/UIP label without matching target
 - Fix matching of label tokens

Signed-off-by: Danylo Piliaiev <danylo.piliaiev@globallogic.com>
Reviewed-by: Sagar Ghuge <sagar.ghuge@intel.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4245>

intel/disasm: Label support in shader disassembly for UIP/JIP

Shader instructions which use UIP/JIP now get formatted with a label
in addition with immediate value, labels have "LABEL%d" format.

v2: - Consider brw_jump_scale when calculating label's offset

From: "Lonnberg, Toni" <toni.lonnberg@intel.com>
Signed-off-by: Danylo Piliaiev <danylo.piliaiev@globallogic.com>
Reviewed-by: Sagar Ghuge <sagar.ghuge@intel.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4245>

intel/disasm: brw_label and support functions

Pre-work for shader disassembly label support.

Introduction of the structures and functions used by the shader disassembly
jump target labeling.

From: "Lonnberg, Toni" <toni.lonnberg@intel.com>
Signed-off-by: Danylo Piliaiev <danylo.piliaiev@globallogic.com>
Reviewed-by: Sagar Ghuge <sagar.ghuge@intel.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4245>

intel/disasm: Change visibility of has_uip and has_jip

Pre-work for shader disassembly label support.

From: "Lonnberg, Toni" <toni.lonnberg@intel.com>
Signed-off-by: Danylo Piliaiev <danylo.piliaiev@globallogic.com>
Reviewed-by: Sagar Ghuge <sagar.ghuge@intel.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4245>

anv: refresh cached current batch bo after emitting some commands

Fixes crashes in:
- Rise of the Tomb Rider (on benchmark start)
- Total War: Three Kingdoms (on game start)
- Total War: Warhammer II (on game start)

Fixes: 34a0ce58c7f ("anv: add a new execution mode for secondary command buffers")
Signed-off-by: Marcin Ślusarz <marcin.slusarz@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6546>

radeonsi: use radeonsi_clamp_div_by_zero for SPECviewperf13, Road Redemption

Fixes SPECviewperf 13 creo rendering.

Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/2639
Cc: mesa-stable
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6259>

radeonsi,driconf: add clamp_div_by_zero option

Cc: mesa-stable
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6259>

ac/llvm: add option to clamp division by zero

Replace div(x) by min(div(x), FLT_MAX)) to avoid getting a NaN result
when x is 0.

A cheaper alternative would be to use legacy mult instructions but they're
not exposed by LLVM.

Cc: mesa-stable
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6259>

radeonsi: enable PIPE_CAP_NO_CLIP_ON_COPY_TEX

This fixes specviewperf13 catia test rendering.

Cc: mesa-stable
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6259>

mesa/st: introduce PIPE_CAP_NO_CLIP_ON_COPY_TEX

If supported this means that src_x/src_y/width/height parameters of
CopyTex functions will not be clipped using the read framebuffer's dimensions.

Cc: mesa-stable
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6259>

gallium/swr: Fix compilation TCS/TES compilation issues

Gallvm API changes in TCS/TES, but the compilation worked
for older LLVM APIs. With LLVM 12 update is needed.

Reviewed-by: Krzysztof Raszkowski <krzysztof.raszkowski@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6554>

gallium/swr: Fix compilation with LLVM 12

Update to reflect changes in VectorType and ElementCount APIs

Closes: #3457
Reviewed-by: Krzysztof Raszkowski <krzysztof.raszkowski@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6554>

spirv: fix retrieving dest type for OpFragmentMaskFetchAMD

Since the dest type is retrieved from the SPIR-V return type now,
we have to set it manually for OpFragmentMaskFetchAMD. The result
type must be a 32-bit unsigned integer type scalar.

Fix dEQP-VK.pipeline.multisample.shader_fragment_mask.* with RADV.

Fixes: a196f05fc22 ("nir/vtn: Use return type rather than image type for tex ops")
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Jesse Natalie <jenatali@microsoft.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6533>

vulkan: make VK_TIME_DOMAIN_CLOCK_MONOTONIC_RAW_EXT conditional

Only advertise VK_TIME_DOMAIN_CLOCK_MONOTONIC_RAW_EXT if CLOCK_MONOTONIC_RAW
is defined.  Fixes the build on OpenBSD which has CLOCK_MONOTONIC but not
CLOCK_MONOTONIC_RAW.

Fixes: 67a2c1493c0 ("vulkan: Add VK_EXT_calibrated_timestamps extension (radv and anv) [v5]")
Signed-off-by: Jonathan Gray <jsg@jsg.id.au>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6517>

radv: remove seccomp includes

57c95d2ce23 ("radv: a support for a secure compile fork at device creation")
added includes which were not removed in
7324977e420 ("radv: remove the secure compile support feature")

remove these no longer needed includes to fix the non-linux build

Fixes: 7324977e420 ("radv: remove the secure compile support feature")
Signed-off-by: Jonathan Gray <jsg@jsg.id.au>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6517>

util/os_misc: os_get_available_system_memory() for OpenBSD

Return the smallest value of available non-kernel physical memory and
the static per process data size limit as the amount of available
system memory on OpenBSD.

Fixes: b80930a6fea ("anv: add support for VK_EXT_memory_budget")
Signed-off-by: Jonathan Gray <jsg@jsg.id.au>
Acked-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6517>

anv: use os_get_available_system_memory()

Replace local get_available_system_memory() function with
os_get_available_system_memory().

Fixes: b80930a6fea ("anv: add support for VK_EXT_memory_budget")
Signed-off-by: Jonathan Gray <jsg@jsg.id.au>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6517>

util/os_misc: add os_get_available_system_memory()

Add os_get_available_system_memory() derived from
src/intel/vulkan/anv_device.c get_available_system_memory()

Fixes: b80930a6fea ("anv: add support for VK_EXT_memory_budget")
Signed-off-by: Jonathan Gray <jsg@jsg.id.au>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6517>

anv: use os_get_total_physical_memory()

Replace non-portable sysinfo() use with Mesa's
os_get_total_physical_memory()

Fixes: 060a6434eca ("anv: Advertise larger heap sizes")
Signed-off-by: Jonathan Gray <jsg@jsg.id.au>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6517>

freedreno/a6xx: Add ARB_depth_clamp and separate clamp support.

Passes piglit depth_clamp, depth-clamp-range,
amd_depth_clamp_separate_range.  This is part of enabling GL 3.2 (the
other is bumping PIPE_CAP_GLSL_FEATURE_LEVEL, which I'm hoping to do once
we have the KHR-GL* testing in place).

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6544>

ci: Enable KHR-GL30 CTS testing on freedreno a630.

Since we expose desktop GL, let's get at least a little bit of testing
coverage of it.

Reviewed-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6526>

ci: Use the same VK-GL-CTS tree for GL/GLES as VK.

There's no need to have separate build scripts here, just choose what the
DEQP_TARGET is for the particular container being built.  This brings in a
tremendous number of GLES test fixes that haven't made it into a tagged
gles CTS release.

Closes: #2056
Reviewed-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6526>

ci: Bump vulkan CTS version to 1.2.3.2, and keep the GL CTS around.

The version bump gets us various testcase fixes, mostly to test
requirements).  While we're rebuilding the container, copy GL CTS stuff
from build-deqp-gl.sh -- we had already included the glcts binary in our
image, but we had unnecessary other binaries and were missing the mustpass
files (container size stays the same overall).  Also pull in all the GLES
mustpass lists, not just the main ones -- Rob wants them to increase our
coverage to match what Android CTS covers.

Reviewed-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6526>

panfrost: Drop PIPE_CAP_MAX_COMBINED_HW_ATOMIC_COUNTER/BUFFERS

Just leave it at 0 and the frontend will lower for us.

Fixes dEQP-GLES31.functional.atomic_counter.get.1_counter_*

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6439>

panfrost: add support for atomics

Signed-off-by: Italo Nicola <italonicola@collabora.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6439>

panfrost: add atomic ops infrastructure

Signed-off-by: Italo Nicola <italonicola@collabora.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6439>

panfrost: add support for src[3] in LOAD_STORE ops

Signed-off-by: Italo Nicola <italonicola@collabora.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6439>

panfrost: introduce LDST_ATOMIC property

Signed-off-by: Italo Nicola <italonicola@collabora.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6439>

panfrost: add LDST_ADDRESS property to atomic ops

Atomic ops have to encode the address of the variable it's writing to.
This property is used to align the address to 64-bit boundaries.

Signed-off-by: Italo Nicola <italonicola@collabora.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6439>

panfrost: add atomic_cmpxchg opcode

Signed-off-by: Italo Nicola <italonicola@collabora.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6439>

panfrost: fix undefined value access on mir_set_intr_mask()

Signed-off-by: Italo Nicola <italonicola@collabora.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6439>