Luke Kenneth Casson Leighton [Tue, 11 Oct 2022 13:11:04 +0000 (14:11 +0100)]
add ld/st-immediate "post-inc" mode support. unit test for LD
Luke Kenneth Casson Leighton [Tue, 11 Oct 2022 12:31:58 +0000 (13:31 +0100)]
add /pi to sv/trans/svp64.py and power_insns.py
Luke Kenneth Casson Leighton [Tue, 11 Oct 2022 12:30:56 +0000 (13:30 +0100)]
add new LD-Immediate Post constants
Konstantinos Margaritis [Tue, 11 Oct 2022 09:51:34 +0000 (09:51 +0000)]
WIP: add initial AV1 SVP64 porting
Konstantinos Margaritis [Tue, 11 Oct 2022 09:49:24 +0000 (09:49 +0000)]
move pypowersim_wrapper on its own
Luke Kenneth Casson Leighton [Tue, 11 Oct 2022 09:48:29 +0000 (10:48 +0100)]
add experimental post-increment fixedload pseudocode
Luke Kenneth Casson Leighton [Mon, 10 Oct 2022 19:29:43 +0000 (20:29 +0100)]
add elwidth overrides on Indexed REMAP, 8-bit example. reduces reg usage
Luke Kenneth Casson Leighton [Mon, 10 Oct 2022 19:02:59 +0000 (20:02 +0100)]
add elwidth overrides to get_idx_out2
Luke Kenneth Casson Leighton [Sat, 8 Oct 2022 23:35:34 +0000 (00:35 +0100)]
fix format in debug log
Luke Kenneth Casson Leighton [Sat, 8 Oct 2022 23:32:05 +0000 (00:32 +0100)]
forgot to add offset on GPR() get
Luke Kenneth Casson Leighton [Sat, 8 Oct 2022 23:11:15 +0000 (00:11 +0100)]
add elwidth overrides on destination (write) in ISACaller.
first two unit tests pass (sv.add/ew=8, sv.add/ew=32)
Luke Kenneth Casson Leighton [Sat, 8 Oct 2022 20:14:24 +0000 (21:14 +0100)]
split out base,offset in register decoding for elwidth overrides to work
previously, calculating the register number was fine, it was straight
64-bit reg indexed. however elwidths are *part-way* through registers
(packed) so need to compute the reg differently
Luke Kenneth Casson Leighton [Sat, 8 Oct 2022 19:42:17 +0000 (20:42 +0100)]
add 8-bit elwidth alu svp64 case
Luke Kenneth Casson Leighton [Sat, 8 Oct 2022 13:37:33 +0000 (14:37 +0100)]
add rfscv to major_19.csv, add test_pysvp64dis.py unit test
Luke Kenneth Casson Leighton [Sat, 8 Oct 2022 13:29:20 +0000 (14:29 +0100)]
drat
Luke Kenneth Casson Leighton [Sat, 8 Oct 2022 13:28:00 +0000 (14:28 +0100)]
add sc and scv support after moving from major.csv to extra.csv
this now involves a laborious brute-force search looking for anything
with an extra.csv path, in order to prioritise the (full) 32-bit
pattern-match over e.g. MAJOR XO=17.
attn should also work (but currently does not, no idea why, possibly
because it should actually be in major.csv?
Luke Kenneth Casson Leighton [Sat, 8 Oct 2022 12:26:09 +0000 (13:26 +0100)]
vector name "RSp" not recognised in sv.stq, added as example
Luke Kenneth Casson Leighton [Sat, 8 Oct 2022 12:23:03 +0000 (13:23 +0100)]
add stq to CSV files and unit test to test_pysvp64dis.py
Luke Kenneth Casson Leighton [Sat, 8 Oct 2022 12:14:13 +0000 (13:14 +0100)]
separate out DQ and DS to separate custom_immediates
D was unhappy about being a custom_field as an immediate.
better: create SignedImmediate class deriving from ImmediateOperand
Luke Kenneth Casson Leighton [Sat, 8 Oct 2022 12:11:33 +0000 (13:11 +0100)]
use new base-class EXTSOperand, derive from ImmediateOperand
Luke Kenneth Casson Leighton [Sat, 8 Oct 2022 11:45:30 +0000 (12:45 +0100)]
convert TargetAddrOperand to base class EXTSOperand
(about to do DQ/DS operand)
Luke Kenneth Casson Leighton [Sat, 8 Oct 2022 11:22:56 +0000 (12:22 +0100)]
add lq and CONST_DQ
Luke Kenneth Casson Leighton [Sat, 8 Oct 2022 10:11:28 +0000 (11:11 +0100)]
restore tests, accidentally disabled
Luke Kenneth Casson Leighton [Sat, 8 Oct 2022 10:09:39 +0000 (11:09 +0100)]
add CY operand to fields.txt, in Z23-Form
(missing from Power ISA v3.0B and v3.1 spec!)
Luke Kenneth Casson Leighton [Sat, 8 Oct 2022 10:04:05 +0000 (11:04 +0100)]
add XER bits to register enums
Luke Kenneth Casson Leighton [Sat, 8 Oct 2022 09:29:38 +0000 (10:29 +0100)]
add addex to csv and sv_analysis db. also needs CryIn.OV enum
added quick test_pysvp64dis.py test too
Luke Kenneth Casson Leighton [Sat, 8 Oct 2022 09:10:15 +0000 (10:10 +0100)]
misnamed instruction, lfiwzx
Luke Kenneth Casson Leighton [Fri, 7 Oct 2022 12:47:03 +0000 (13:47 +0100)]
more work on inssort. add useful reg-dump in ISACaller
Luke Kenneth Casson Leighton [Thu, 6 Oct 2022 21:41:04 +0000 (22:41 +0100)]
nope. failfirst needs to always save the result, but truncate VL *after*.
https://bugs.libre-soc.org/show_bug.cgi?id=936
Luke Kenneth Casson Leighton [Thu, 6 Oct 2022 19:19:42 +0000 (20:19 +0100)]
fix fail-first to exclude failed element in VLi=0 mode
Luke Kenneth Casson Leighton [Thu, 6 Oct 2022 17:34:38 +0000 (18:34 +0100)]
sort out CROPs fail-first in ISACaller. needed to take a copy of CR
for when sv.cmp (and other pseudocode) *overwrites* CR and it needs
restoring (when VLI=0). also needed to identify 3-bit and 5-bit
ffirst mode, and extract bottom 2 bits of BF
Luke Kenneth Casson Leighton [Thu, 6 Oct 2022 16:26:24 +0000 (17:26 +0100)]
make fail-first cope with sv.cmp which uses CR[BF]
Luke Kenneth Casson Leighton [Thu, 6 Oct 2022 14:59:54 +0000 (15:59 +0100)]
add insert sort svp64 test
Luke Kenneth Casson Leighton [Thu, 6 Oct 2022 14:58:11 +0000 (15:58 +0100)]
search for BF in registers to over-ride Vector lookup into CR Register
CR[32+BF...] is used, so it is more complex
Luke Kenneth Casson Leighton [Thu, 6 Oct 2022 13:36:23 +0000 (14:36 +0100)]
starting to add sv.cmp support and failfirst, had to add
SVMode to SVP64RMModeDecode to identify the different RM modes first
Luke Kenneth Casson Leighton [Thu, 6 Oct 2022 12:16:28 +0000 (13:16 +0100)]
add PredicateBaseRM decode to CR Ops Simple mode as well as ff=3-bit
Luke Kenneth Casson Leighton [Thu, 6 Oct 2022 11:57:57 +0000 (12:57 +0100)]
add vli mode to ff=5 CR ops
Luke Kenneth Casson Leighton [Thu, 6 Oct 2022 11:51:42 +0000 (12:51 +0100)]
whoops must only be PredicateBaseRM in CROpFF5RM
Luke Kenneth Casson Leighton [Thu, 6 Oct 2022 11:43:00 +0000 (12:43 +0100)]
add sv.cmp (ffirst-5) decode/encode asm support
* sv/trans/svp64.py needed a totally different ffirst handling
* CROpFF5RM needs to derive from FFPRRc0BaseRM and PredicateWidthBaseRM
Luke Kenneth Casson Leighton [Thu, 6 Oct 2022 11:18:30 +0000 (12:18 +0100)]
slightly different crops failfirst mode bits
Luke Kenneth Casson Leighton [Thu, 6 Oct 2022 10:53:59 +0000 (11:53 +0100)]
add sv.cmp and try fail-first test_pysvp64dist.py
Luke Kenneth Casson Leighton [Sun, 2 Oct 2022 11:38:32 +0000 (12:38 +0100)]
remove complaints about standard Cray-style Vectors for the past 40 years
being able to have VL set to zero dynamically at runtime.
it is not appropriate to have complaints about 40-year-old standard
canonical behaviour of Cray Vectors in source code comments
VL=0 being set dynamically at runtime based on an algorithm input
sets the operations to nop because that is expected behaviour.
to not have VL=0 would be catastrophically inconvenient: it would
require either Illegal-Instruction traps to be raised, or Condition
Codes to be set and followed up with instructions to test and
branch for the dynamic condition when RA was zero, or to pre-test
for RA or CTR pre-being-zero prior to entry into a loop.
Data-Dependent Fail-First would become irrevocably damaged as well
as it is possible for VL to be set to zero at that time (first
test fails)
sv.bc would also be irrevocably damaged as it would no longer
be possible in VLSET mode to have VL become truncated to zero
dynamically based on a Condition Code.
in all it is pretty catastrophic to the entire Cray-Vector paradigm
and would severely damage SimpleV to disallow VL=0 purely for
arbitrary "convenience"
Luke Kenneth Casson Leighton [Sun, 2 Oct 2022 02:29:39 +0000 (03:29 +0100)]
comments for why preinc is called for svstep
Luke Kenneth Casson Leighton [Sun, 2 Oct 2022 02:21:08 +0000 (03:21 +0100)]
comment out selectableint getitem logs
Luke Kenneth Casson Leighton [Sat, 1 Oct 2022 23:35:08 +0000 (00:35 +0100)]
skip svstate_pre_inc on svremap
should not be needed
Luke Kenneth Casson Leighton [Sat, 1 Oct 2022 23:26:23 +0000 (00:26 +0100)]
no svstate instruction
Luke Kenneth Casson Leighton [Sat, 1 Oct 2022 23:24:25 +0000 (00:24 +0100)]
svstep calls SVSTATE_NEXT so needs svstate_pre_inc
setvl no longer calls SVSTATE_NEXT so does not
Luke Kenneth Casson Leighton [Sat, 1 Oct 2022 23:10:15 +0000 (00:10 +0100)]
remove special case from setvl calling SVSTATE_NEXT,
only accessible through svstep now
Luke Kenneth Casson Leighton [Sat, 1 Oct 2022 21:40:21 +0000 (22:40 +0100)]
replacing setvl-svstep with just svstep
Luke Kenneth Casson Leighton [Sat, 1 Oct 2022 21:36:04 +0000 (22:36 +0100)]
replacing setvl-svstep with just svstep
Luke Kenneth Casson Leighton [Sat, 1 Oct 2022 21:27:25 +0000 (22:27 +0100)]
replacing setvl-svstep with just svstep
Luke Kenneth Casson Leighton [Sat, 1 Oct 2022 16:00:06 +0000 (17:00 +0100)]
comments
Luke Kenneth Casson Leighton [Sat, 1 Oct 2022 15:55:13 +0000 (16:55 +0100)]
comments
Luke Kenneth Casson Leighton [Sat, 1 Oct 2022 15:44:56 +0000 (16:44 +0100)]
minor cleanup in ISACaller on result handling
create a dictionary matched with output reg names, adapt handle_carry
handle_overflow etc. to use it. mostly
Luke Kenneth Casson Leighton [Sat, 1 Oct 2022 13:43:24 +0000 (14:43 +0100)]
simplify ISACaller execute_one
Luke Kenneth Casson Leighton [Sat, 1 Oct 2022 13:21:44 +0000 (14:21 +0100)]
simplify setting default SVSHAPE SPRs to zero
Jacob Lifshay [Sat, 1 Oct 2022 00:10:44 +0000 (17:10 -0700)]
increase pcdec. output compression by skipping impossible codes
Jacob Lifshay [Fri, 30 Sep 2022 23:08:53 +0000 (16:08 -0700)]
prefix codes tests pass
Luke Kenneth Casson Leighton [Fri, 30 Sep 2022 17:39:45 +0000 (18:39 +0100)]
no need for ctr mode on sv.bc
Luke Kenneth Casson Leighton [Fri, 30 Sep 2022 17:37:35 +0000 (18:37 +0100)]
ctr mode not needed, just use unconditional CTR dec
Luke Kenneth Casson Leighton [Fri, 30 Sep 2022 13:39:27 +0000 (14:39 +0100)]
set srcstep/dststep to zero in StepLoop (ISACaller) at loopend
see if a different style of looping can be used
Luke Kenneth Casson Leighton [Fri, 30 Sep 2022 13:03:20 +0000 (14:03 +0100)]
add sv.bc vlset-inverted test
Luke Kenneth Casson Leighton [Fri, 30 Sep 2022 12:59:05 +0000 (13:59 +0100)]
comments/variables-cleanup
Luke Kenneth Casson Leighton [Fri, 30 Sep 2022 11:28:19 +0000 (12:28 +0100)]
add sv.bc vlset-inverted test
this one inverts all the logic (some instead of all, LE instead of GT,
VL-truncate if FAIL)
and thus can swap the success-fail branch point. avoids one branch in loops
Luke Kenneth Casson Leighton [Fri, 30 Sep 2022 10:56:55 +0000 (11:56 +0100)]
add sv.bc/vs - VLset - test. truncates VL at the vector-condition-fail point
Luke Kenneth Casson Leighton [Fri, 30 Sep 2022 09:47:41 +0000 (10:47 +0100)]
add code-comments in variance_svp64_real.s on how to use sv.bc/ctr/all
Luke Kenneth Casson Leighton [Fri, 30 Sep 2022 09:37:57 +0000 (10:37 +0100)]
add new sv.bc CTR-loop test, subtracts VL from CTR
Luke Kenneth Casson Leighton [Fri, 30 Sep 2022 08:14:26 +0000 (09:14 +0100)]
whitespace
Luke Kenneth Casson Leighton [Fri, 30 Sep 2022 08:12:41 +0000 (09:12 +0100)]
use regs variables in get_predint
Luke Kenneth Casson Leighton [Fri, 30 Sep 2022 08:06:58 +0000 (09:06 +0100)]
comments
Jacob Lifshay [Fri, 30 Sep 2022 03:49:16 +0000 (20:49 -0700)]
fix pcdec. assembly -- merge into va_form() since it's no longer VA2-form
Jacob Lifshay [Fri, 30 Sep 2022 03:46:38 +0000 (20:46 -0700)]
fix pcdec.'s form
Jacob Lifshay [Fri, 30 Sep 2022 03:17:50 +0000 (20:17 -0700)]
rewrite pcdec. pseudocode to work better for JPEG
the pcdec. unittests aren't updated yet
Jacob Lifshay [Fri, 30 Sep 2022 01:44:47 +0000 (18:44 -0700)]
add lookup table generation for JPEG decode
Jacob Lifshay [Fri, 30 Sep 2022 01:44:23 +0000 (18:44 -0700)]
allow logging function to be overridden for Mem.log_fancy
Jacob Lifshay [Thu, 29 Sep 2022 23:21:22 +0000 (16:21 -0700)]
convert svp64 bigint unittests to use TestAccumulatorBase
Jacob Lifshay [Thu, 29 Sep 2022 22:46:48 +0000 (15:46 -0700)]
finish changing to use adde, not addeo for bigint add
Luke Kenneth Casson Leighton [Thu, 29 Sep 2022 18:00:30 +0000 (19:00 +0100)]
sv.adde not sv.addeo
Luke Kenneth Casson Leighton [Thu, 29 Sep 2022 14:06:52 +0000 (15:06 +0100)]
destination for maddedu and divmod2du for RS defaults to RC for scalar
Luke Kenneth Casson Leighton [Thu, 29 Sep 2022 13:59:45 +0000 (14:59 +0100)]
wowser, complex. implementing maddedu implicit RC/RS rules.
still TODO
<!-- bit 8 of EXTRA is clear: RS.[s|v]=RT.[s|v]+MAXVL
<!-- bit 8 of EXTRA is set : RS.[s|v]=RC.[s|v]
actually it is currently "if RC is scalar then RS=RC" which is more
sensible
Luke Kenneth Casson Leighton [Thu, 29 Sep 2022 13:57:26 +0000 (14:57 +0100)]
add carry-roll-over-vector-mul-with-add (!) unit test
test_caller_svp64_bigint.py
https://bugs.libre-soc.org/show_bug.cgi?id=937
Luke Kenneth Casson Leighton [Thu, 29 Sep 2022 11:09:43 +0000 (12:09 +0100)]
comments
Luke Kenneth Casson Leighton [Thu, 29 Sep 2022 10:56:20 +0000 (11:56 +0100)]
add shift-left and shift-right scalar-to-vector tests
Luke Kenneth Casson Leighton [Thu, 29 Sep 2022 01:39:55 +0000 (02:39 +0100)]
update iterators in ISACaller, not used yet
Jacob Lifshay [Thu, 29 Sep 2022 03:10:05 +0000 (20:10 -0700)]
rename madded->maddedu for consistency with PowerISA maddhdu instruction
Jacob Lifshay [Thu, 29 Sep 2022 03:05:02 +0000 (20:05 -0700)]
rename divrem2du->divmod2du for consistency with PowerISA mod* instructions
Jacob Lifshay [Thu, 29 Sep 2022 02:46:54 +0000 (19:46 -0700)]
add bigint tests and fix madded pseudocode
Jacob Lifshay [Thu, 29 Sep 2022 02:46:15 +0000 (19:46 -0700)]
add bigint ops
Jacob Lifshay [Thu, 29 Sep 2022 02:45:00 +0000 (19:45 -0700)]
fill out dsld/dsrd pseudocode
Jacob Lifshay [Thu, 29 Sep 2022 02:43:16 +0000 (19:43 -0700)]
add missing DRAFT comment
Jacob Lifshay [Thu, 29 Sep 2022 02:39:27 +0000 (19:39 -0700)]
fix test_minor_30
Jacob Lifshay [Thu, 29 Sep 2022 02:39:07 +0000 (19:39 -0700)]
format code
Jacob Lifshay [Thu, 29 Sep 2022 02:33:00 +0000 (19:33 -0700)]
clean up bigint instruction naming
Jacob Lifshay [Thu, 29 Sep 2022 02:29:20 +0000 (19:29 -0700)]
remove unnecesary commented code
Jacob Lifshay [Thu, 29 Sep 2022 02:08:07 +0000 (19:08 -0700)]
add unofficial and comment2 fields to minor_31.csv
Luke Kenneth Casson Leighton [Wed, 28 Sep 2022 23:49:46 +0000 (00:49 +0100)]
srcstep
Luke Kenneth Casson Leighton [Wed, 28 Sep 2022 21:14:17 +0000 (22:14 +0100)]
rename iterators init function
Luke Kenneth Casson Leighton [Wed, 28 Sep 2022 21:04:16 +0000 (22:04 +0100)]
redundant comment
Luke Kenneth Casson Leighton [Wed, 28 Sep 2022 21:00:23 +0000 (22:00 +0100)]
split out svstate update in ISACaller
Luke Kenneth Casson Leighton [Wed, 28 Sep 2022 20:44:54 +0000 (21:44 +0100)]
move failfirst check to separate function in ISACaller