Raptor Engineering Development Team [Mon, 11 Apr 2022 20:06:17 +0000 (15:06 -0500)]
Reduce ECP5 85 nest frequency to 75MHz
This gets much closer to passing timing on the
-7 speed grade parts, and should pass timing
on the -8 speed grade parts.
Verified to boot correctly:
fw..DRAM init... initseq
done
MR profile:
00000B20 00000806 00000200 00000000
Rdly
p0:
01110011
Rdly
p1:
01110011
Auto calibrating... find mindone
Auto calibration profile:p0 rdly:
00000002 p1 rdly:
00000002
Reloading built-in calibration profile...DRAM test...
done
Raptor Engineering Development Team [Mon, 11 Apr 2022 19:33:25 +0000 (14:33 -0500)]
Separate nest and core clocks
Add async bridges between CPU and Wishbone
downconverters
Switch Raptor Versa 85 board to 100MHz
nest and 50MHz core
Verified to function on Raptor Versa 85
board
Raptor Engineering Development Team [Mon, 11 Apr 2022 17:43:52 +0000 (12:43 -0500)]
WB64to32Convert: Obey STALL in burst mode (#807)
Raptor Engineering Development Team [Mon, 11 Apr 2022 17:43:12 +0000 (12:43 -0500)]
Add missing DELAYG peripheral to simulation script
Luke Kenneth Casson Leighton [Sat, 9 Apr 2022 22:06:09 +0000 (23:06 +0100)]
add QSPI dump back in (smaller one) to check it is working
Raptor Engineering Development Team [Sat, 9 Apr 2022 20:06:12 +0000 (15:06 -0500)]
Wire up missing CRG / DDR3 clock control / reset signals
Luke Kenneth Casson Leighton [Sat, 9 Apr 2022 14:21:52 +0000 (15:21 +0100)]
sigh use MEMORY_BASE which is at 0x0000_0000 and coincides with DRAM_BASE
Luke Kenneth Casson Leighton [Sat, 9 Apr 2022 13:02:01 +0000 (14:02 +0100)]
shuffle addresses around a bit
* firmware ROM is at 0xff00_0000
* DRAM is at 0x0000_0000
* for no real reason if DRAM is not present at 0x0 an SRAM is added
* set the default coldboot compile-start address at 0xff00_0000
Luke Kenneth Casson Leighton [Fri, 8 Apr 2022 20:34:08 +0000 (21:34 +0100)]
add DRAM offset into SYSCON and jump to DRAM if flash successfully
returns an offset after copy
Luke Kenneth Casson Leighton [Fri, 8 Apr 2022 20:09:20 +0000 (21:09 +0100)]
add ELF reading to coldboot.c, move spi address to 0xf000_000
and add spi read-offset to Microwatt SYSCON
Luke Kenneth Casson Leighton [Fri, 8 Apr 2022 17:46:12 +0000 (18:46 +0100)]
add read of SYSCON and entry for SPIFlash
Luke Kenneth Casson Leighton [Fri, 8 Apr 2022 14:53:29 +0000 (15:53 +0100)]
up the delay-time on ddr3 reset, put loop around dram init just for fun
Luke Kenneth Casson Leighton [Fri, 8 Apr 2022 11:54:05 +0000 (12:54 +0100)]
comment/80-char limit
Raptor Engineering Development Team [Thu, 7 Apr 2022 21:36:51 +0000 (16:36 -0500)]
Update coldboot DDR3 init firmware to work with latest gram changes
Raptor Engineering Development Team [Thu, 7 Apr 2022 21:33:51 +0000 (16:33 -0500)]
Add an asm dump with source to the coldboot makefile
Clean all files, including libgram files, when running
make clean
Raptor Engineering Development Team [Thu, 7 Apr 2022 21:33:18 +0000 (16:33 -0500)]
Enable DDR3 using a 50MHz clock on Versa 85
Raptor Engineering Development Team [Thu, 7 Apr 2022 21:32:53 +0000 (16:32 -0500)]
Move simulation HyperRAM pins off of DDR3 pins
Raptor Engineering Development Team [Thu, 7 Apr 2022 21:32:18 +0000 (16:32 -0500)]
Fix DRAM simulation commands
Luke Kenneth Casson Leighton [Wed, 6 Apr 2022 11:28:03 +0000 (12:28 +0100)]
add QSPI support to arty_a7
Luke Kenneth Casson Leighton [Mon, 4 Apr 2022 19:14:10 +0000 (20:14 +0100)]
allow setting individual directions on QSPI dq0-dq3
Luke Kenneth Casson Leighton [Mon, 4 Apr 2022 17:14:46 +0000 (18:14 +0100)]
write out firmware to correct location,
adapt to 64/32 bit output
Luke Kenneth Casson Leighton [Mon, 4 Apr 2022 17:09:26 +0000 (18:09 +0100)]
sigh put firmware.hex qspi file in correct place
Luke Kenneth Casson Leighton [Mon, 4 Apr 2022 17:08:59 +0000 (18:08 +0100)]
increase power-on-delay for icarus sim to allow reset to occur
Luke Kenneth Casson Leighton [Mon, 4 Apr 2022 16:25:44 +0000 (17:25 +0100)]
re-enable build of firmware in sim
Luke Kenneth Casson Leighton [Mon, 4 Apr 2022 16:11:46 +0000 (17:11 +0100)]
disable ethmac for now, pass firmware.hex to cypress qspi model
Luke Kenneth Casson Leighton [Sun, 3 Apr 2022 10:23:46 +0000 (11:23 +0100)]
redo start address of firmware so it can be specified -DBOOT_INIT_BASE
Raptor Engineering Development Team [Mon, 4 Apr 2022 16:06:51 +0000 (11:06 -0500)]
Fix SPI device simulation model MISO/MOSI wiring
Raptor Engineering Development Team [Sat, 2 Apr 2022 21:53:56 +0000 (16:53 -0500)]
Add 10/100 MAC pins for Versa boards and enable MAC
Tested to not interfere with main SoC in simulation,
not tested further at this point.
Luke Kenneth Casson Leighton [Thu, 31 Mar 2022 13:42:53 +0000 (14:42 +0100)]
reduce number of params obtained on QSPI for icarus sim
Luke Kenneth Casson Leighton [Thu, 31 Mar 2022 13:31:08 +0000 (14:31 +0100)]
got icarus verilog model of QSPI working and it returns the same
FFFFFFF
Luke Kenneth Casson Leighton [Thu, 31 Mar 2022 09:02:39 +0000 (10:02 +0100)]
whitespace cleanup
Raptor Engineering Development Team [Thu, 31 Mar 2022 07:39:31 +0000 (02:39 -0500)]
Fix Tercel QSPI master connections
Tested to work on Raptor Versa 85 custom board
in both word and byte mode.
Luke Kenneth Casson Leighton [Thu, 31 Mar 2022 01:31:37 +0000 (02:31 +0100)]
remove {err} feature from Tercel
Luke Kenneth Casson Leighton [Tue, 29 Mar 2022 19:43:58 +0000 (20:43 +0100)]
add err wishbone feature to Tercel
Luke Kenneth Casson Leighton [Tue, 29 Mar 2022 19:43:44 +0000 (20:43 +0100)]
add config-dump from SPI
Luke Kenneth Casson Leighton [Tue, 29 Mar 2022 19:40:27 +0000 (20:40 +0100)]
remove clk from spi_flash,
change cs_n to cs,
de-bork WB access with stall=cyc&~ack thing
Luke Kenneth Casson Leighton [Tue, 29 Mar 2022 12:45:51 +0000 (13:45 +0100)]
add qspi module to arty_a7
Luke Kenneth Casson Leighton [Tue, 29 Mar 2022 12:45:32 +0000 (13:45 +0100)]
quick-and-dirty QSPI read test
Luke Kenneth Casson Leighton [Tue, 29 Mar 2022 12:32:35 +0000 (13:32 +0100)]
use nmigen_boards naming conventions for SPIFlash
Luke Kenneth Casson Leighton [Tue, 29 Mar 2022 11:52:11 +0000 (12:52 +0100)]
update comments, link/setup of peripherals
(all done manually at the moment, TODO a dev-env-setup)
Luke Kenneth Casson Leighton [Tue, 29 Mar 2022 11:46:57 +0000 (12:46 +0100)]
add TODO comments about using platform.add_resources
Luke Kenneth Casson Leighton [Tue, 29 Mar 2022 11:00:54 +0000 (12:00 +0100)]
whitespace cleanup, 80 char limit
Luke Kenneth Casson Leighton [Tue, 29 Mar 2022 10:58:32 +0000 (11:58 +0100)]
add patch for n25q to fix model using fork/join, should be begin/end
Raptor Engineering Development Team [Tue, 29 Mar 2022 01:11:43 +0000 (20:11 -0500)]
Add initial integration for OpenCores 10/100 Ethernet MAC
Raptor Engineering Development Team [Mon, 28 Mar 2022 15:58:23 +0000 (10:58 -0500)]
Fix instructions in comment
Luke Kenneth Casson Leighton [Mon, 28 Mar 2022 14:16:45 +0000 (15:16 +0100)]
quick memory test increasing by power-2 each time shows all 32 mbytes of
hyperram ICs are accessible
Luke Kenneth Casson Leighton [Sun, 27 Mar 2022 15:32:15 +0000 (16:32 +0100)]
set reset from ResetSignal not straight to 1 for HyperRAM
put correct IOPad names into HyperRAMResource for arty a7
Luke Kenneth Casson Leighton [Sun, 27 Mar 2022 12:21:48 +0000 (13:21 +0100)]
try latency of 7 for winbond hyperram
Luke Kenneth Casson Leighton [Sun, 27 Mar 2022 12:21:25 +0000 (13:21 +0100)]
add link to Winbond HyperRAM model
Luke Kenneth Casson Leighton [Sun, 27 Mar 2022 11:07:50 +0000 (12:07 +0100)]
set upper CSns on HyperRAM to zero and set reset_n HI
fix CSn pin-pad names
Luke Kenneth Casson Leighton [Sat, 26 Mar 2022 22:40:47 +0000 (22:40 +0000)]
add clock output on hyperram sim
Luke Kenneth Casson Leighton [Sat, 26 Mar 2022 22:40:33 +0000 (22:40 +0000)]
add all 4 CSn lines for Quad HyperRAM PMOD
Luke Kenneth Casson Leighton [Sat, 26 Mar 2022 22:18:15 +0000 (22:18 +0000)]
grr
Luke Kenneth Casson Leighton [Sat, 26 Mar 2022 22:16:27 +0000 (22:16 +0000)]
reduce power-on-delay bits to 2 for icarus sim ecp5
Luke Kenneth Casson Leighton [Sat, 26 Mar 2022 21:49:14 +0000 (21:49 +0000)]
remove switches from hyperram iverilog test
Luke Kenneth Casson Leighton [Sat, 26 Mar 2022 21:39:58 +0000 (21:39 +0000)]
remove unneeded model variable
Luke Kenneth Casson Leighton [Sat, 26 Mar 2022 21:36:59 +0000 (21:36 +0000)]
add missing ECP5 model OBZ.v and rename testbench
Luke Kenneth Casson Leighton [Sat, 26 Mar 2022 21:21:48 +0000 (21:21 +0000)]
sort out platform IO pads for iverilog hyperram sim
Luke Kenneth Casson Leighton [Sat, 26 Mar 2022 20:58:45 +0000 (20:58 +0000)]
add hyperram iverilog runner including s27kl0641.v model
Luke Kenneth Casson Leighton [Fri, 25 Mar 2022 14:55:03 +0000 (14:55 +0000)]
rename ECP5 CRG, move source, remove duplicate version
Luke Kenneth Casson Leighton [Fri, 25 Mar 2022 14:53:14 +0000 (14:53 +0000)]
up arty a7 frequency to 40 mhz
Luke Kenneth Casson Leighton [Fri, 25 Mar 2022 14:53:01 +0000 (14:53 +0000)]
increase time for power-on-delay to 2^25 in ECP5
Luke Kenneth Casson Leighton [Fri, 25 Mar 2022 14:50:22 +0000 (14:50 +0000)]
loop-test on hyperram read/write which needs carriage-return to activate
Luke Kenneth Casson Leighton [Thu, 24 Mar 2022 22:13:13 +0000 (22:13 +0000)]
increase delay on ECP5 ulx3s
Luke Kenneth Casson Leighton [Thu, 24 Mar 2022 20:35:46 +0000 (20:35 +0000)]
check ulx3s, add CRG support for ulx3s
Luke Kenneth Casson Leighton [Thu, 24 Mar 2022 13:28:12 +0000 (13:28 +0000)]
establish power-on reset stabilisation for Arty A7 and ECP5
Luke Kenneth Casson Leighton [Tue, 22 Mar 2022 17:00:39 +0000 (17:00 +0000)]
add hack to modify VERSA_ECP5 85F platform to speed grade 7
Luke Kenneth Casson Leighton [Tue, 22 Mar 2022 16:59:31 +0000 (16:59 +0000)]
adding hyperram for arty a7 and also adding a workaround for some stupid issues
Luke Kenneth Casson Leighton [Sun, 20 Mar 2022 13:40:58 +0000 (13:40 +0000)]
add microwatt hello_world source
Luke Kenneth Casson Leighton [Sun, 20 Mar 2022 13:40:47 +0000 (13:40 +0000)]
crank A7 FPGA speed down to experiment
Luke Kenneth Casson Leighton [Sun, 20 Mar 2022 13:19:14 +0000 (13:19 +0000)]
code-comments
Luke Kenneth Casson Leighton [Sun, 20 Mar 2022 13:18:21 +0000 (13:18 +0000)]
fix Arty A7-100t PLL with quick demo
Luke Kenneth Casson Leighton [Sun, 20 Mar 2022 11:34:42 +0000 (11:34 +0000)]
first cut at Arty A7 Clock-Reset-Generator with S7 PLL
Luke Kenneth Casson Leighton [Sun, 20 Mar 2022 09:56:46 +0000 (09:56 +0000)]
beginnings of arty a7 clock-reset-generator
Luke Kenneth Casson Leighton [Sat, 19 Mar 2022 22:44:36 +0000 (22:44 +0000)]
add VERSA_ECP5 85F custom board
Luke Kenneth Casson Leighton [Sat, 19 Mar 2022 20:46:31 +0000 (20:46 +0000)]
move quick read/write test for hyperram in coldboot.c
Luke Kenneth Casson Leighton [Sat, 19 Mar 2022 19:00:19 +0000 (19:00 +0000)]
set IO_TYPE 3.3v attribute on HyperRAM not IOSTANDARD
disable DDR3 temporarily with a hack on versa_ecp5 platform
Luke Kenneth Casson Leighton [Sat, 19 Mar 2022 14:04:57 +0000 (14:04 +0000)]
correct pin names for HyperRAMResource, indent spi0 core
Luke Kenneth Casson Leighton [Sat, 19 Mar 2022 12:37:33 +0000 (12:37 +0000)]
fixed hyperram pin names which was stopping verilator (and pretty much
everything) from working. HyperRAMResource had a name "clk" as a pin
which was obviously getting merged with sys_clk, sigh
Luke Kenneth Casson Leighton [Sat, 19 Mar 2022 11:48:37 +0000 (11:48 +0000)]
disable hyperram for now (under investigation)
Luke Kenneth Casson Leighton [Sat, 19 Mar 2022 11:28:37 +0000 (11:28 +0000)]
adding in hyperram peripheral
Luke Kenneth Casson Leighton [Fri, 18 Mar 2022 12:32:42 +0000 (12:32 +0000)]
whitespace / module-import / comments / tidyup
Luke Kenneth Casson Leighton [Fri, 18 Mar 2022 10:51:55 +0000 (10:51 +0000)]
beginning to add hyperram module
Luke Kenneth Casson Leighton [Fri, 18 Mar 2022 09:26:46 +0000 (09:26 +0000)]
whitespace cleanup and make SPI core (temporarily) optional
based on arctic tern fpga board. TODO: add arctic tern fpga board to
nmigen_boards
Luke Kenneth Casson Leighton [Thu, 17 Mar 2022 13:40:09 +0000 (13:40 +0000)]
work-in-progress on DDR3 firmware. sigh
Luke Kenneth Casson Leighton [Thu, 17 Mar 2022 12:57:05 +0000 (12:57 +0000)]
comment about icarus verilog to speed up simulations
Raptor Engineering Development Team [Mon, 14 Mar 2022 00:33:24 +0000 (19:33 -0500)]
Add initial Tercel SPI controller
NOTE: Still needs testing on physical hardware,
waiting for Arctic Tern support.
Luke Kenneth Casson Leighton [Thu, 10 Mar 2022 12:41:09 +0000 (12:41 +0000)]
sigh gramWishbone is not WB4-pipeline-burst-compliant
compensate for this with the "usual" WB3 classic trick stall=cyc&~ack;
Luke Kenneth Casson Leighton [Wed, 9 Mar 2022 19:44:13 +0000 (19:44 +0000)]
fix WB6to32 downconverter with stall signalling
Luke Kenneth Casson Leighton [Wed, 9 Mar 2022 12:12:51 +0000 (12:12 +0000)]
add stall signal to arbiter, assume nmigen-soc takes
care of adaptation from WB4-pipeline-burst to WB3-classic
Luke Kenneth Casson Leighton [Fri, 4 Mar 2022 14:58:28 +0000 (14:58 +0000)]
add experimental stall-capable 64-to-32 wishbone converter
based on microwatt soc.vhdl
Luke Kenneth Casson Leighton [Wed, 2 Mar 2022 13:59:26 +0000 (13:59 +0000)]
lots of comments in the yosys script file
Luke Kenneth Casson Leighton [Wed, 2 Mar 2022 13:56:55 +0000 (13:56 +0000)]
invert reset and chip-select on dram, and initialise uart input
in iverilog sim
Luke Kenneth Casson Leighton [Wed, 2 Mar 2022 13:56:15 +0000 (13:56 +0000)]
forgot to include firmware in build for new icarus sim platform
Luke Kenneth Casson Leighton [Tue, 1 Mar 2022 17:09:07 +0000 (17:09 +0000)]
add new icarus-versa-ecp5 platform in ls2.py
Luke Kenneth Casson Leighton [Mon, 28 Feb 2022 21:51:56 +0000 (21:51 +0000)]
increase timescale of icarus simulation
to cover the period for coldboot.bin to initialise DRAM and perform
read/write tests
Luke Kenneth Casson Leighton [Mon, 28 Feb 2022 18:12:16 +0000 (18:12 +0000)]
fix undefined uart_tx in icarus simulation, icarus is damn smart,
it respects undefined values and propagates them. kinda cool
Luke Kenneth Casson Leighton [Mon, 28 Feb 2022 18:10:57 +0000 (18:10 +0000)]
use a slightly different yosys initialisation sequence for memory
Luke Kenneth Casson Leighton [Mon, 28 Feb 2022 17:43:59 +0000 (17:43 +0000)]
fix memory issue in yosys synth for icarus
Luke Kenneth Casson Leighton [Mon, 28 Feb 2022 17:25:04 +0000 (17:25 +0000)]
add icarus simulation of ls2 with DDR3 and ECP5 models