litex.git
5 years agosoc/cores: add initial simple hyperram core
Antti Lukats [Fri, 16 Aug 2019 07:46:15 +0000 (09:46 +0200)]
soc/cores: add initial simple hyperram core

5 years agobuild/altera/quartus: add add_ip method to use Quartus QSYS files
Florent Kermarrec [Thu, 15 Aug 2019 11:44:36 +0000 (13:44 +0200)]
build/altera/quartus: add add_ip method to use Quartus QSYS files

platform.add_ip("my_ip.qsys")

5 years agocpu_interface: add json csr map export, simplify csv csr map export using json
Florent Kermarrec [Thu, 15 Aug 2019 07:26:25 +0000 (09:26 +0200)]
cpu_interface: add json csr map export, simplify csv csr map export using json

5 years agobios/sdram: set init done after memtest (for standalone LiteDRAM controllers)
Florent Kermarrec [Wed, 14 Aug 2019 17:09:58 +0000 (19:09 +0200)]
bios/sdram: set init done after memtest (for standalone LiteDRAM controllers)

5 years agobuild/xilinx/vivado: use "" for strings
Florent Kermarrec [Wed, 14 Aug 2019 17:03:10 +0000 (19:03 +0200)]
build/xilinx/vivado: use "" for strings

5 years agobuild/xilinx/vivado: remove with_phys_opt
Florent Kermarrec [Wed, 14 Aug 2019 17:02:01 +0000 (19:02 +0200)]
build/xilinx/vivado: remove with_phys_opt

5 years agoMerge pull request #243 from sergachev/master
enjoy-digital [Wed, 14 Aug 2019 16:58:15 +0000 (18:58 +0200)]
Merge pull request #243 from sergachev/master

build/xilinx/vivado: improve directive support

5 years agoMerge pull request #241 from railnova/zynq
enjoy-digital [Wed, 14 Aug 2019 16:55:34 +0000 (18:55 +0200)]
Merge pull request #241 from railnova/zynq

[fix] prevent Vivado from inferring DSP48 in AXIBurst2Beat

5 years agobuild/xilinx/vivado: improve directive support
Ilia Sergachev [Wed, 14 Aug 2019 15:49:13 +0000 (17:49 +0200)]
build/xilinx/vivado: improve directive support

5 years ago[fix] prevent Vivado from inferring DSP48 in AXIBurst2Beat
chmousset [Wed, 14 Aug 2019 09:30:39 +0000 (11:30 +0200)]
[fix] prevent Vivado from inferring DSP48 in AXIBurst2Beat

5 years agocores/spi_flash/S7SPIFlash: make cs_n optional in pads (when driven externally)
Florent Kermarrec [Wed, 14 Aug 2019 05:35:45 +0000 (07:35 +0200)]
cores/spi_flash/S7SPIFlash: make cs_n optional in pads (when driven externally)

5 years agoMerge pull request #240 from danielkucera/patch-1
enjoy-digital [Tue, 13 Aug 2019 08:34:50 +0000 (10:34 +0200)]
Merge pull request #240 from danielkucera/patch-1

more understandable error when missing a memory

5 years agomore understandable error when missing a memory
Daniel Kucera [Tue, 13 Aug 2019 08:14:16 +0000 (10:14 +0200)]
more understandable error when missing a memory

5 years agoUpdate .gitmodules
atommann [Mon, 12 Aug 2019 14:20:34 +0000 (22:20 +0800)]
Update .gitmodules

http to https

5 years agoMerge pull request #235 from gsomlo/gls-trellis-yosys-opt
enjoy-digital [Sat, 10 Aug 2019 13:33:05 +0000 (15:33 +0200)]
Merge pull request #235 from gsomlo/gls-trellis-yosys-opt

build/lattice/trellis: use additional yosys optimization flags

5 years agobuild/lattice/trellis: use abc9 techmapping pass with yosys
Gabriel L. Somlo [Fri, 5 Jul 2019 20:28:23 +0000 (16:28 -0400)]
build/lattice/trellis: use abc9 techmapping pass with yosys

Signed-off-by: Gabriel Somlo <gsomlo@gmail.com>
5 years agosoftware/libbase/mdio: set data before clock, revert two cycle turnaround and test...
Florent Kermarrec [Fri, 9 Aug 2019 11:26:31 +0000 (13:26 +0200)]
software/libbase/mdio: set data before clock, revert two cycle turnaround and test with different phys

5 years agocores/cpu: add riscv-none-embed toolchain support to riscv32 cpus
Florent Kermarrec [Fri, 9 Aug 2019 10:33:10 +0000 (12:33 +0200)]
cores/cpu: add riscv-none-embed toolchain support to riscv32 cpus

5 years agosoftware/libase/mdio: cleanup and reduce raw_turnaround by 1 cycle
Florent Kermarrec [Fri, 9 Aug 2019 08:31:53 +0000 (10:31 +0200)]
software/libase/mdio: cleanup and reduce raw_turnaround by 1 cycle

5 years agocores/clock/S7PLL: fix -1/-3 speedgrade vco max freq swap
Florent Kermarrec [Fri, 9 Aug 2019 07:27:32 +0000 (09:27 +0200)]
cores/clock/S7PLL: fix -1/-3 speedgrade vco max freq swap

5 years agosoftware/bios: add Ethernet PHY MDIO read/write/dump commands
Florent Kermarrec [Fri, 9 Aug 2019 07:26:41 +0000 (09:26 +0200)]
software/bios: add Ethernet PHY MDIO read/write/dump commands

5 years agoaltera/common: fix AsyncResetSynchronizer polarity and simplify
Florent Kermarrec [Thu, 8 Aug 2019 14:19:22 +0000 (16:19 +0200)]
altera/common: fix AsyncResetSynchronizer polarity and simplify

5 years agobuild/xilinx/common: improve presentation
Florent Kermarrec [Thu, 8 Aug 2019 14:08:55 +0000 (16:08 +0200)]
build/xilinx/common: improve presentation

5 years agomicrosemi/common: improve presentation
Florent Kermarrec [Thu, 8 Aug 2019 14:06:40 +0000 (16:06 +0200)]
microsemi/common: improve presentation

5 years agobuild/altera/common: improve presentation
Florent Kermarrec [Thu, 8 Aug 2019 14:02:34 +0000 (16:02 +0200)]
build/altera/common: improve presentation

5 years agoplatforms/default_clk_period: use 1e9/freq
Florent Kermarrec [Wed, 7 Aug 2019 06:36:04 +0000 (08:36 +0200)]
platforms/default_clk_period: use 1e9/freq

5 years agotargets/minispartan6/crg: only keep S6PLL code
Florent Kermarrec [Wed, 7 Aug 2019 06:29:59 +0000 (08:29 +0200)]
targets/minispartan6/crg: only keep S6PLL code

5 years agocores/clock: juse use 1e9/freq instead of period_ns
Florent Kermarrec [Wed, 7 Aug 2019 06:29:20 +0000 (08:29 +0200)]
cores/clock: juse use 1e9/freq instead of period_ns

5 years agocores/clock/s6pll: add phase support
Florent Kermarrec [Wed, 7 Aug 2019 06:18:54 +0000 (08:18 +0200)]
cores/clock/s6pll: add phase support

5 years agocores/clock/xilinx: change clkfbout_mult loop order to select highest vco_freq
Florent Kermarrec [Wed, 7 Aug 2019 06:17:44 +0000 (08:17 +0200)]
cores/clock/xilinx: change clkfbout_mult loop order to select highest vco_freq

5 years agolitex_term: make sure to unconfigure console when board is unplugged
Florent Kermarrec [Tue, 6 Aug 2019 06:46:25 +0000 (08:46 +0200)]
litex_term: make sure to unconfigure console when board is unplugged

5 years agosoc/integration/builder: -x
Florent Kermarrec [Tue, 6 Aug 2019 05:56:45 +0000 (07:56 +0200)]
soc/integration/builder: -x

5 years agocores: -x on spi.py
Florent Kermarrec [Mon, 5 Aug 2019 08:36:38 +0000 (10:36 +0200)]
cores: -x on spi.py

5 years agowishbone/SRAM: make read_only emited verilog code compatible with all tools
Florent Kermarrec [Mon, 5 Aug 2019 07:08:56 +0000 (09:08 +0200)]
wishbone/SRAM: make read_only emited verilog code compatible with all tools

Quartus was not able to implement ROM correctly, see #228

5 years agosoc/cores/uart: add FT245 FIFO mode support (sync & async)
Florent Kermarrec [Sun, 4 Aug 2019 10:22:35 +0000 (12:22 +0200)]
soc/cores/uart: add FT245 FIFO mode support (sync & async)

5 years agobuild/altera/quartus: use .bat on win32/cygwin
Florent Kermarrec [Fri, 2 Aug 2019 08:27:38 +0000 (10:27 +0200)]
build/altera/quartus: use .bat on win32/cygwin

5 years agobuild/xilinx/vivado: change severity of Common 17-55 critical warning to warning
Florent Kermarrec [Thu, 1 Aug 2019 19:03:05 +0000 (21:03 +0200)]
build/xilinx/vivado: change severity of Common 17-55 critical warning to warning

5 years agocores/pwm: remove default CSR reset values.
Florent Kermarrec [Mon, 29 Jul 2019 06:37:46 +0000 (08:37 +0200)]
cores/pwm: remove default CSR reset values.

5 years agosoc: generate git header and show migen/litex git sha1 in bios
Florent Kermarrec [Sat, 27 Jul 2019 18:27:53 +0000 (20:27 +0200)]
soc: generate git header and show migen/litex git sha1 in bios

5 years agoMerge pull request #223 from sergachev/master
enjoy-digital [Thu, 25 Jul 2019 18:24:25 +0000 (20:24 +0200)]
Merge pull request #223 from sergachev/master

support vivado incremental implementation

5 years agosupport vivado incremental implementation
Ilia Sergachev [Thu, 25 Jul 2019 17:18:11 +0000 (19:18 +0200)]
support vivado incremental implementation

5 years agoMerge pull request #222 from antmicro/bump_vexriscv
enjoy-digital [Thu, 25 Jul 2019 07:25:26 +0000 (09:25 +0200)]
Merge pull request #222 from antmicro/bump_vexriscv

cpu/vexriscv: bump submodule

5 years agocpu/vexriscv: bump submodule
Mateusz Holenko [Thu, 25 Jul 2019 06:43:35 +0000 (08:43 +0200)]
cpu/vexriscv: bump submodule

5 years agobios/sdram: fix compilation warning
Florent Kermarrec [Thu, 25 Jul 2019 05:46:14 +0000 (07:46 +0200)]
bios/sdram: fix compilation warning

5 years agotest/test_axi: remove use of rand_wait, rename rand_level to random
Florent Kermarrec [Tue, 23 Jul 2019 18:56:49 +0000 (20:56 +0200)]
test/test_axi: remove use of rand_wait, rename rand_level to random

5 years agosoc_core: round memory regions size/length to next power of 2 (if not already a power...
Florent Kermarrec [Tue, 23 Jul 2019 18:35:28 +0000 (20:35 +0200)]
soc_core: round memory regions size/length to next power of 2 (if not already a power of 2)

5 years agoMerge pull request #221 from antmicro/bump_vexriscv
enjoy-digital [Tue, 23 Jul 2019 10:01:13 +0000 (12:01 +0200)]
Merge pull request #221 from antmicro/bump_vexriscv

cpu/vexriscv: bump submodule

5 years agocpu/vexriscv: bump submodule
Mateusz Holenko [Tue, 23 Jul 2019 09:48:00 +0000 (11:48 +0200)]
cpu/vexriscv: bump submodule

5 years agobios/boot: fix default EMULATOR_RAM_BASE
Florent Kermarrec [Tue, 23 Jul 2019 08:28:19 +0000 (10:28 +0200)]
bios/boot: fix default EMULATOR_RAM_BASE

5 years agocores/clock: cleanup
Florent Kermarrec [Tue, 23 Jul 2019 07:53:48 +0000 (09:53 +0200)]
cores/clock: cleanup

5 years agocores/clock: add initial iCE40 support
Florent Kermarrec [Tue, 23 Jul 2019 07:27:20 +0000 (09:27 +0200)]
cores/clock: add initial iCE40 support

5 years agocores/spi_flash/add_clk_primitive: return if clk primitive is not needed
Florent Kermarrec [Mon, 22 Jul 2019 19:55:07 +0000 (21:55 +0200)]
cores/spi_flash/add_clk_primitive: return if clk primitive is not needed

5 years agobios/boot: define EMULATOR_RAM_BASE if not defined, add KERNEL_IMAGE_RAM_OFFSET
Florent Kermarrec [Mon, 22 Jul 2019 19:32:46 +0000 (21:32 +0200)]
bios/boot: define EMULATOR_RAM_BASE if not defined, add KERNEL_IMAGE_RAM_OFFSET

5 years agosoc_core: fix cpu_variant definition
Florent Kermarrec [Mon, 22 Jul 2019 10:38:16 +0000 (12:38 +0200)]
soc_core: fix cpu_variant definition

5 years agobios/boot: fix booting rework
Florent Kermarrec [Mon, 22 Jul 2019 09:43:22 +0000 (11:43 +0200)]
bios/boot: fix booting rework

- keep emulator.bin in a specific ram (for now)
- print message when falling back to boot.bin
- print destination on tftp download (to ease debug)

5 years agosoc_core: fix cpu_variant config (we don't want the extension)
Florent Kermarrec [Mon, 22 Jul 2019 09:41:01 +0000 (11:41 +0200)]
soc_core: fix cpu_variant config (we don't want the extension)

5 years agoMerge pull request #216 from antmicro/booting_vexriscv_linux
enjoy-digital [Mon, 22 Jul 2019 09:44:20 +0000 (11:44 +0200)]
Merge pull request #216 from antmicro/booting_vexriscv_linux

Rework booting Linux on VexRiscv

5 years agocores/spi_flash: add SpiFlashCommon and use it to add clk primitives (7-Series/ECP5...
Florent Kermarrec [Mon, 22 Jul 2019 08:28:03 +0000 (10:28 +0200)]
cores/spi_flash: add SpiFlashCommon and use it to add clk primitives (7-Series/ECP5 support for now)

5 years agoplatforms/versa_ecp5: add spiflash pads
Florent Kermarrec [Mon, 22 Jul 2019 08:25:55 +0000 (10:25 +0200)]
platforms/versa_ecp5: add spiflash pads

5 years agosoc_core: optimize mem_decoder
Florent Kermarrec [Mon, 22 Jul 2019 06:53:18 +0000 (08:53 +0200)]
soc_core: optimize mem_decoder

Non-optimized version was tested on 7-series and was additional resource usage
was not noticeable. This does not seems to be the case on iCE40 (see #220), so
hand optimize it. On 256MB aligned addresses, it should be equivalent to the
old decoder used by previously in LiteX.

The only requirement is that to have address aligned on size, which was already
the case. An assertion will trigger it this condition is not respected.

5 years agocores/up5ksram: optimize bus.adr decoding
Florent Kermarrec [Mon, 22 Jul 2019 05:55:47 +0000 (07:55 +0200)]
cores/up5ksram: optimize bus.adr decoding

5 years agocores/up5kspram: simplify and add support for all width/depth configurations
Florent Kermarrec [Sun, 21 Jul 2019 17:27:43 +0000 (19:27 +0200)]
cores/up5kspram: simplify and add support for all width/depth configurations

5 years agocores/pwm: remove clock_domain support (better to use ClockDomainsRenamer), make...
Florent Kermarrec [Sat, 20 Jul 2019 10:57:32 +0000 (12:57 +0200)]
cores/pwm: remove clock_domain support (better to use ClockDomainsRenamer), make csr optional

5 years agocores/spi: rename add_control paramter to add_csr
Florent Kermarrec [Sat, 20 Jul 2019 10:54:45 +0000 (12:54 +0200)]
cores/spi: rename add_control paramter to add_csr

5 years agosoc_core: add SoCMini class (SoCCore with no cpu, sram, uart, timer) for simple designs
Florent Kermarrec [Sat, 20 Jul 2019 10:52:44 +0000 (12:52 +0200)]
soc_core: add SoCMini class (SoCCore with no cpu, sram, uart, timer) for simple designs

5 years agoMerge pull request #219 from flammit/fix-ecp5-pll
enjoy-digital [Tue, 16 Jul 2019 05:48:22 +0000 (07:48 +0200)]
Merge pull request #219 from flammit/fix-ecp5-pll

soc: cores: fix name of EHXPLLL output clock in ECP5PLL

5 years agobios/boot: rework netboot/flashboot for VexRiscv in linux variant
Mateusz Holenko [Thu, 11 Jul 2019 08:14:27 +0000 (10:14 +0200)]
bios/boot: rework netboot/flashboot for VexRiscv in linux variant

Get rid of NETBOOT_LINUX_VEXRISCV/FLASHBOOT_LINUX_VEXRISCV defines
and use information about CPU_TYPE and CPU_VARIANT instead.

Use common kernel/rootfs/device tree/emulator images layout
when booting over network and from flash.

5 years agosoc_core: generate extra string-based config defines
Mateusz Holenko [Thu, 11 Jul 2019 08:13:54 +0000 (10:13 +0200)]
soc_core: generate extra string-based config defines

C preprocessor does not allow to compare strings, so
the current defines are not usable at the compile time.
This adds new defines that can be ifdefed.

5 years agosoc_core: include information about cpu variant in csv and headers
Mateusz Holenko [Thu, 11 Jul 2019 08:13:28 +0000 (10:13 +0200)]
soc_core: include information about cpu variant in csv and headers

5 years agosoc: cores: fix name of EHXPLLL output clock in ECP5PLL
Francis Lam [Sun, 14 Jul 2019 19:27:28 +0000 (12:27 -0700)]
soc: cores: fix name of EHXPLLL output clock in ECP5PLL

5 years agocores/spi: fix/simplify loopback
Florent Kermarrec [Sat, 13 Jul 2019 11:10:24 +0000 (13:10 +0200)]
cores/spi: fix/simplify loopback

5 years agoREADME: update banner
Florent Kermarrec [Sat, 13 Jul 2019 11:04:00 +0000 (13:04 +0200)]
README: update banner

5 years agocores/spi: move CSR control/status to add_control method, add loopback capability...
Florent Kermarrec [Sat, 13 Jul 2019 10:54:24 +0000 (12:54 +0200)]
cores/spi: move CSR control/status to add_control method, add loopback capability and simple xfer loopback test

Moving control/status registers to add_control method allow using SPIMaster directly with exposed signals.
Add loopback capability (mostly for simulation, but can be useful on hardware too).

5 years agosoc/cores: add ECC (Error Correcting Code)
Florent Kermarrec [Sat, 13 Jul 2019 09:44:29 +0000 (11:44 +0200)]
soc/cores: add ECC (Error Correcting Code)

Hamming codes with additional parity (SECDED):
- Single Error Correction
- Double Error Detection

5 years agoplatforms/tinyfpga_bx: add serial extension
Florent Kermarrec [Sat, 13 Jul 2019 09:43:16 +0000 (11:43 +0200)]
platforms/tinyfpga_bx: add serial extension

5 years agoREADME: add a few links to papers/presentations/tutorials
Florent Kermarrec [Fri, 12 Jul 2019 18:11:44 +0000 (20:11 +0200)]
README: add a few links to papers/presentations/tutorials

5 years agoMerge pull request #218 from railnova/zynq
enjoy-digital [Fri, 12 Jul 2019 16:00:03 +0000 (18:00 +0200)]
Merge pull request #218 from railnova/zynq

[fix] Slave interface HP0 clk name

5 years ago[fix] Slave interface HP0 clk name
chmousset [Fri, 12 Jul 2019 14:37:23 +0000 (16:37 +0200)]
[fix] Slave interface HP0 clk name

5 years agoMerge pull request #217 from sergachev/master
enjoy-digital [Fri, 12 Jul 2019 12:44:53 +0000 (14:44 +0200)]
Merge pull request #217 from sergachev/master

spi: change CSR to CSRStorage

5 years agospi: change CSR to CSRStorage
Ilia Sergachev [Fri, 12 Jul 2019 12:12:51 +0000 (14:12 +0200)]
spi: change CSR to CSRStorage

5 years agosoc_zynq: use zynq fabric reset as sys reset
Florent Kermarrec [Fri, 12 Jul 2019 07:52:40 +0000 (09:52 +0200)]
soc_zynq: use zynq fabric reset as sys reset

5 years agosoc_zynq: add missing axi hp0 clock
Florent Kermarrec [Wed, 10 Jul 2019 14:51:08 +0000 (16:51 +0200)]
soc_zynq: add missing axi hp0 clock

5 years agosoc_zynq: move axi gp0 clock connection to add_gp0 method
Florent Kermarrec [Wed, 10 Jul 2019 14:50:06 +0000 (16:50 +0200)]
soc_zynq: move axi gp0 clock connection to add_gp0 method

5 years agosoc_core: use fixed 16MB CSR address space
Florent Kermarrec [Wed, 10 Jul 2019 08:37:32 +0000 (10:37 +0200)]
soc_core: use fixed 16MB CSR address space

Using too small CSR address space cause a regression on PCIe SoC, this would
need to be understood if we want to reduce CSR address space under 16MB.

5 years agosoc_sdram: limit main_ram to 512MB for now
Florent Kermarrec [Tue, 9 Jul 2019 10:14:50 +0000 (12:14 +0200)]
soc_sdram: limit main_ram to 512MB for now

Otherwise breaks linux-on-litex-vexriscv for targets with 1GB of ram, could
be removed when mem_map will be reworked on linux-on-litex-vexriscv.

5 years agocompiler-rt: update to new location, fixes #209
Florent Kermarrec [Mon, 8 Jul 2019 21:02:43 +0000 (23:02 +0200)]
compiler-rt: update to new location, fixes #209

5 years agosoc_core: declare csr address size when registering csr, fixes #212
Florent Kermarrec [Mon, 8 Jul 2019 20:58:07 +0000 (22:58 +0200)]
soc_core: declare csr address size when registering csr, fixes #212

5 years agosoc_cores: fix typos
Florent Kermarrec [Mon, 8 Jul 2019 20:56:14 +0000 (22:56 +0200)]
soc_cores: fix typos

5 years agoMerge pull request #214 from gsomlo/gls-alignment-fixup
enjoy-digital [Mon, 8 Jul 2019 17:03:28 +0000 (19:03 +0200)]
Merge pull request #214 from gsomlo/gls-alignment-fixup

soc_core: additional csr_alignment follow-up fixes

5 years agosoc_core: additional csr_alignment follow-up fixes
Gabriel L. Somlo [Mon, 8 Jul 2019 13:43:40 +0000 (09:43 -0400)]
soc_core: additional csr_alignment follow-up fixes

- Update a few additional places to use DFII_ADDR_SHIFT instead of
  a hard-coded 4, which assumed 32-bit alignment.

- Force 64-bit alignment Rocket -- the only supported configuration!

This is a fixup for commit f4770219, tested on Rocket and 64bit Linux.

Signed-off-by: Gabriel Somlo <gsomlo@gmail.com>
5 years agosoc_core: add csr_alignment to allow 64-bit alignment with 64-bit CPUs
Florent Kermarrec [Mon, 8 Jul 2019 07:53:52 +0000 (09:53 +0200)]
soc_core: add csr_alignment to allow 64-bit alignment with 64-bit CPUs

5 years agosoc/integration: uniformize configuration constants declaration in SoCs (use self...
Florent Kermarrec [Mon, 8 Jul 2019 06:57:05 +0000 (08:57 +0200)]
soc/integration: uniformize configuration constants declaration in SoCs (use self.config instead self.add_constant)

5 years agosoftware/libbase/id: update code (length is now fixed to 256)
Florent Kermarrec [Sat, 6 Jul 2019 15:18:34 +0000 (17:18 +0200)]
software/libbase/id: update code (length is now fixed to 256)

5 years agocores: add simple PWM (Pulse Width Modulation) module
Florent Kermarrec [Fri, 5 Jul 2019 17:38:58 +0000 (19:38 +0200)]
cores: add simple PWM (Pulse Width Modulation) module

5 years agocore/spi: make cs_n optional (sometimes managed externally)
Florent Kermarrec [Fri, 5 Jul 2019 17:18:52 +0000 (19:18 +0200)]
core/spi: make cs_n optional (sometimes managed externally)

5 years agocores/spi_flash: add non-memory mapped S7SPIFlash modules based on SPIMaster (for...
Florent Kermarrec [Fri, 5 Jul 2019 17:01:55 +0000 (19:01 +0200)]
cores/spi_flash: add non-memory mapped S7SPIFlash modules based on SPIMaster (for design were we only want to re-program the bistream)

5 years agocores: add ICAP core (tested with reconfiguration commands)
Florent Kermarrec [Fri, 5 Jul 2019 16:30:34 +0000 (18:30 +0200)]
cores: add ICAP core (tested with reconfiguration commands)

5 years agocores: add simple and minimal hardware SPI Master with CPOL=0, CPHA=0 and build time...
Florent Kermarrec [Fri, 5 Jul 2019 13:49:17 +0000 (15:49 +0200)]
cores: add simple and minimal hardware SPI Master with CPOL=0, CPHA=0 and build time configurable data_width and frequency.

5 years agosoc/cores/spi: remove too complicated and does not seem reliable in all cases.
Florent Kermarrec [Fri, 5 Jul 2019 12:37:46 +0000 (14:37 +0200)]
soc/cores/spi: remove too complicated and does not seem reliable in all cases.

5 years agocores: add bitbang class with minimal hardware for I2C/SPI software bit-banging
Florent Kermarrec [Fri, 5 Jul 2019 12:26:10 +0000 (14:26 +0200)]
cores: add bitbang class with minimal hardware for I2C/SPI software bit-banging