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base: Iterable CircularQueue implementation
2018-12-06 Rekai Gonzalez-Alber... base: Iterable CircularQueue implementation
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2018-12-06 Giacomo Travagliniext: Build googlemock with googletest
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2018-12-06 Giacomo Travagliniext: Import googlemock, release version 1.8.0
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2018-12-03 Giacomo Gabriellibase: Add type alias for raw pointer in RefCountingPtr
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2018-11-28 Matteo Andreozziarch-arm: clang compilation fixes
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2018-11-28 Giacomo Travaglinitests: Convert IniFile unit test to a GTest
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2018-11-16 Matteo Andreozzimem: avoid calling regStat twice on a QoSPolicy
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2018-11-14 Giacomo Travagliniarch-arm: Print register name when warning on AT instructions
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2018-11-14 Giacomo Travaglinisim: Move BitUnion overloading to show/parseParams
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2018-11-14 Giacomo Travaglinisim: Move paramIn/Out definition to header file
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2018-11-12 Giacomo Travaglinisystemc: Push python headers on top of sources
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2018-11-07 Giacomo Travagliniarch-arm: Deprecate usage of legacy bootloader patching
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2018-11-07 Giacomo Travagliniarch-arm: ArmSystem::resetAddr64 renamed to be used...
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2018-11-07 Giacomo Travagliniarch-arm: Implement AArch32 RVBAR
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2018-11-07 Giacomo Travagliniarch-arm: Remove SCTLR.VE bit
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2018-11-07 Giacomo Travagliniarch-arm: Refactor ISA::clear by adding a ISA::clear32...
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2018-11-07 Giacomo Travagliniarch-arm: Remove MISCREG commented numbers
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2018-10-26 Giacomo Travagliniarch-arm: IMPDEF for SYS instruction with CRn = {11...
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2018-10-26 Giacomo Travagliniarch-arm: AArch64 Instruction for MISCREG_IMPDEF_UNIMPL
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2018-10-26 Giacomo Travagliniarch-arm: Refactor AArch64 MSR/MRS trapping
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2018-10-26 Giacomo Travagliniarch-arm: Trap to EL2 only if not in Secure State
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2018-10-26 Giacomo Travagliniarch-arm: Fix HVC trapping beahviour
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2018-10-26 Giacomo Travagliniarch-arm: CPTR_EL3.TCPAC traps EL2 accesses to CPACR_EL1
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2018-10-17 Adrien Pesledev-arm: Don't panic when EOIR a non active PPI
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2018-10-17 Adrien Pesledev-arm: Fix Gicv2 distributor group register
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2018-10-09 Giacomo Travagliniarch-arm: Add have_crypto System parameter
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2018-10-09 Giacomo Travaglinicpu: Fix MinorCPU executing Crypto Instructions
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2018-10-09 Giacomo Travagliniarch-arm: AArch64 Crypto AES
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2018-10-09 Giacomo Travagliniarch-arm: AArch64 Crypto SHA
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2018-10-09 Matt Horsnellarch-arm: AArch32 Crypto AES
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2018-10-09 Matt Horsnellarch-arm: AArch32 Crypto SHA
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2018-10-08 Matteo Andreozziarch-arm: Mark ArmProcess method as override
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2018-10-02 Giacomo Travaglinisim-se: Set ArmProcess64 hwcaps depending on ID regs
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2018-10-02 Giacomo Travaglinisim-se: Different HWCAP for ArmProcess32/64
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2018-10-01 Giacomo Travagliniarch-arm: Implement AArch64 ID regs as bitunions
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2018-10-01 Giacomo Travagliniarch-arm: Implement AArch64 ID_AA64MMFR2_EL1 register
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2018-10-01 Giacomo Travagliniarch-arm: Move MiscReg BitUnions into a separate header...
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2018-10-01 Giacomo Travagliniarch-arm: Init AArch64 ID registers in SE mode
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2018-10-01 Giacomo Travaglinicpu: Fix typo in header guard for Noncaching cpu
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2018-10-01 Giacomo Travaglinidev-arm: Enable FIQ signaling for Group0 interrupts...
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2018-10-01 Giacomo Travaglinidev-arm: Create postFiq events for GICv2
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2018-10-01 Giacomo Travaglinidev-arm: Implement GICv2 GICD_IGROUPR register
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2018-10-01 Giacomo Travaglinidev-arm: Fix GICv2 cpu interrupt enable flag
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2018-10-01 Adrien Pesledev-arm: Add basic support for level sensitive SPIs...
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2018-10-01 Giacomo Travaglinisim: Extend (UN)SERIALIZE_ARRAY to BitUnions
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2018-09-28 Giacomo Travaglinidev-arm: Make CpuLocalTimer use standard ArmInterruptPin
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2018-09-28 Giacomo Travaglinidev-arm: Take into account PPI enable bit
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2018-09-28 Giacomo Travagliniarch-arm: raise/clear IRQ when writing to PMOVSCLR/SET
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2018-09-17 Giacomo Travaglinimem: Implement QoS Proportional Fair policy
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2018-09-10 Giacomo Travaglinidev-arm: Make GenericTimer use standard ArmInterruptPin
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2018-09-10 Giacomo Travaglinidev-arm: Factory SimObject for generating ArmInterruptPin
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2018-09-10 Andreas Sandbergarm: Use the interrupt adaptor in the PMU
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2018-09-10 Andreas Sandbergarm: Add support for tracking TCs in ISA devices
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2018-09-10 Andreas Sandbergdev, arm: Add misc reg tracing to the generic timer
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2018-09-10 Giacomo Travaglinidev-arm: Create a getter for ArmInterruptPin ID number
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2018-09-07 Matteo Andreozzimem: Make DRAMCtrl a QoS-aware Memory Controller
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2018-09-07 Giacomo Travaglinimem: Implement base QoS Policies.
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2018-09-07 Matteo Andreozzimem: Add a simple QoS-aware Memory Controller
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2018-09-07 Matteo Andreozzimem: Add a QoS-aware Memory Controller type
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2018-09-07 Giacomo Travaglinisim: Add System method for MasterID lookup
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2018-08-24 Giacomo Travaglinicpu: Stream/SubstreamID support in TrafficGen
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2018-08-24 Michiel W. van Tolcpu: Turn BaseTrafficGen numSuppressed into a stat
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2018-08-22 Stanislaw Czerniawskimem: Add StreamID and SubstreamID
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2018-08-10 Giacomo Gabrielliarm: Add support for RCpc load-acquire instructions...
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2018-07-26 Giacomo Travaglinibase: Fix ucontext compilation error for macOS
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2018-07-25 Giacomo Travaglinicpu: Warn when (un)serializing a traffic generator
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2018-07-25 Giacomo Travaglinicpu: Allow creation of traffic gen from generic SimObjects
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2018-07-16 Giacomo Travagliniarch-arm: Introduce ARMv8.1 Virtual Timer System Registers
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2018-07-16 Giacomo Travagliniarch-arm: Introduce RAS System Registers
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2018-06-28 Giacomo Travaglinibase: Add an asymmetrical Coroutine class
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2018-06-22 Giacomo Travagliniarch-arm: AArch32 execution triggering AArch64 SW Break
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2018-06-22 Giacomo Travagliniarch-arm: BadMode checking if corresponding EL is implemented
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2018-06-21 Giacomo Travaglinicpu: Fix bug introduced by RequestPtr type change
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2018-06-14 Giacomo Travagliniarch-arm: Adapting IllegalExecution fault for AArch32
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2018-06-14 Giacomo Travagliniarch-arm: Add Illegal Execution flag to PCState
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2018-06-14 Giacomo Travagliniarch-arm: Read APSR in User Mode
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2018-06-13 Giacomo Travagliniarch-arm: Fix missing Request allocation
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2018-06-11 Giacomo Travaglinimisc: Using smart pointers for memory Requests
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2018-06-11 Giacomo Travaglinimisc: Substitute pointer to Request with aliased RequestPtr
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2018-05-29 Giacomo Travagliniarch-arm: ISA param for treating MISCREG_IMPDEF_UNIMPL...
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2018-05-29 Giacomo Travagliniarch-arm: Remove unusued MISCREG_A64_UNIMPL
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2018-05-29 Giacomo Travagliniarch-arm: MPIDR.MT = 1 in a multithreaded system
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2018-05-29 Giacomo Travagliniarch-arm: S3_<op1>_<Cn>_<Cm>_<op2> are Implementation...
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2018-05-29 Giacomo Travaglinicpu: Avoid unnecessary dynamic_pointer_cast in atomic...
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2018-05-29 Giacomo Travagliniarch-arm: Implement ARMv8.1 TTBR1_EL2 register
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2018-05-29 Giacomo Travagliniarch-arm: Add E2H bit to HCR_EL2 System register
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2018-05-18 Wendy Elsassermem: Add support for more flexible DRAM timing and...
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2018-05-18 Wendy Elsassermem: Optimize self-refresh entry
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2018-05-09 Giacomo Travaglinisim: Remove trailing dot when assigning a master's...
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2018-05-08 Giacomo Travagliniarch-arm: Map ID_x_EL1 registers to AArch32 version
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2018-05-04 Giacomo Travagliniscons: Fix --with-ubsan/asan compilation flags
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2018-04-27 Giacomo Travaglinisim,cpu,mem,arch: Introduced MasterInfo data structure
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2018-04-19 Giacomo Travagliniarch-arm: Add ARMv8.1 TTBR1_EL2 register
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2018-04-19 Giacomo Travagliniarch-arm: Fix Unknown Instruction disassemble
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2018-04-19 Giacomo Travagliniarch-arm: Change disassemble when MSR to UNKNOWN register
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2018-04-18 Chuan Zhuarch-arm: Fix masking in CPACR_EL1
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2018-04-18 Chuan Zhuarch-arm: Mask out unsupported trapped exception handling...
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2018-04-18 Chuan Zhuarch-arm: Fix FPEXC32_EL2 to FPEXC mapping
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2018-04-18 Giacomo Travagliniarch-arm: Adding MiscReg Priv (EL1) global flag
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2018-04-18 Chuan Zhuarch-arm: Correct masking of cp10 and cp11 in CPACR
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