| 2018-09-10 |
Andreas Sandberg | dev, arm: Add misc reg tracing to the generic timer
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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commit | commitdiff | tree |
| 2018-09-10 |
Giacomo Travaglini | dev-arm: Create a getter for ArmInterruptPin ID number
...off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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commit | commitdiff | tree |
| 2018-09-07 |
Matteo Andreozzi | mem: Make DRAMCtrl a QoS-aware Memory Controller
...off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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commit | commitdiff | tree |
| 2018-09-07 |
Giacomo Travaglini | mem: Implement base QoS Policies.
...off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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commit | commitdiff | tree |
| 2018-09-07 |
Matteo Andreozzi | mem: Add a simple QoS-aware Memory Controller
...off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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commit | commitdiff | tree |
| 2018-09-07 |
Matteo Andreozzi | mem: Add a QoS-aware Memory Controller type
...off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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commit | commitdiff | tree |
| 2018-09-07 |
Giacomo Travaglini | sim: Add System method for MasterID lookup
...off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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commit | commitdiff | tree |
| 2018-08-24 |
Giacomo Travaglini | cpu: Stream/SubstreamID support in TrafficGen
...off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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commit | commitdiff | tree |
| 2018-08-24 |
Michiel W. van Tol | cpu: Turn BaseTrafficGen numSuppressed into a stat
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commit | commitdiff | tree |
| 2018-08-22 |
Stanislaw Czerniawski | mem: Add StreamID and SubstreamID
...off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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commit | commitdiff | tree |
| 2018-08-10 |
Giacomo Gabrielli | arm: Add support for RCpc load-acquire instructions...
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
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commit | commitdiff | tree |
| 2018-07-26 |
Giacomo Travaglini | base: Fix ucontext compilation error for macOS
...off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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commit | commitdiff | tree |
| 2018-07-25 |
Giacomo Travaglini | cpu: Warn when (un)serializing a traffic generator
...off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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commit | commitdiff | tree |
| 2018-07-25 |
Giacomo Travaglini | cpu: Allow creation of traffic gen from generic SimObjects
...off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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commit | commitdiff | tree |
| 2018-07-16 |
Giacomo Travaglini | arch-arm: Introduce ARMv8.1 Virtual Timer System Registers
...off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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commit | commitdiff | tree |
| 2018-07-16 |
Giacomo Travaglini | arch-arm: Introduce RAS System Registers
...off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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commit | commitdiff | tree |
| 2018-06-28 |
Giacomo Travaglini | base: Add an asymmetrical Coroutine class
...off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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commit | commitdiff | tree |
| 2018-06-22 |
Giacomo Travaglini | arch-arm: AArch32 execution triggering AArch64 SW Break
...off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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commit | commitdiff | tree |
| 2018-06-22 |
Giacomo Travaglini | arch-arm: BadMode checking if corresponding EL is implemented
...off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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commit | commitdiff | tree |
| 2018-06-21 |
Giacomo Travaglini | cpu: Fix bug introduced by RequestPtr type change
...off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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commit | commitdiff | tree |
| 2018-06-14 |
Giacomo Travaglini | arch-arm: Adapting IllegalExecution fault for AArch32
...off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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commit | commitdiff | tree |
| 2018-06-14 |
Giacomo Travaglini | arch-arm: Add Illegal Execution flag to PCState
...off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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commit | commitdiff | tree |
| 2018-06-14 |
Giacomo Travaglini | arch-arm: Read APSR in User Mode
...off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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commit | commitdiff | tree |
| 2018-06-13 |
Giacomo Travaglini | arch-arm: Fix missing Request allocation
...off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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commit | commitdiff | tree |
| 2018-06-11 |
Giacomo Travaglini | misc: Using smart pointers for memory Requests
...off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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commit | commitdiff | tree |
| 2018-06-11 |
Giacomo Travaglini | misc: Substitute pointer to Request with aliased RequestPtr
...off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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commit | commitdiff | tree |
| 2018-05-29 |
Giacomo Travaglini | arch-arm: ISA param for treating MISCREG_IMPDEF_UNIMPL...
...off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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commit | commitdiff | tree |
| 2018-05-29 |
Giacomo Travaglini | arch-arm: Remove unusued MISCREG_A64_UNIMPL
...off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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commit | commitdiff | tree |
| 2018-05-29 |
Giacomo Travaglini | arch-arm: MPIDR.MT = 1 in a multithreaded system
...off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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commit | commitdiff | tree |
| 2018-05-29 |
Giacomo Travaglini | arch-arm: S3_<op1>_<Cn>_<Cm>_<op2> are Implementation...
...off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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commit | commitdiff | tree |
| 2018-05-29 |
Giacomo Travaglini | cpu: Avoid unnecessary dynamic_pointer_cast in atomic...
...off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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commit | commitdiff | tree |
| 2018-05-29 |
Giacomo Travaglini | arch-arm: Implement ARMv8.1 TTBR1_EL2 register
...off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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commit | commitdiff | tree |
| 2018-05-29 |
Giacomo Travaglini | arch-arm: Add E2H bit to HCR_EL2 System register
...off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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commit | commitdiff | tree |
| 2018-05-18 |
Wendy Elsasser | mem: Add support for more flexible DRAM timing and...
|
commit | commitdiff | tree |
| 2018-05-18 |
Wendy Elsasser | mem: Optimize self-refresh entry
|
commit | commitdiff | tree |
| 2018-05-09 |
Giacomo Travaglini | sim: Remove trailing dot when assigning a master's...
...off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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commit | commitdiff | tree |
| 2018-05-08 |
Giacomo Travaglini | arch-arm: Map ID_x_EL1 registers to AArch32 version
...off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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commit | commitdiff | tree |
| 2018-05-04 |
Giacomo Travaglini | scons: Fix --with-ubsan/asan compilation flags
...off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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commit | commitdiff | tree |
| 2018-04-27 |
Giacomo Travaglini | sim,cpu,mem,arch: Introduced MasterInfo data structure
...off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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commit | commitdiff | tree |
| 2018-04-19 |
Giacomo Travaglini | arch-arm: Add ARMv8.1 TTBR1_EL2 register
...off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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commit | commitdiff | tree |
| 2018-04-19 |
Giacomo Travaglini | arch-arm: Fix Unknown Instruction disassemble
...off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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commit | commitdiff | tree |
| 2018-04-19 |
Giacomo Travaglini | arch-arm: Change disassemble when MSR to UNKNOWN register
...off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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commit | commitdiff | tree |
| 2018-04-18 |
Chuan Zhu | arch-arm: Fix masking in CPACR_EL1
|
commit | commitdiff | tree |
| 2018-04-18 |
Chuan Zhu | arch-arm: Mask out unsupported trapped exception handling...
|
commit | commitdiff | tree |
| 2018-04-18 |
Chuan Zhu | arch-arm: Fix FPEXC32_EL2 to FPEXC mapping
|
commit | commitdiff | tree |
| 2018-04-18 |
Giacomo Travaglini | arch-arm: Adding MiscReg Priv (EL1) global flag
...off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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commit | commitdiff | tree |
| 2018-04-18 |
Chuan Zhu | arch-arm: Correct masking of cp10 and cp11 in CPACR
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commit | commitdiff | tree |
| 2018-04-18 |
Giacomo Travaglini | arch-arm: Using explicit invalidation in TLB
...off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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commit | commitdiff | tree |
| 2018-04-17 |
Giacomo Travaglini | arch-arm: Fix secure MiscReg access when EL3 is not...
...off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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commit | commitdiff | tree |
| 2018-04-10 |
Giacomo Travaglini | arch-arm: Fix mrc,mcr to cop14 disassemble
...off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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commit | commitdiff | tree |
| 2018-04-06 |
Giacomo Travaglini | arch-arm: Add support for Tarmac trace generation
...off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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commit | commitdiff | tree |
| 2018-04-06 |
Giacomo Travaglini | arch-arm: Add support for Tarmac trace-based simulation
...off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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commit | commitdiff | tree |
| 2018-04-06 |
Giacomo Travaglini | arch-arm: Fix AArch32 branch instructions disassemble
...off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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commit | commitdiff | tree |
| 2018-04-06 |
Giacomo Travaglini | arch-arm: Fix secure write of SCTLR when EL3 is AArch64
...off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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commit | commitdiff | tree |
| 2018-04-06 |
Giacomo Travaglini | arch-arm: Correct mcrr,mrrc disassemble
...off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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commit | commitdiff | tree |
| 2018-03-23 |
Giacomo Travaglini | arch-arm: Distinguish IS TLBI from non-IS
...off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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commit | commitdiff | tree |
| 2018-03-23 |
Giacomo Travaglini | arch-arm: Created function for TLB ASID Invalidation
...off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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commit | commitdiff | tree |
| 2018-03-14 |
Giacomo Travaglini | tests: Add missing print replacements in tests subdir
...off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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commit | commitdiff | tree |
| 2018-03-14 |
Giacomo Travaglini | arch-arm: ERET from AArch64 to AArch32 ignore MSBs
...off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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commit | commitdiff | tree |
| 2018-03-12 |
Giacomo Travaglini | arch-arm: Adding IPA-Based Invalidating instructions
...off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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commit | commitdiff | tree |
| 2018-03-12 |
Giacomo Travaglini | arch-arm: Implement missing aarch32 TLBI registers
...off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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commit | commitdiff | tree |
| 2018-03-09 |
Giacomo Travaglini | tests: Python regression scripts using new print function
...off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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commit | commitdiff | tree |
| 2018-03-08 |
Giacomo Travaglini | arch-arm: Enable Debug IFSC when faulting to aarch64...
...off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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commit | commitdiff | tree |
| 2018-03-08 |
Giacomo Travaglini | arch-arm: Fix FSC generation in AbortFault
...off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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commit | commitdiff | tree |
| 2018-03-08 |
Giacomo Travaglini | arch-arm: Introduce update method in ArmFault class
...off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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commit | commitdiff | tree |
| 2018-03-08 |
Giacomo Travaglini | arch-arm: Fix PCAlignmentFault routing to Hypervisor
...off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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commit | commitdiff | tree |
| 2018-02-20 |
Giacomo Travaglini | arch-arm: Make hlt64 a mem barrier with semihosting
...off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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commit | commitdiff | tree |
| 2018-02-20 |
Giacomo Travaglini | arch-arm: Add AArch32 HLT Semihosting interface
...off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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commit | commitdiff | tree |
| 2018-02-20 |
Giacomo Travaglini | arch-arm: Add AArch32 SVC Semihosting interface
...off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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commit | commitdiff | tree |
| 2018-02-20 |
Giacomo Travaglini | arch-arm: Adding isa templates for semihosting ops
...off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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commit | commitdiff | tree |
| 2018-02-20 |
Giacomo Travaglini | arch-arm: HLT using immediate when checking for semihosting
...off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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commit | commitdiff | tree |
| 2018-02-20 |
Giacomo Travaglini | arch-arm: Fix Hlt64,Svc64,Hvc64,Smc64,Brk64 disassembly
...off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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commit | commitdiff | tree |
| 2018-02-20 |
Andreas Sandberg | cpu-o3: Don't add non-speculative mem barriers to the...
|
commit | commitdiff | tree |
| 2018-02-16 |
Giacomo Travaglini | arch-arm: IMPLEMENTATION DEFINED register
...off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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commit | commitdiff | tree |
| 2018-02-16 |
Giacomo Travaglini | arch-arm: Arch regs and pseudo regs distinction
...off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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commit | commitdiff | tree |
| 2018-02-16 |
Chuan Zhu | arch-arm: Fix syntax error in TLB::getResultTe
|
commit | commitdiff | tree |
| 2018-02-16 |
Giacomo Travaglini | arch-arm: Change ArmFault cast from reinterpret to...
...off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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commit | commitdiff | tree |
| 2018-02-16 |
Chuan Zhu | arch-arm: Fix Secure state check in checkFPAdvSIMDTrap64
Reviewed-by: Jack Travaglini <giacomo.travaglini@arm.com>
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commit | commitdiff | tree |
| 2018-02-13 |
Rekai Gonzalez-Alber... | sim: Make Stats truly non-copy-constructible
|
commit | commitdiff | tree |
| 2018-02-09 |
Giacomo Travaglini | sim: Remove _numContexts member in System class
...off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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commit | commitdiff | tree |
| 2018-02-08 |
Giacomo Travaglini | arch-arm: Correct SecureMonitorTrap vals for aarch32
...off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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commit | commitdiff | tree |
| 2018-02-08 |
Chuan Zhu | arch-arm: Fixed error in choosing vector offset
Reviewed-by: Jack Travaglini <giacomo.travaglini@arm.com>
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commit | commitdiff | tree |
| 2018-02-08 |
Giacomo Travaglini | arch-arm: Don't change PSTATE in Illegal Exception...
...off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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commit | commitdiff | tree |
| 2018-02-08 |
Chuan Zhu | arch-arm: Handle route to EL2 in Supervisor Trap
Reviewed-by: Jack Travaglini <giacomo.travaglini@arm.com>
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commit | commitdiff | tree |
| 2018-02-07 |
Giacomo Travaglini | arch-arm: Change function name for banked miscregs
...off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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commit | commitdiff | tree |
| 2018-02-07 |
Giacomo Travaglini | arch-arm: Fix AArch32 SETEND Instruction
...off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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commit | commitdiff | tree |
| 2018-02-07 |
Giacomo Travaglini | arch-arm: Correct Illegal Exception Return detection
...off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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commit | commitdiff | tree |
| 2018-02-07 |
Giacomo Travaglini | arch-arm: ELUsingAArch32K from armarm pseudocode
...off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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commit | commitdiff | tree |
| 2018-02-07 |
Giacomo Travaglini | arch-arm: isSecureBelow from armarm pseudocode
...off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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commit | commitdiff | tree |
| 2018-02-07 |
Chuan Zhu | arch-arm: Fix incorrect assumptions in ELIs64
|
commit | commitdiff | tree |
| 2018-02-05 |
Giacomo Travaglini | cpu: MinorCPU handling IsSquashAfter flag
...off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
|
commit | commitdiff | tree |
| 2018-02-05 |
Giacomo Travaglini | arch-arm: Removing Serializing flag from ISB
...off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
|
commit | commitdiff | tree |
| 2017-12-21 |
Giacomo Travaglini | arch-arm: Fixed WFE/WFI trapping behaviour
...off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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commit | commitdiff | tree |
| 2017-12-21 |
Giacomo Travaglini | arch-arm: Hyp routed undef fault need to change its...
...off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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commit | commitdiff | tree |
| 2017-12-21 |
Giacomo Travaglini | arch-arm: Fix StaticInst encoding() method
...off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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commit | commitdiff | tree |
| 2017-12-19 |
Giacomo Travaglini | arch-arm: Instruction size methods in StaticInst class
...off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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commit | commitdiff | tree |
| 2017-12-19 |
Giacomo Travaglini | arch-arm: Change casting type from reinterpret to static
...off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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commit | commitdiff | tree |
| 2017-12-08 |
Giacomo Travaglini | arm: Change access permission in TPIDRURO and TPIDRURW
...off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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commit | commitdiff | tree |
| 2017-12-01 |
Giacomo Travaglini | arm: Enable ns registers access in secure mode
...off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
|
commit | commitdiff | tree |
| 2017-11-28 |
Giacomo Travaglini | arch-arm: Add haveEL pseudocode function
...off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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