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2018-09-22	Sean Cross	csr: use external csr_readl()/csr_writel() if present Signed-off-by: Sean Cross <sean@xobs.io>	commit \| commitdiff \| tree
2018-09-22	Sean Cross	csr: use readl()/writel() accessors for accessing mmio Signed-off-by: Sean Cross <sean@xobs.io>	commit \| commitdiff \| tree
2018-07-27	Sean Cross	tools: remove vexriscv_debug Signed-off-by: Sean Cross <sean@xobs.io>	commit \| commitdiff \| tree
2018-07-27	Sean Cross	vexriscv: reset wishbone bus on CPU reset Signed-off-by: Sean Cross <sean@xobs.io>	commit \| commitdiff \| tree
2018-07-27	Sean Cross	vexriscv: put debug bus directly on wishbone bus Signed-off-by: Sean Cross <sean@xobs.io>	commit \| commitdiff \| tree
2018-07-17	Sean Cross	vexriscv_debug: use csr read()/write() accessors Signed-off-by: Sean Cross <sean@xobs.io>	commit \| commitdiff \| tree
2018-07-06	Sean Cross	vexriscv: debug: fix reading DATA register Signed-off-by: Sean Cross <sean@xobs.io>	commit \| commitdiff \| tree
2018-07-06	Sean Cross	setup: add vexriscv_debug to list of entrypoints Signed-off-by: Sean Cross <sean@xobs.io>	commit \| commitdiff \| tree
2018-07-06	Sean Cross	tools: vexriscv_debug: add debug bridge Signed-off-by: Sean Cross <sean@xobs.io>	commit \| commitdiff \| tree
2018-07-05	Sean Cross	soc_core: uart: add a reset line to the UART Signed-off-by: Sean Cross <sean@xobs.io>	commit \| commitdiff \| tree
2018-07-05	Sean Cross	soc: integration: use the new cpu_debugging flag for... Signed-off-by: Sean Cross <sean@xobs.io>	commit \| commitdiff \| tree
2018-07-05	Sean Cross	soc: vexriscv: add cpu debug support Signed-off-by: Sean Cross <sean@xobs.io>	commit \| commitdiff \| tree
2018-07-05	Sean Cross	vexriscv: verilog: pull debug-enabled verilog Signed-off-by: Sean Cross <sean@xobs.io>	commit \| commitdiff \| tree
2018-06-18	Sean Cross	soc: bios: fix windows build Signed-off-by: Sean Cross <sean@xobs.io>	commit \| commitdiff \| tree

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