| 2023-05-15 |
Luke Kenneth Casson... | ld/st mismatch in power_insn.py and sv_analysis.py
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| 2023-05-15 |
Luke Kenneth Casson... | add sv.ffmadds test to test_pysvp64dis.py
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| 2023-05-15 |
Luke Kenneth Casson... | in DCT/FFT 3-in 2-out set had to make RT same source...
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| 2023-05-15 |
Luke Kenneth Casson... | move RG bit in CRops to Mode[2] from Mode[3] MSB0-numbering
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| 2023-05-15 |
Luke Kenneth Casson... | got linked-list-pointer-chasing working
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| 2023-05-15 |
Luke Kenneth Casson... | bug in power_insn.py where record.svp64 is None (??)
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| 2023-05-15 |
Luke Kenneth Casson... | have to now add LD/ST-update instructions to list of...
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| 2023-05-15 |
Luke Kenneth Casson... | prevent duplicate EXTRA2/3 in power_insndb when assembling...
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| 2023-05-14 |
Luke Kenneth Casson... | attempting to get LD/ST-Update SVP64 EXTRA3 working...
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| 2023-05-14 |
Luke Kenneth Casson... | classify LD/ST-Immediate-Update as EXTRA3.
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| 2023-05-14 |
Luke Kenneth Casson... | whitespace cleanup and remove as many PHP-style-formatters...
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| 2023-05-12 |
Luke Kenneth Casson... | check expected CR fields in Data-Dependent Fail-First
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| 2023-05-11 |
Luke Kenneth Casson... | corrections to dd-ffirst tests when VLi=0, the write...
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| 2023-05-10 |
Luke Kenneth Casson... | add very very very basic write-out of instruction log
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| 2023-05-10 |
Luke Kenneth Casson... | add ld/st data-dependent fail-first /vli (inclusive)
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| 2023-05-10 |
Luke Kenneth Casson... | fix data-dependent fail-first on load
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| 2023-05-10 |
Luke Kenneth Casson... | extend previous hard-coded magic constant (256) used...
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| 2023-05-09 |
Luke Kenneth Casson... | separate ISAPages out from inherited ISA Class
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| 2023-05-07 |
Luke Kenneth Casson... | comment TODO on Load-Fault in strncpy example
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| 2023-05-07 |
Luke Kenneth Casson... | add stub reset_xflags function
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| 2023-05-06 |
Luke Kenneth Casson... | add FPSCR to Test API (ExpectedState, SimState). untested
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| 2023-05-06 |
Luke Kenneth Casson... | add FPSCR to ISACaller
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| 2023-05-06 |
Luke Kenneth Casson... | notes: make FPSCR definition more like MSR (see openpower...
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| 2023-05-06 |
Luke Kenneth Casson... | drastically simplify fpscr.py. extreme overcomplexity...
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| 2023-05-06 |
Luke Kenneth Casson... | add comment about why the new check has been added
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| 2023-05-06 |
Luke Kenneth Casson... | get table down to under 80 chars per line
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| 2023-05-04 |
Luke Kenneth Casson... | maddsubrs no longer has CR0
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| 2023-05-02 |
Luke Kenneth Casson... | add links between decode and issue
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| 2023-05-02 |
Luke Kenneth Casson... | reserve writes in Issue Phase, add comment
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| 2023-05-02 |
Luke Kenneth Casson... | add Issue phase and writes/reads possible in CPU
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commit | commitdiff | tree |
| 2023-05-02 |
Luke Kenneth Casson... | add Decode and CPU classes
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| 2023-05-02 |
Luke Kenneth Casson... | add quick preamble header
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| 2023-05-02 |
Luke Kenneth Casson... | update comments and correct retiring, remove registers...
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| 2023-05-02 |
Luke Kenneth Casson... | start on cycle-accurate model of inorder core
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| 2023-04-30 |
Luke Kenneth Casson... | ffnmadds converted to 3-operand
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commit | commitdiff | tree |
| 2023-04-30 |
Luke Kenneth Casson... | converted ffnmadds to 3-operand
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| 2023-04-30 |
Luke Kenneth Casson... | ffmsubs number of operands reduced to match ffmadds
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commit | commitdiff | tree |
| 2023-04-28 |
Luke Kenneth Casson... | reduce number of operands to ffmadds as well
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commit | commitdiff | tree |
| 2023-04-28 |
Luke Kenneth Casson... | reduce fdmadds down to only 3 operands, RT-overwrite...
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| 2023-04-27 |
Luke Kenneth Casson... | add SVSHAPE setup for parallel/prefix but it refuses...
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| 2023-04-27 |
Luke Kenneth Casson... | add implicit rs detection for maddsubrs
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| 2023-04-27 |
Luke Kenneth Casson... | link in new parallel-prefix REMAP schedule
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commit | commitdiff | tree |
| 2023-04-25 |
Luke Kenneth Casson... | add CW and CW2 Form
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| 2023-04-25 |
Luke Kenneth Casson... | check RC1, add data-dependent fail-first LD/ST test
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| 2023-04-06 |
Luke Kenneth Casson... | add power_decode_svp64_rm.py capability for new LD...
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| 2023-04-04 |
Luke Kenneth Casson... | add quick test_pysvp64dis.py of LD/ST data-dependent...
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| 2023-04-04 |
Luke Kenneth Casson... | https://bugs.libre-soc.org/show_bug.cgi?id=1047
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| 2023-04-04 |
Luke Kenneth Casson... | whitespace cleanup (80 char per line hard limit)
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| 2023-04-04 |
Luke Kenneth Casson... | comment about massive unnecessary code-duplication...
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| 2023-04-04 |
Luke Kenneth Casson... | fix setvl unit test which happened to use deprecated
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commit | commitdiff | tree |
| 2023-03-29 |
Luke Kenneth Casson... | remove DCT/iDCT redundant modes which require less...
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commit | commitdiff | tree |
| 2023-03-25 |
Luke Kenneth Casson... | all whitespace. reduce to under 80 chars
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| 2023-03-25 |
Luke Kenneth Casson... | update comments on svstep returning pack/unpack state
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| 2023-03-25 |
Luke Kenneth Casson... | whitespace - 80 char limit
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| 2023-03-25 |
Luke Kenneth Casson... | in xchacha20 svp64 assembler remove r22 from setvl and
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| 2023-03-25 |
Luke Kenneth Casson... | updated simplev setvl specification pseudocode: MAJOR...
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commit | commitdiff | tree |
| 2023-03-25 |
Luke Kenneth Casson... | whitespace
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commit | commitdiff | tree |
| 2023-03-24 |
Luke Kenneth Casson... | whoops added "CRB-Form" format not "CRB"
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commit | commitdiff | tree |
| 2023-03-18 |
Luke Kenneth Casson... | brief explanation of Vertical-First
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commit | commitdiff | tree |
| 2023-03-18 |
Luke Kenneth Casson... | spelling
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commit | commitdiff | tree |
| 2023-03-18 |
Luke Kenneth Casson... | whitespace cleanup
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commit | commitdiff | tree |
| 2023-03-15 |
Luke Kenneth Casson... | add CRB-Form fields for crternlogi and crbinlog, they...
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| 2023-03-12 |
Luke Kenneth Casson... | set MAXVL=VL=32 first, then set vertical-first separately
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| 2023-03-12 |
Luke Kenneth Casson... | change target registers in test_caller_svp64_chacha20...
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| 2023-03-12 |
Luke Kenneth Casson... | whoops use same temp reg for ctr
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commit | commitdiff | tree |
| 2023-03-12 |
Luke Kenneth Casson... | parameterise svstep RT (set to 16 in chacha20 test)
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commit | commitdiff | tree |
| 2023-03-12 |
Luke Kenneth Casson... | parameterising VL and SHAPE0-2 in chacha20 test
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commit | commitdiff | tree |
| 2023-03-12 |
Luke Kenneth Casson... | parameterise the target block in chacha20 test,
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commit | commitdiff | tree |
| 2023-03-12 |
Luke Kenneth Casson... | add print-out for chacha20 schedule
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commit | commitdiff | tree |
| 2023-03-08 |
Luke Kenneth Casson... | update pseudocode for dsld/dsrd to note that only when...
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| 2023-02-20 |
Luke Kenneth Casson... | after move data to new directory, update runner-script...
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commit | commitdiff | tree |
| 2023-01-01 |
Luke Kenneth Casson... | correct name for Mem test function
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commit | commitdiff | tree |
| 2023-01-01 |
Luke Kenneth Casson... | gaah a mess (but working)
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commit | commitdiff | tree |
| 2023-01-01 |
Luke Kenneth Casson... | use qemu user-mode to run cross-compiled xchacha20
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commit | commitdiff | tree |
| 2023-01-01 |
Luke Kenneth Casson... | ascii dump on xchacha20 to compare against x86 version
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commit | commitdiff | tree |
| 2023-01-01 |
Luke Kenneth Casson... | add -mno-altivec option to xchacha20 test
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commit | commitdiff | tree |
| 2023-01-01 |
Luke Kenneth Casson... | enable misaligned Mem in ISACaller by default
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commit | commitdiff | tree |
| 2022-12-30 |
Luke Kenneth Casson... | corrections to boundary-wrapped store, and add misaligned...
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commit | commitdiff | tree |
| 2022-12-30 |
Luke Kenneth Casson... | add rollover mem test, store "rolls over" a 64-bit...
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commit | commitdiff | tree |
| 2022-12-30 |
Luke Kenneth Casson... | add misaligned mem test
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commit | commitdiff | tree |
| 2022-12-30 |
Luke Kenneth Casson... | add misaligned mem test
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commit | commitdiff | tree |
| 2022-12-30 |
Luke Kenneth Casson... | relocate main() to a single section
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commit | commitdiff | tree |
| 2022-12-30 |
Luke Kenneth Casson... | add unit test for Mem class, need to add misaligned...
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commit | commitdiff | tree |
| 2022-12-29 |
Luke Kenneth Casson... | print out memory exception details, on unaligned
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commit | commitdiff | tree |
| 2022-12-29 |
Luke Kenneth Casson... | add .gitignore
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commit | commitdiff | tree |
| 2022-12-29 |
Luke Kenneth Casson... | add cross-compiled test of xchacha20 suitable for running...
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commit | commitdiff | tree |
| 2022-12-29 |
Luke Kenneth Casson... | simplify by running smallest test
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| 2022-12-29 |
Luke Kenneth Casson... | get video pypowersim_wrapper running
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| 2022-12-29 |
Luke Kenneth Casson... | add bryan hawkins chacha20 source from
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commit | commitdiff | tree |
| 2022-11-01 |
Luke Kenneth Casson... | corrections to shadd/uw after reverting to switch
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| 2022-11-01 |
Luke Kenneth Casson... | Revert "https://bugs.libre-soc.org/show_bug.cgi?id...
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| 2022-10-29 |
Luke Kenneth Casson... | add dsld. (Rc=1) test, make overflow acceptable to...
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| 2022-10-28 |
Luke Kenneth Casson... | dsld: MASK(0, 63-n) works just as well as MASK(64,...
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| 2022-10-28 |
Luke Kenneth Casson... | overflow condition in dsld and dsrd if RS is non-zero
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commit | commitdiff | tree |
| 2022-10-28 |
Luke Kenneth Casson... | fix dsrd pseudocode to use ROTL64 not ROTL128
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commit | commitdiff | tree |
| 2022-10-28 |
Luke Kenneth Casson... | fix dsld pseudocode to use ROTL64 instead of ROTL128
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| 2022-10-28 |
Luke Kenneth Casson... | add test showing that dsld and dsrd are not quite inverses
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commit | commitdiff | tree |
| 2022-10-28 |
Jacob Lifshay | fix bigint shift tests
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commit | commitdiff | tree |
| 2022-10-28 |
Luke Kenneth Casson... | fix dsrd, ROTL128 use 128-n not 64-n,
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| 2022-10-28 |
Luke Kenneth Casson... | redo sv_analysis for dsld/dsrd
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