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Fix URL for liteUSB
2018-07-27 Sean Crosstools: remove vexriscv_debug
Signed-off-by: Sean Cross <sean@xobs.io>
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2018-07-27 Sean Crossvexriscv: reset wishbone bus on CPU reset
Signed-off-by: Sean Cross <sean@xobs.io>
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2018-07-27 Sean Crossvexriscv: put debug bus directly on wishbone bus
Signed-off-by: Sean Cross <sean@xobs.io>
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2018-07-17 Sean Crossvexriscv_debug: use csr read()/write() accessors
Signed-off-by: Sean Cross <sean@xobs.io>
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2018-07-06 Sean Crossvexriscv: debug: fix reading DATA register
Signed-off-by: Sean Cross <sean@xobs.io>
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2018-07-06 Sean Crosssetup: add vexriscv_debug to list of entrypoints
Signed-off-by: Sean Cross <sean@xobs.io>
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2018-07-06 Sean Crosstools: vexriscv_debug: add debug bridge
Signed-off-by: Sean Cross <sean@xobs.io>
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2018-07-05 Sean Crosssoc_core: uart: add a reset line to the UART
Signed-off-by: Sean Cross <sean@xobs.io>
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2018-07-05 Sean Crosssoc: integration: use the new cpu_debugging flag for...
Signed-off-by: Sean Cross <sean@xobs.io>
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2018-07-05 Sean Crosssoc: vexriscv: add cpu debug support
Signed-off-by: Sean Cross <sean@xobs.io>
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2018-07-05 Sean Crossvexriscv: verilog: pull debug-enabled verilog
Signed-off-by: Sean Cross <sean@xobs.io>
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2018-06-18 Sean Crosssoc: bios: fix windows build
Signed-off-by: Sean Cross <sean@xobs.io>
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