2022-02-22 |
Luke Kenneth Casson... | xdr=4 missing on ddr3 platform request for VERSA_ECP5
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2022-02-21 |
Luke Kenneth Casson... | lengthen cdelay pauses by a factor of 10
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2022-02-21 |
Luke Kenneth Casson... | * use readl and writel for accessing memory
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2022-02-21 |
Luke Kenneth Casson... | use microwatt mmu powerpc.lds with better stack space
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2022-02-20 |
Luke Kenneth Casson... | fix dfi initialisation and calibration to use
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2022-02-20 |
Luke Kenneth Casson... | set RAM base to #defined DRAM_BASE not hard-coded value
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2022-02-20 |
Luke Kenneth Casson... | for simulatio keep the simulated dram in the
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2022-02-20 |
Luke Kenneth Casson... | add fake (sim) DRAM from gram library
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2022-02-19 |
Luke Kenneth Casson... | match up dram initialisation parameters
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2022-02-19 |
Luke Kenneth Casson... | put together coldboot startup firmware
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2022-02-19 |
Luke Kenneth Casson... | hm -abc9 seems to be working, and without -nowidelut
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2022-02-18 |
Luke Kenneth Casson... | add DRAM class to DDR3Soc
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2022-02-18 |
Luke Kenneth Casson... | add FPGA argument to DDR3SoC
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2022-02-18 |
Luke Kenneth Casson... | add microwatt console lib and #includes
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2022-02-18 |
Luke Kenneth Casson... | make cpu optional (test purposes), make bios optional,
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2022-02-16 |
Luke Kenneth Casson... | remove minerva cpu
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2022-02-16 |
Luke Kenneth Casson... | drop clock frequency to 25 mhz and disable abc9 (it...
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2022-02-16 |
Luke Kenneth Casson... | add openocd load command for ecp5
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2022-02-16 |
Luke Kenneth Casson... | wildcards never ok. update comments
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2022-02-16 |
Luke Kenneth Casson... | add copyright notices
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2022-02-16 |
Luke Kenneth Casson... | update ECP5 PLL to accept parameters for setting arbitrary...
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2022-02-16 |
Luke Kenneth Casson... | add start of README as reminder
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2022-02-16 |
Luke Kenneth Casson... | * add uart_pins to UART16550 peripheral so they get...
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2022-02-16 |
Luke Kenneth Casson... | * disable DDR3 for now
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2022-02-15 |
Luke Kenneth Casson... | connect up stall signals (fake) for WB Classic compliance
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2022-02-15 |
Luke Kenneth Casson... | alternative uart wishbone mapping which just takes...
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2022-02-15 |
Luke Kenneth Casson... | attempt to do 8-bit downconvert on wishbone bus for...
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2022-02-15 |
Luke Kenneth Casson... | correct syscon bus address to 0xC000_0000
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2022-02-15 |
Luke Kenneth Casson... | add microwatt SYSCON peripheral at 0xc000_0000
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2022-02-15 |
Luke Kenneth Casson... | increase size of bootmem
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2022-02-15 |
Luke Kenneth Casson... | add interrupt controller module, remove stall feature...
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2022-02-15 |
Luke Kenneth Casson... | FLGA_TARGET=verilator not uppercase
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2022-02-14 |
Luke Kenneth Casson... | add external cpu
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2022-02-14 |
Luke Kenneth Casson... | convert boot rom to bootmem and get first hello_world...
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2022-02-14 |
Luke Kenneth Casson... | add IBM microwatt CC4 license and copyright notices
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2022-02-14 |
Luke Kenneth Casson... | add first cut of verilator simulation, over from microwatt
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2022-02-14 |
Luke Kenneth Casson... | add verilog build option, make DDR3 PHY optional, add...
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2022-02-13 |
Luke Kenneth Casson... | add future sim option (needs Simulated DDR PHY)
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2022-02-13 |
Luke Kenneth Casson... | add build to gitignore
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2022-02-13 |
Luke Kenneth Casson... | rename examples to src
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2022-02-13 |
Luke Kenneth Casson... | not for any good reason, separate adding the uart16550...
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2022-02-13 |
Luke Kenneth Casson... | add MemoryMap to UART16550 (TODO, put that into UART16550...
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2022-02-13 |
Luke Kenneth Casson... | start adding uart16550
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2022-02-13 |
Luke Kenneth Casson... | select a firmware file
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2022-02-13 |
Luke Kenneth Casson... | allow selection of alternative FPGAs at commandline
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2022-02-13 |
Luke Kenneth Casson... | add blinky lights so we know FPGA is alive
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2022-02-13 |
Luke Kenneth Casson... | make firmware and cpu optional for now to get a basic...
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2022-02-12 |
Luke Kenneth Casson... | begin a tidyup on the example
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2022-02-10 |
Luke Kenneth Casson... | resolve imports, whitespace, add Copyright
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2022-02-10 |
Luke Kenneth Casson... | add crg.py
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2022-02-10 |
Luke Kenneth Casson... | update contributors
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2022-02-10 |
Luke Kenneth Casson... | sort out license and headers for NLnet and NGI POINTER...
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2022-02-10 |
Luke Kenneth Casson... | add gram soc example and license and contributors
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2022-02-09 |
Luke Kenneth Casson... | empty first commit
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