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Give human-readable names to slots, run functions and filenames
2021-12-10
Jacob Lifshay
add ternlogi to SVP64Asm
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2021-12-10
Jacob Lifshay
format code
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2021-12-10
Jacob Lifshay
change ternlogi to not have Rc field
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2021-12-10
Jacob Lifshay
add .gitignore to ignore the generated vhdl
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2021-12-09
Jacob Lifshay
make ternlogi tests run
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2021-12-09
Jacob Lifshay
rename ternaryi to ternlogi
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2021-12-09
Jacob Lifshay
add initial ternlogi pseudo-code
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2021-12-07
Jacob Lifshay
fix broken url
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2021-12-02
Jacob Lifshay
move ternlogi to SHIFT_ROT unit
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2021-12-02
Jacob Lifshay
fix sv_analysis command, cuz script created by setup...
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2021-12-02
Jacob Lifshay
format code
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2021-11-17
Jacob Lifshay
add bitmanip_cases.py
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2021-11-17
Jacob Lifshay
rename ternary->ternlog and associated form/field TI...
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2021-11-13
Jacob Lifshay
remove excess I from ternary-related names
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2021-11-12
Jacob Lifshay
change ternaryi to correct register fields
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2021-11-12
Jacob Lifshay
format code
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2021-11-12
Jacob Lifshay
format code
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2021-11-05
Jacob Lifshay
add ternaryi
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2021-11-05
Jacob Lifshay
format code
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2021-11-05
Jacob Lifshay
format code
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2021-11-05
Jacob Lifshay
add comment2 and unofficial fields to existing instructions
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2021-09-17
Jacob Lifshay
add mock power-instruction-analyzer implementation...
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2021-09-17
Jacob Lifshay
fix test_caller_bcd_full.py not actually running correct...
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2021-09-17
Jacob Lifshay
add test_caller_bcd_full.py to fully test all edge...
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2021-09-07
Jacob Lifshay
XLEN-ify bcd instructions
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2021-09-07
Jacob Lifshay
clean up test_caller_bcd.py
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2021-09-07
Jacob Lifshay
add missing items to .gitignore
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2021-04-30
Jacob Lifshay
fix executable names
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