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Improve the invalid CPU type error message.
2019-12-30
Tim 'mithro' Ansell
Improve the invalid CPU type error message.
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2019-10-31
Tim 'mithro' Ansell
Improve the error message on memory region conflict.
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2019-10-30
Tim 'mithro' Ansell
Fix file names for the mor1kx processor.
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2019-09-02
Tim 'mithro' Ansell
Use `SMALL_CRC` to enable smaller CRC versions.
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2019-09-02
Tim 'mithro' Ansell
Remove extra whitespace.
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2019-09-02
Sean Cross
libbase: crc16: commit smaller version of crc16
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2019-09-02
Sean Cross
libbase: crc32: add smaller version
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2019-09-02
Tim 'mithro' Ansell
Only write file if contents will change.
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2019-06-21
Tim 'mithro' Ansell
Convert top level comment to a docstring.
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2019-04-26
Tim 'mithro' Ansell
Adding testing of cpu variants.
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2019-04-26
Tim 'mithro' Ansell
Work with no `cpu_variant` provided.
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2019-04-26
Tim 'mithro' Ansell
Updating documents from LiteX BuildEnv Wiki
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2019-04-26
Tim 'mithro' Ansell
Updating documents from LiteX BuildEnv Wiki
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2019-04-26
Tim 'mithro' Ansell
Standardize the `cpu_variant` strings.
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2019-04-26
Tim 'mithro' Ansell
docs: Adding script to pull useful docs from LiteX...
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2018-12-20
Tim 'mithro' Ansell
Integrate latest migen changes for lattice/icestorm.
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2018-12-18
Tim 'mithro' Ansell
Fix `-vlgincdir` for xst.
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2018-12-16
Tim 'mithro' Ansell
Hack to fix #136.
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2018-12-16
Tim 'mithro' Ansell
Add uwg30 package and up3k part.
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2018-11-25
Tim 'mithro' Ansell
stream.Endpoint: Pass extra arguments to superclass.
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2018-11-25
Tim 'mithro' Ansell
wishbone.SRAM: Support non-32bit wishbone widths.
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2018-11-14
Tim 'mithro' Ansell
lattice/icestorm: Add toolchain_path so it doesn't...
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2018-10-29
Tim 'mithro' Ansell
litex/build: Always run Vivado.
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2018-10-27
Tim 'mithro' Ansell
uart: Enable buffering the FIFO.
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2018-10-05
Tim 'mithro' Ansell
build.xilinx: Convert attributes to something Yosys...
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2018-10-04
Tim 'mithro' Ansell
xilinx/viviado: Allow yosys for synthesis.
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2018-10-04
Tim 'mithro' Ansell
cpu/mor1kx: Adding verilog include directory.
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2018-10-03
Tim 'mithro' Ansell
build.xilinx: Run `phys_opt_design` and generate timing...
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2018-03-04
Tim 'mithro' Ansell
travis: Adding some color.
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2018-03-04
Tim 'mithro' Ansell
travis: Move the conda install into script so it can...
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2018-03-04
Tim 'mithro' Ansell
travis: Making the output more readable.
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2018-03-04
Tim 'mithro' Ansell
travis: Build all the SoCs (without gateware).
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2018-03-04
Tim 'mithro' Ansell
Adding a travis config which tests the conda environment...
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2018-03-04
Tim 'mithro' Ansell
Adding conda environment example.
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2018-03-04
Tim 'mithro' Ansell
Improving error message when csr name is not found.
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2018-01-18
Tim 'mithro' Ansell
Support forcing colorama colors on.
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2018-01-13
Tim 'mithro' Ansell
soc_core: Don't fail if name is the same.
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2018-01-13
Tim 'mithro' Ansell
cpu_interface: Fix indenting on constant generation.
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2017-12-30
Tim 'mithro' Ansell
cpu: Adding "variant" support.
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2017-12-29
Greg Darke
Wait longer before giving up on the 2nd tftp block.
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