| 2021-06-25 |
Luke Kenneth Casson... | rename svp64 bit-reversed LD instructions to not conflict...
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| 2021-06-24 |
Luke Kenneth Casson... | whoops SVP64 bit-rev LDs need to use SVD and SVDS immediate...
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| 2021-06-24 |
Luke Kenneth Casson... | allow default decoder to be created with no col/row...
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| 2021-06-24 |
Luke Kenneth Casson... | add in Power Decoder conditions to select SVP64 bit...
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commit | commitdiff | tree |
| 2021-06-24 |
Luke Kenneth Casson... | add "conditions" for PowerDecoder, basic test
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commit | commitdiff | tree |
| 2021-06-24 |
Luke Kenneth Casson... | remove svp64 ld/st decoder tree
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commit | commitdiff | tree |
| 2021-06-24 |
Luke Kenneth Casson... | must pass in conditions into Sub-decoders
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| 2021-06-24 |
Luke Kenneth Casson... | search for CSV "Conditions", set to static (disabled...
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| 2021-06-24 |
Luke Kenneth Casson... | add major.csv LD operations with SVP64BREV condition
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| 2021-06-24 |
Luke Kenneth Casson... | add PowerDecoder condition switches (untested, doesnt...
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commit | commitdiff | tree |
| 2021-06-24 |
Luke Kenneth Casson... | was going to set 2nd decoder up through MUX but now...
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commit | commitdiff | tree |
| 2021-06-24 |
Luke Kenneth Casson... | add extra CONDITION column to CSVs
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commit | commitdiff | tree |
| 2021-06-24 |
Luke Kenneth Casson... | whoops fix rounding error in mapreduce unit test
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commit | commitdiff | tree |
| 2021-06-24 |
Luke Kenneth Casson... | only add svdecldst in PowerDecoder2 or LDST PowerDecodeSubset
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commit | commitdiff | tree |
| 2021-06-24 |
Luke Kenneth Casson... | use PowerOp copy of PowerDecodeSubset in get_op
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commit | commitdiff | tree |
| 2021-06-24 |
Luke Kenneth Casson... | add "user_svp64_ldst_dec" flag to PowerDecodeSubset
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commit | commitdiff | tree |
| 2021-06-24 |
Luke Kenneth Casson... | use new PowerOp.like function in PowerDecoder, fix...
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| 2021-06-24 |
Luke Kenneth Casson... | use get_op on "internal_op" instead of self.dec.op...
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commit | commitdiff | tree |
| 2021-06-24 |
Luke Kenneth Casson... | do shorter-path detection of SVP64 LD/ST bitreverse...
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commit | commitdiff | tree |
| 2021-06-24 |
Luke Kenneth Casson... | tidy up PowerOp and rename svp64 ldst decoder creater
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commit | commitdiff | tree |
| 2021-06-24 |
Luke Kenneth Casson... | add comment about perfcounters
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| 2021-06-23 |
Luke Kenneth Casson... | get op always using function PowerDecoder.op_get
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commit | commitdiff | tree |
| 2021-06-23 |
Luke Kenneth Casson... | add PowerOp.like function to be able to duplicate a...
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commit | commitdiff | tree |
| 2021-06-23 |
Luke Kenneth Casson... | add SVP64 alternative LDST decoder (unused so far)
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commit | commitdiff | tree |
| 2021-06-23 |
Luke Kenneth Casson... | only add SVP64 bitreverse mode for LDs at the moment...
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| 2021-06-23 |
Luke Kenneth Casson... | add SVP64 LD/ST "bitrev" alternative CSV
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| 2021-06-23 |
Luke Kenneth Casson... | add sv bitrev "major" CSV table
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commit | commitdiff | tree |
| 2021-06-23 |
Luke Kenneth Casson... | add start of bit-reverse mode for LD/ST to SVP64 encode...
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commit | commitdiff | tree |
| 2021-06-23 |
Luke Kenneth Casson... | looks like spec error on maddhd etc. should be a comma...
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commit | commitdiff | tree |
| 2021-06-23 |
Luke Kenneth Casson... | add mul-add to list of instructions
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| 2021-06-23 |
Luke Kenneth Casson... | add ASCII art example to int predicated SVP64
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| 2021-06-23 |
Luke Kenneth Casson... | add VL and srcstep to ISACaller namespace
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| 2021-06-23 |
Luke Kenneth Casson... | add SHL64 helper function
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| 2021-06-23 |
Luke Kenneth Casson... | add bitrev to pywriter autogenerator
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commit | commitdiff | tree |
| 2021-06-23 |
Luke Kenneth Casson... | add bitrev function to be used in LD-ST-bitrev FFT/DCT
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| 2021-06-23 |
Luke Kenneth Casson... | better ways to do sign-inversion (without multiply...
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commit | commitdiff | tree |
| 2021-06-23 |
Luke Kenneth Casson... | add sign-inversion argument to FPMUL/DIV helpers
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commit | commitdiff | tree |
| 2021-06-23 |
Luke Kenneth Casson... | add comments for SVP64 FP FFT/DCT
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commit | commitdiff | tree |
| 2021-06-23 |
Luke Kenneth Casson... | add FFT/DCT to titles
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commit | commitdiff | tree |
| 2021-06-23 |
Luke Kenneth Casson... | add SV FP arithmetic in "Overflow" mode for FFT/DCT +/-
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commit | commitdiff | tree |
| 2021-06-23 |
Luke Kenneth Casson... | use SHL64 function for shift because "<<" operator...
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commit | commitdiff | tree |
| 2021-06-23 |
Luke Kenneth Casson... | add in bitreverse function call into svfixedload
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commit | commitdiff | tree |
| 2021-06-23 |
Luke Kenneth Casson... | add RC and SVD/SVDS-Form to svfixedload
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commit | commitdiff | tree |
| 2021-06-23 |
Luke Kenneth Casson... | add svfixedload.mdwn at correct place
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commit | commitdiff | tree |
| 2021-06-23 |
Luke Kenneth Casson... | add SVD-Form and SVDS-Form, variants of fixedload for...
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commit | commitdiff | tree |
| 2021-06-19 |
Luke Kenneth Casson... | 128 regs added to simulator - works
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commit | commitdiff | tree |
| 2021-06-19 |
Luke Kenneth Casson... | sigh cannot add comments at end of SV lines in SVP64...
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commit | commitdiff | tree |
| 2021-06-19 |
Luke Kenneth Casson... | increase number of registers to 128 in pypowersim
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commit | commitdiff | tree |
| 2021-06-19 |
Luke Kenneth Casson... | set regfile in ISACaller equal to length of initial...
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commit | commitdiff | tree |
| 2021-06-19 |
Luke Kenneth Casson... | add mapreduce "reverse gear" unit tests
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commit | commitdiff | tree |
| 2021-06-19 |
Luke Kenneth Casson... | add mapreduce "reverse gear" to PowerDecoder2. gets...
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commit | commitdiff | tree |
| 2021-06-19 |
Luke Kenneth Casson... | add decode of "reverse gear" in SVP64 reduce mode
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commit | commitdiff | tree |
| 2021-06-19 |
Luke Kenneth Casson... | add "reverse-gear" mode to mapreduce in SVP64
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commit | commitdiff | tree |
| 2021-06-18 |
Luke Kenneth Casson... | add SV Context SPRs (SVCTX0-7)
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commit | commitdiff | tree |
| 2021-06-18 |
Luke Kenneth Casson... | add SVR-Form and associated fields
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commit | commitdiff | tree |
| 2021-06-18 |
Luke Kenneth Casson... | add four SVSHAPE SPRs for REMAP
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commit | commitdiff | tree |
| 2021-06-17 |
Luke Kenneth Casson... | add SV "Context Propagation" Form
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commit | commitdiff | tree |
| 2021-06-17 |
Luke Kenneth Casson... | add SVP64REMAP Record
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commit | commitdiff | tree |
| 2021-06-17 |
Luke Kenneth Casson... | shuffle comments
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commit | commitdiff | tree |
| 2021-06-17 |
Luke Kenneth Casson... | fix MP3 CODEC basic demo by using fmuls and fadds/fsubs...
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commit | commitdiff | tree |
| 2021-06-16 |
Luke Kenneth Casson... | sorted out order of FPMULADD32 helper, only have rounding...
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commit | commitdiff | tree |
| 2021-06-16 |
Luke Kenneth Casson... | add extra comments to mp3 svp64 codec assembler
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commit | commitdiff | tree |
| 2021-06-16 |
Luke Kenneth Casson... | fix fmadds/fmsubs FPMULADD32 helper
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commit | commitdiff | tree |
| 2021-06-16 |
Luke Kenneth Casson... | more code-comments in mp3 codec svp64 example
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commit | commitdiff | tree |
| 2021-06-16 |
Luke Kenneth Casson... | although unused read first sum from *dither_state
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commit | commitdiff | tree |
| 2021-06-16 |
Luke Kenneth Casson... | use addi where sv.addi is inappropriate (scalar values)
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commit | commitdiff | tree |
| 2021-06-16 |
Luke Kenneth Casson... | reorder arguments to FPMULADD32 to match pseudocode
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commit | commitdiff | tree |
| 2021-06-16 |
Luke Kenneth Casson... | use fnmsubs instead of fmadds followed by fsubs
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commit | commitdiff | tree |
| 2021-06-16 |
Luke Kenneth Casson... | fnmadds and fnmsubs were inverted
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commit | commitdiff | tree |
| 2021-06-16 |
Luke Kenneth Casson... | ad fnmadd and fnmsubs to ISA pseudocode
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commit | commitdiff | tree |
| 2021-06-16 |
Luke Kenneth Casson... | reverting removal of tmpsum and tmpsum2, not using...
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commit | commitdiff | tree |
| 2021-06-15 |
Luke Kenneth Casson... | whoops forgot import
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commit | commitdiff | tree |
| 2021-06-15 |
Luke Kenneth Casson... | whoops still using DOUBLE(SINGLE(x)) rather than DOUBLE2SINGLE
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commit | commitdiff | tree |
| 2021-06-15 |
Luke Kenneth Casson... | remove predicate mask r30, no longer needed
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commit | commitdiff | tree |
| 2021-06-15 |
Luke Kenneth Casson... | no need for tmpsu or tmpsum2, fmadds if replaced with...
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commit | commitdiff | tree |
| 2021-06-15 |
Luke Kenneth Casson... | use new sv.fmadds SVP64 instruction in MP3 CODEC assembler
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commit | commitdiff | tree |
| 2021-06-15 |
Luke Kenneth Casson... | fix sv_analysis.py for 3R-1W-CRo case, add fmadds/fmsubs...
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commit | commitdiff | tree |
| 2021-06-15 |
Luke Kenneth Casson... | mark as possible bug, the fneg sum,sum
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commit | commitdiff | tree |
| 2021-06-15 |
Luke Kenneth Casson... | add fmadds and fmsubs to Power ISA pseudo-code, add...
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commit | commitdiff | tree |
| 2021-06-15 |
Luke Kenneth Casson... | remove negate of sum for last value in SVP64 MP3 CODEC...
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commit | commitdiff | tree |
| 2021-06-15 |
Luke Kenneth Casson... | SVP64 mp3 assembler almost correct
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commit | commitdiff | tree |
| 2021-06-15 |
Luke Kenneth Casson... | add comments into mapreduce example
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commit | commitdiff | tree |
| 2021-06-15 |
Luke Kenneth Casson... | whoops overlap of fv0-2 with sum/2/tmp, move further up
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commit | commitdiff | tree |
| 2021-06-14 |
Luke Kenneth Casson... | sigh bug in setvl, temporarily setting to 7 not 8
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commit | commitdiff | tree |
| 2021-06-14 |
Luke Kenneth Casson... | nope, win = win2 + 31
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commit | commitdiff | tree |
| 2021-06-14 |
Luke Kenneth Casson... | guessing probably supposed to be 128 not 124
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commit | commitdiff | tree |
| 2021-06-14 |
Luke Kenneth Casson... | tmpsum2 probably needed to be fp3
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commit | commitdiff | tree |
| 2021-06-14 |
Luke Kenneth Casson... | temporary move regs into range 0-31
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commit | commitdiff | tree |
| 2021-06-14 |
Luke Kenneth Casson... | recognise setvl instruction during SVP64 translation
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commit | commitdiff | tree |
| 2021-06-14 |
Luke Kenneth Casson... | whoops forgot format-to-format conversion
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commit | commitdiff | tree |
| 2021-06-14 |
Luke Kenneth Casson... | series of text macro formats to look for: x.v, x.s (x)
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commit | commitdiff | tree |
| 2021-06-14 |
Luke Kenneth Casson... | add basic "macro" (.set) support to SVP64Asm
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commit | commitdiff | tree |
| 2021-06-09 |
Luke Kenneth Casson... | add some more comments in the mapreduce svp64 examples...
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commit | commitdiff | tree |
| 2021-06-09 |
Luke Kenneth Casson... | add sv.fmuls/mr - mapreduce - FP multiply-single test
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commit | commitdiff | tree |
| 2021-06-09 |
Luke Kenneth Casson... | add first scalar mapreduce SVP64 example
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commit | commitdiff | tree |
| 2021-06-09 |
Luke Kenneth Casson... | add what might turn out to be only what is needed to...
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commit | commitdiff | tree |
| 2021-06-08 |
Luke Kenneth Casson... | whoops, carry-over during rounding picks MSB not LSB
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commit | commitdiff | tree |
| 2021-06-08 |
Luke Kenneth Casson... | whoops copy sign over on zero
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commit | commitdiff | tree |
| 2021-06-08 |
Luke Kenneth Casson... | exponent bitwidth in DOUBLE2SINGLE needs to be 11 bits...
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commit | commitdiff | tree |
| 2021-06-08 |
Luke Kenneth Casson... | use new auto-generated DOUBLE2SINGLE from isafunctions...
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