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bios: add litesdcard test routines to boot menu
2020-02-20 Gabriel Somlobios: add litesdcard test routines to boot menu
Signed-off-by: Gabriel Somlo <gsomlo@gmail.com>
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2020-02-20 Gabriel Somlotargets/nexys4ddr: add ethernet via method instead...
Signed-off-by: Gabriel Somlo <gsomlo@gmail.com>
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2020-01-29 Gabriel Somlosoftware, integration/export: (re-)expose CSR subregister...
Signed-off-by: Gabriel Somlo <gsomlo@gmail.com>
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2020-01-13 Gabriel Somlobios/sdram: switch to updated CSR accessors, and misc...
Signed-off-by: Gabriel Somlo <gsomlo@gmail.com>
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2020-01-13 Gabriel Somlosoftware, integration/export: rename and reimplement...
Signed-off-by: Gabriel Somlo <gsomlo@gmail.com>
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2020-01-03 Gabriel Somlointerconnect/csr_bus/SRAM: allow 64-bit alignment ...
Signed-off-by: Gabriel Somlo <gsomlo@gmail.com>
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2019-12-21 Gabriel Somlocpu/rocket: variants with double (128b) and quad (256b...
Signed-off-by: Gabriel Somlo <gsomlo@gmail.com>
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2019-12-21 Gabriel Somlosoc_core: csr_alignment assertions
Signed-off-by: Gabriel Somlo <gsomlo@gmail.com>
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2019-12-21 Gabriel Somlocpu/rocket: access PLIC registers via pointer dereference
Signed-off-by: Gabriel Somlo <gsomlo@gmail.com>
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2019-12-12 Gabriel Somlosoc_core: additional CSR safety assertions
Signed-off-by: Gabriel Somlo <gsomlo@gmail.com>
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2019-11-18 Gabriel Somlosoc_sdram, bios/sdram: support sdram init for csr_data_width...
Signed-off-by: Gabriel Somlo <gsomlo@gmail.com>
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2019-11-01 Gabriel Somlocpu/rocket: parameterize axi interface data width
Signed-off-by: Gabriel Somlo <gsomlo@gmail.com>
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2019-11-01 Gabriel Somlosoc_sdram: remove upper limit on usable main RAM
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2019-11-01 Gabriel Somlocpu/rocket, soc_sdram: Connect mem_axi to LiteDRAM...
Signed-off-by: Gabriel Somlo <gsomlo@gmail.com>
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2019-10-24 Gabriel Somlobuild/lattice/trellis: optionally allow failure if...
Signed-off-by: Gabriel Somlo <gsomlo@gmail.com>
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2019-10-09 Gabriel Somlocpu/rocket: swap main_mem and io regions
Signed-off-by: Gabriel Somlo <gsomlo@gmail.com>
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2019-10-08 Gabriel Somlobuilder: use the SoC's existing shadow base with get_csr_hea...
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2019-10-06 Gabriel L. Somlotrellis, versa_ecp5: optional '-nowidelut' flag for...
Signed-off-by: Gabriel Somlo <gsomlo@gmail.com>
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2019-10-01 Gabriel Somlosoc/integration: ensure CSR constants are in uppercase
Signed-off-by: Gabriel Somlo <gsomlo@gmail.com>
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2019-08-23 Gabriel L. Somlosoftware: use native toolchain for same host, target...
Signed-off-by: Gabriel Somlo <gsomlo@gmail.com>
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2019-08-09 Gabriel L. Somlobuild/lattice/trellis: use abc9 techmapping pass with...
Signed-off-by: Gabriel Somlo <gsomlo@gmail.com>
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2019-07-08 Gabriel L. Somlosoc_core: additional csr_alignment follow-up fixes
Signed-off-by: Gabriel Somlo <gsomlo@gmail.com>
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2019-06-27 Gabriel L. SomloBIOS: TFTP: ASCII spinner progress indicator (cosmetic)
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2019-06-18 Gabriel L. Somlotools/litex_sim: fix default endianness for mem_init
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2019-06-18 Gabriel L. Somlocpu/rocket: add "linux" (MMU) and "full" (MMU & FPU...
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2019-06-04 Gabriel L. Somlosoftware/libbase: memcpy: simple, arch-width agnostic...
Signed-off-by: Gabriel Somlo <gsomlo@gmail.com>
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2019-05-29 Gabriel L. Somlosoc/integration/cpu_interface: improve code legibility
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2019-05-23 Gabriel L. Somlofixup: generated-verilog submodule for experimental...
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2019-05-23 Gabriel L. Somlosoc/cores/cpu/rocket: Support for 64-bit RocketChip...
Signed-off-by: Gabriel Somlo <gsomlo@gmail.com>
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2019-05-23 Gabriel L. Somlotools/litex_sim: restore functionality of '--with-sdram...
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2019-05-17 Gabriel L. Somloboards/nexys4ddr: ethernet support fix-up
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2019-05-08 Gabriel L. Somlosoc/integration/cpu_interface: more arch-specific address...
Signed-off-by: Gabriel Somlo <gsomlo@gmail.com>
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2019-04-29 Gabriel L. Somlosoftware: use "unsigned long" for address values, also...
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2019-04-24 Gabriel L. Somlobuild: handle exceptional case when litex/migen not...
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2019-04-17 Gabriel L. Somlobuild/sim/core: Initialize Verilator commandArgs
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2019-03-27 Gabriel L. Somlosoc/interconnect/axi: data/address length cleanup
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2019-03-06 Gabriel L. Somlobuild/lattice/trellis: also generate bitstream in svf...
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