| 2022-03-26 |
Luke Kenneth Casson... | add all 4 CSn lines for Quad HyperRAM PMOD
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commit | commitdiff | tree |
| 2022-03-26 |
Luke Kenneth Casson... | grr
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commit | commitdiff | tree |
| 2022-03-26 |
Luke Kenneth Casson... | reduce power-on-delay bits to 2 for icarus sim ecp5
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commit | commitdiff | tree |
| 2022-03-26 |
Luke Kenneth Casson... | remove switches from hyperram iverilog test
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commit | commitdiff | tree |
| 2022-03-26 |
Luke Kenneth Casson... | remove unneeded model variable
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commit | commitdiff | tree |
| 2022-03-26 |
Luke Kenneth Casson... | add missing ECP5 model OBZ.v and rename testbench
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commit | commitdiff | tree |
| 2022-03-26 |
Luke Kenneth Casson... | sort out platform IO pads for iverilog hyperram sim
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commit | commitdiff | tree |
| 2022-03-26 |
Luke Kenneth Casson... | add hyperram iverilog runner including s27kl0641.v...
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commit | commitdiff | tree |
| 2022-03-25 |
Luke Kenneth Casson... | rename ECP5 CRG, move source, remove duplicate version
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commit | commitdiff | tree |
| 2022-03-25 |
Luke Kenneth Casson... | up arty a7 frequency to 40 mhz
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commit | commitdiff | tree |
| 2022-03-25 |
Luke Kenneth Casson... | increase time for power-on-delay to 2^25 in ECP5
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commit | commitdiff | tree |
| 2022-03-25 |
Luke Kenneth Casson... | loop-test on hyperram read/write which needs carriage...
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commit | commitdiff | tree |
| 2022-03-24 |
Luke Kenneth Casson... | increase delay on ECP5 ulx3s
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commit | commitdiff | tree |
| 2022-03-24 |
Luke Kenneth Casson... | check ulx3s, add CRG support for ulx3s
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commit | commitdiff | tree |
| 2022-03-24 |
Luke Kenneth Casson... | establish power-on reset stabilisation for Arty A7...
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commit | commitdiff | tree |
| 2022-03-22 |
Luke Kenneth Casson... | add hack to modify VERSA_ECP5 85F platform to speed...
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commit | commitdiff | tree |
| 2022-03-22 |
Luke Kenneth Casson... | adding hyperram for arty a7 and also adding a workaround...
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commit | commitdiff | tree |
| 2022-03-20 |
Luke Kenneth Casson... | add microwatt hello_world source
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commit | commitdiff | tree |
| 2022-03-20 |
Luke Kenneth Casson... | crank A7 FPGA speed down to experiment
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commit | commitdiff | tree |
| 2022-03-20 |
Luke Kenneth Casson... | code-comments
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commit | commitdiff | tree |
| 2022-03-20 |
Luke Kenneth Casson... | fix Arty A7-100t PLL with quick demo
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commit | commitdiff | tree |
| 2022-03-20 |
Luke Kenneth Casson... | first cut at Arty A7 Clock-Reset-Generator with S7 PLL
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commit | commitdiff | tree |
| 2022-03-20 |
Luke Kenneth Casson... | beginnings of arty a7 clock-reset-generator
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commit | commitdiff | tree |
| 2022-03-19 |
Luke Kenneth Casson... | add VERSA_ECP5 85F custom board
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commit | commitdiff | tree |
| 2022-03-19 |
Luke Kenneth Casson... | move quick read/write test for hyperram in coldboot.c
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commit | commitdiff | tree |
| 2022-03-19 |
Luke Kenneth Casson... | set IO_TYPE 3.3v attribute on HyperRAM not IOSTANDARD
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commit | commitdiff | tree |
| 2022-03-19 |
Luke Kenneth Casson... | correct pin names for HyperRAMResource, indent spi0...
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commit | commitdiff | tree |
| 2022-03-19 |
Luke Kenneth Casson... | fixed hyperram pin names which was stopping verilator...
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commit | commitdiff | tree |
| 2022-03-19 |
Luke Kenneth Casson... | disable hyperram for now (under investigation)
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commit | commitdiff | tree |
| 2022-03-19 |
Luke Kenneth Casson... | adding in hyperram peripheral
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commit | commitdiff | tree |
| 2022-03-18 |
Luke Kenneth Casson... | whitespace / module-import / comments / tidyup
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commit | commitdiff | tree |
| 2022-03-18 |
Luke Kenneth Casson... | beginning to add hyperram module
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commit | commitdiff | tree |
| 2022-03-18 |
Luke Kenneth Casson... | whitespace cleanup and make SPI core (temporarily)...
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commit | commitdiff | tree |
| 2022-03-17 |
Luke Kenneth Casson... | work-in-progress on DDR3 firmware. sigh
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commit | commitdiff | tree |
| 2022-03-17 |
Luke Kenneth Casson... | comment about icarus verilog to speed up simulations
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commit | commitdiff | tree |
| 2022-03-10 |
Luke Kenneth Casson... | sigh gramWishbone is not WB4-pipeline-burst-compliant
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commit | commitdiff | tree |
| 2022-03-09 |
Luke Kenneth Casson... | fix WB6to32 downconverter with stall signalling
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commit | commitdiff | tree |
| 2022-03-09 |
Luke Kenneth Casson... | add stall signal to arbiter, assume nmigen-soc takes
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commit | commitdiff | tree |
| 2022-03-04 |
Luke Kenneth Casson... | add experimental stall-capable 64-to-32 wishbone converter
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commit | commitdiff | tree |
| 2022-03-02 |
Luke Kenneth Casson... | lots of comments in the yosys script file
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commit | commitdiff | tree |
| 2022-03-02 |
Luke Kenneth Casson... | invert reset and chip-select on dram, and initialise...
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commit | commitdiff | tree |
| 2022-03-02 |
Luke Kenneth Casson... | forgot to include firmware in build for new icarus...
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commit | commitdiff | tree |
| 2022-03-01 |
Luke Kenneth Casson... | add new icarus-versa-ecp5 platform in ls2.py
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commit | commitdiff | tree |
| 2022-02-28 |
Luke Kenneth Casson... | increase timescale of icarus simulation
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commit | commitdiff | tree |
| 2022-02-28 |
Luke Kenneth Casson... | fix undefined uart_tx in icarus simulation, icarus...
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commit | commitdiff | tree |
| 2022-02-28 |
Luke Kenneth Casson... | use a slightly different yosys initialisation sequence...
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commit | commitdiff | tree |
| 2022-02-28 |
Luke Kenneth Casson... | fix memory issue in yosys synth for icarus
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commit | commitdiff | tree |
| 2022-02-28 |
Luke Kenneth Casson... | add icarus simulation of ls2 with DDR3 and ECP5 models
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commit | commitdiff | tree |
| 2022-02-23 |
Luke Kenneth Casson... | invert CRG reset on PLL see if it makes any difference
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commit | commitdiff | tree |
| 2022-02-23 |
Luke Kenneth Casson... | add comments about DRAM sync clock being identical...
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commit | commitdiff | tree |
| 2022-02-22 |
Luke Kenneth Casson... | xdr=4 missing on ddr3 platform request for VERSA_ECP5
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commit | commitdiff | tree |
| 2022-02-21 |
Luke Kenneth Casson... | lengthen cdelay pauses by a factor of 10
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commit | commitdiff | tree |
| 2022-02-21 |
Luke Kenneth Casson... | * use readl and writel for accessing memory
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commit | commitdiff | tree |
| 2022-02-21 |
Luke Kenneth Casson... | use microwatt mmu powerpc.lds with better stack space
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commit | commitdiff | tree |
| 2022-02-20 |
Luke Kenneth Casson... | fix dfi initialisation and calibration to use
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commit | commitdiff | tree |
| 2022-02-20 |
Luke Kenneth Casson... | set RAM base to #defined DRAM_BASE not hard-coded value
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commit | commitdiff | tree |
| 2022-02-20 |
Luke Kenneth Casson... | for simulatio keep the simulated dram in the
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commit | commitdiff | tree |
| 2022-02-20 |
Luke Kenneth Casson... | add fake (sim) DRAM from gram library
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commit | commitdiff | tree |
| 2022-02-19 |
Luke Kenneth Casson... | match up dram initialisation parameters
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commit | commitdiff | tree |
| 2022-02-19 |
Luke Kenneth Casson... | put together coldboot startup firmware
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commit | commitdiff | tree |
| 2022-02-19 |
Luke Kenneth Casson... | hm -abc9 seems to be working, and without -nowidelut
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commit | commitdiff | tree |
| 2022-02-18 |
Luke Kenneth Casson... | add DRAM class to DDR3Soc
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commit | commitdiff | tree |
| 2022-02-18 |
Luke Kenneth Casson... | add FPGA argument to DDR3SoC
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commit | commitdiff | tree |
| 2022-02-18 |
Luke Kenneth Casson... | add microwatt console lib and #includes
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commit | commitdiff | tree |
| 2022-02-18 |
Luke Kenneth Casson... | make cpu optional (test purposes), make bios optional,
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commit | commitdiff | tree |
| 2022-02-16 |
Luke Kenneth Casson... | remove minerva cpu
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commit | commitdiff | tree |
| 2022-02-16 |
Luke Kenneth Casson... | drop clock frequency to 25 mhz and disable abc9 (it...
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commit | commitdiff | tree |
| 2022-02-16 |
Luke Kenneth Casson... | add openocd load command for ecp5
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commit | commitdiff | tree |
| 2022-02-16 |
Luke Kenneth Casson... | wildcards never ok. update comments
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commit | commitdiff | tree |
| 2022-02-16 |
Luke Kenneth Casson... | add copyright notices
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commit | commitdiff | tree |
| 2022-02-16 |
Luke Kenneth Casson... | update ECP5 PLL to accept parameters for setting arbitrary...
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commit | commitdiff | tree |
| 2022-02-16 |
Luke Kenneth Casson... | add start of README as reminder
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commit | commitdiff | tree |
| 2022-02-16 |
Luke Kenneth Casson... | * add uart_pins to UART16550 peripheral so they get...
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commit | commitdiff | tree |
| 2022-02-16 |
Luke Kenneth Casson... | * disable DDR3 for now
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commit | commitdiff | tree |
| 2022-02-15 |
Luke Kenneth Casson... | connect up stall signals (fake) for WB Classic compliance
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commit | commitdiff | tree |
| 2022-02-15 |
Luke Kenneth Casson... | alternative uart wishbone mapping which just takes...
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commit | commitdiff | tree |
| 2022-02-15 |
Luke Kenneth Casson... | attempt to do 8-bit downconvert on wishbone bus for...
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commit | commitdiff | tree |
| 2022-02-15 |
Luke Kenneth Casson... | correct syscon bus address to 0xC000_0000
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commit | commitdiff | tree |
| 2022-02-15 |
Luke Kenneth Casson... | add microwatt SYSCON peripheral at 0xc000_0000
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commit | commitdiff | tree |
| 2022-02-15 |
Luke Kenneth Casson... | increase size of bootmem
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commit | commitdiff | tree |
| 2022-02-15 |
Luke Kenneth Casson... | add interrupt controller module, remove stall feature...
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commit | commitdiff | tree |
| 2022-02-15 |
Luke Kenneth Casson... | FLGA_TARGET=verilator not uppercase
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commit | commitdiff | tree |
| 2022-02-14 |
Luke Kenneth Casson... | add external cpu
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commit | commitdiff | tree |
| 2022-02-14 |
Luke Kenneth Casson... | convert boot rom to bootmem and get first hello_world...
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commit | commitdiff | tree |
| 2022-02-14 |
Luke Kenneth Casson... | add IBM microwatt CC4 license and copyright notices
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commit | commitdiff | tree |
| 2022-02-14 |
Luke Kenneth Casson... | add first cut of verilator simulation, over from microwatt
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commit | commitdiff | tree |
| 2022-02-14 |
Luke Kenneth Casson... | add verilog build option, make DDR3 PHY optional, add...
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commit | commitdiff | tree |
| 2022-02-13 |
Luke Kenneth Casson... | add future sim option (needs Simulated DDR PHY)
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commit | commitdiff | tree |
| 2022-02-13 |
Luke Kenneth Casson... | add build to gitignore
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commit | commitdiff | tree |
| 2022-02-13 |
Luke Kenneth Casson... | rename examples to src
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commit | commitdiff | tree |
| 2022-02-13 |
Luke Kenneth Casson... | not for any good reason, separate adding the uart16550...
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commit | commitdiff | tree |
| 2022-02-13 |
Luke Kenneth Casson... | add MemoryMap to UART16550 (TODO, put that into UART16550...
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commit | commitdiff | tree |
| 2022-02-13 |
Luke Kenneth Casson... | start adding uart16550
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commit | commitdiff | tree |
| 2022-02-13 |
Luke Kenneth Casson... | select a firmware file
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commit | commitdiff | tree |
| 2022-02-13 |
Luke Kenneth Casson... | allow selection of alternative FPGAs at commandline
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commit | commitdiff | tree |
| 2022-02-13 |
Luke Kenneth Casson... | add blinky lights so we know FPGA is alive
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commit | commitdiff | tree |
| 2022-02-13 |
Luke Kenneth Casson... | make firmware and cpu optional for now to get a basic...
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commit | commitdiff | tree |
| 2022-02-12 |
Luke Kenneth Casson... | begin a tidyup on the example
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commit | commitdiff | tree |
| 2022-02-10 |
Luke Kenneth Casson... | resolve imports, whitespace, add Copyright
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commit | commitdiff | tree |
| 2022-02-10 |
Luke Kenneth Casson... | add crg.py
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