2020-07-25 |
Luke Kenneth... | remove old div overflow test, keep microwatt version |
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2020-07-25 |
Luke Kenneth... | hilarious. only just caught a bug where overflow was... |
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2020-07-25 |
Luke Kenneth... | comb += missing |
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2020-07-25 |
Luke Kenneth... | add CR0 regression, expected 0b10 actual 0b11 |
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2020-07-25 |
Luke Kenneth... | add regression test 8, DivPipeCore producing spurious... |
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2020-07-25 |
Luke Kenneth... | add pia back in |
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2020-07-25 |
Luke Kenneth... | re-add pia_result_to_output function (minus "typing... |
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2020-07-25 |
Luke Kenneth... | add div compunit test |
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2020-07-25 |
Luke Kenneth... | wait until pipeline indicates that its output is valid... |
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2020-07-25 |
Luke Kenneth... | move reset of rdmaskn to after "busy" |
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2020-07-25 |
Luke Kenneth... | comment LDST FunctionUnit |
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2020-07-25 |
Luke Kenneth... | going on a bit of a "naming" spree, this for Jean-Paul... |
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2020-07-25 |
Luke Kenneth... | add spec page numbers to logical ops |
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2020-07-25 |
Luke Kenneth... | add page-number comments to ALU main_stage |
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2020-07-25 |
Luke Kenneth... | update comment-headers (TODO include page numbers to... |
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2020-07-25 |
Luke Kenneth... | make trap proof section more readable |
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2020-07-24 |
Samuel A. Falvo II | Properties for MFMSR |
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2020-07-24 |
Samuel A. Falvo II | Reorganize code layout |
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2020-07-24 |
Samuel A. Falvo II | WIP: SC properties more closely match doc'd behavior |
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2020-07-24 |
Cole Poirier | Update libreriscv/HDL_workflow with instructions how... |
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2020-07-24 |
Samuel A. Falvo II | WIP: addressing code review, restoring proofs, etc. |
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2020-07-24 |
Luke Kenneth... | got fed up with bit-slice ordering crap. cut it out |
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2020-07-24 |
Luke Kenneth... | add better comments on field_slice |
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2020-07-24 |
Luke Kenneth... | returned field_slice to original, and added comments |
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2020-07-24 |
Luke Kenneth... | annoying, yet more typos |
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2020-07-24 |
Luke Kenneth... | annoying, typo |
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2020-07-24 |
Luke Kenneth... | better debug assert log message |
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2020-07-24 |
Luke Kenneth... | too much debug info going past, so add the test registe... |
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2020-07-24 |
Luke Kenneth... | missed import |
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2020-07-24 |
Luke Kenneth... | calling the test dictionary from the constructor is... |
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2020-07-24 |
Luke Kenneth... | whoops spelling |
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2020-07-24 |
Luke Kenneth... | add the div pipe kind plus prog.assembly to the assert... |
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2020-07-24 |
Luke Kenneth... | call test_write_ilang only once - ends up being called... |
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2020-07-24 |
Luke Kenneth... | fix how long div tests run, de-comment FSM and DivPipeCore |
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2020-07-24 |
Luke Kenneth... | argh! work-in-progress breaking / fixing how to do... |
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2020-07-24 |
Luke Kenneth... | whoops must add DivTestCasesLong to get it to produce... |
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2020-07-24 |
Luke Kenneth... | remove bad hack calling trunc_divs/trunc_mods |
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2020-07-24 |
Luke Kenneth... | re-enable commented-out div unit tests |
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2020-07-24 |
Luke Kenneth... | split out "all" div into separate unit test (takes... |
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2020-07-24 |
Luke Kenneth... | reduce variable size, continuation not needed |
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2020-07-24 |
Luke Kenneth... | comment about timeline does not exist |
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2020-07-24 |
Luke Kenneth... | ah ha! not using "with" was not calling the "close... |
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2020-07-24 |
Luke Kenneth... | read into a BytesIO to avoid "too many open files" |
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2020-07-24 |
Luke Kenneth... | whitespace / comments |
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2020-07-24 |
Luke Kenneth... | restore modification to caller.py from reversion of... |
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2020-07-24 |
Luke Kenneth... | Revert "working on div's test_pipe_caller" |
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2020-07-24 |
Luke Kenneth... | bug found in pseudocode reader when assembly code has... |
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2020-07-24 |
Luke Kenneth... | submodule update |
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2020-07-24 |
Luke Kenneth... | code review comments for trap and proof |
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2020-07-24 |
Luke Kenneth... | made it clear what is meant by the slice numbering... |
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2020-07-24 |
Samuel A. Falvo II | Refactorin of common code |
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2020-07-24 |
Samuel A. Falvo II | Address code review comments |
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2020-07-24 |
Jacob Lifshay | working on div's test_pipe_caller |
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2020-07-24 |
Jacob Lifshay | add power-instruction-analyzer as a dependency |
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2020-07-24 |
Jacob Lifshay | format |
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2020-07-23 |
Luke Kenneth... | syntax error |
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2020-07-23 |
Luke Kenneth... | support 32-bit mem width setting |
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2020-07-23 |
Luke Kenneth... | try SDRAM SDR |
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2020-07-23 |
Luke Kenneth... | allow imem to be 64/32 bit wide |
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2020-07-23 |
Luke Kenneth... | begin core in running state |
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2020-07-23 |
Luke Kenneth... | try different MEMTEST_xxx sizes with 64 bit bus width |
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2020-07-23 |
Cole Poirier | Update libreriscv HDL_workflow/coriolis2 |
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2020-07-23 |
Jacob Lifshay | add all div* and mod* instructions to test_pipe_caller |
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2020-07-22 |
Jacob Lifshay | working on fsm |
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2020-07-22 |
Jacob Lifshay | Merge remote-tracking branch 'origin/master' |
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2020-07-22 |
Jacob Lifshay | format code |
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2020-07-22 |
Luke Kenneth... | re-add CRG (clock reset generator) |
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2020-07-22 |
Luke Kenneth... | missing ports from issuer, when doing verilog |
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2020-07-22 |
Luke Kenneth... | add clock domain using snippet taken from random file |
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2020-07-22 |
Luke Kenneth... | cleanup in litex core.py |
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2020-07-22 |
Luke Kenneth... | update comments |
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2020-07-22 |
Luke Kenneth... | add dummy irq set/get |
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2020-07-22 |
Luke Kenneth... | add boot-helper.S etc from microwatt litex core |
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2020-07-22 |
Luke Kenneth... | set additional MSR bits according to v3.0B spec when... |
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2020-07-22 |
Luke Kenneth... | use (new) MSRb and PIb which has auto-bigendian numbers |
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2020-07-22 |
Luke Kenneth... | sigh, auto-create some little/big-endian classes for... |
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2020-07-22 |
Luke Kenneth... | missed import of Builder, set cpu_type to "None" tempor... |
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2020-07-22 |
Luke Kenneth... | begin converting litex sim to libre-soc |
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2020-07-22 |
Luke Kenneth... | whoops forgot field accessor |
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2020-07-22 |
Luke Kenneth... | do not use wildcard import |
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2020-07-22 |
Luke Kenneth... | start from vexriscv sim.py from |
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2020-07-22 |
Luke Kenneth... | correct syntax error |
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2020-07-22 |
Luke Kenneth... | first version of litex core (to be submitted upstream... |
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2020-07-22 |
Luke Kenneth... | whoops typo, 63-start not 3-start (doh) |
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2020-07-22 |
Luke Kenneth... | field number ordering wrong way round? |
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2020-07-22 |
Luke Kenneth... | syntax error |
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2020-07-22 |
Luke Kenneth... | review trap main_stage.py modifications: we are not... |
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2020-07-22 |
Luke Kenneth... | comments, add page spec numbers for branch ops into... |
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2020-07-22 |
Luke Kenneth... | add comment headings with spec page numbers |
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2020-07-22 |
Luke Kenneth... | comment on op.insn ordering |
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2020-07-22 |
Luke Kenneth... | code-shuffle, add comments |
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2020-07-22 |
Luke Kenneth... | add TT.size and use it in PowerDecoder and trap input... |
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2020-07-22 |
Luke Kenneth... | inline comments in trap proof |
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2020-07-22 |
Luke Kenneth... | note that traptype MUST increase in bitwidth correspond... |
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2020-07-22 |
Luke Kenneth... | fix branch main_stage proof, add ctr 32-bit, fix BCREG |
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2020-07-22 |
Luke Kenneth... | rework branch proof to use br_input_record |
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2020-07-22 |
Luke Kenneth... | update README for pipe_data.py |
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2020-07-22 |
Luke Kenneth... | reduce number of FastRegs read ports |
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2020-07-22 |
Luke Kenneth... | comments on what goes into CommonPipeSpec |
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2020-07-22 |
Samuel A. Falvo II | Complete FV properties for OP_TRAP instructions. |
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next |