soc.git
2021-10-08 Luke Kenneth... move coresync clock synchronisation into HDLRunner
2021-10-08 Luke Kenneth... whoops missed one function which should be a yield...
2021-10-08 Luke Kenneth... use yield from on StateRunners
2021-10-08 Luke Kenneth... add comments, remove unneeded code
2021-10-08 Luke Kenneth... move pc_i and svstate_i to HDLRunner
2021-10-08 klehmanadd end_test, minor cleanup, added hdlrun.cleanup(...
2021-10-08 klehmanmoved pc_i and sv_state to constructor, remove hdl_stat...
2021-10-08 klehmanchange over run_hdl_state to TestRunner class
2021-10-08 Luke Kenneth... add dummy call to simrun and end_test()
2021-10-08 Luke Kenneth... code-comments and dummy functions
2021-10-08 Luke Kenneth... move contents of run_sim_state into SimRunner run_test...
2021-10-08 Luke Kenneth... add a SimRunner prepare_for_test and run_test function
2021-10-06 Las Safinflake.nix: Clean up
2021-10-05 Las Safinecp5-program: Delete garbage
2021-10-05 Las SafinUpdate lock file
2021-09-26 Las SafinAdd script for loading Libre-SOC onto Versa ECP5 board!
2021-09-25 Las SafinMerge remote-tracking branch 'upstream/master' into pr
2021-09-25 Las SafinUpdate libresoc-litex submodule
2021-09-25 Las SafinUpdate libresoc-litex submodule
2021-09-25 Las SafinFix building for a Versa ECP5
2021-09-25 Las SafinPin version of yosys
2021-09-25 klehmanstart of HDLRunner
2021-09-25 Las SafinGet further building for versa ecp5
2021-09-24 Las SafinAttempt to build for versa ecp5
2021-09-24 Las SafinUpdate nix-litex
2021-09-24 Luke Kenneth... create initial SimRunner
2021-09-24 Luke Kenneth... add shiftrot2 tests to test_issuer.py
2021-09-23 Luke Kenneth... move pc_i and svstate_i inside if self.run_hdl
2021-09-23 Luke Kenneth... more comments
2021-09-23 Luke Kenneth... add in a stack of comments for identifying match-points...
2021-09-23 Luke Kenneth... add option to run ISACaller Sim (or not)
2021-09-23 Luke Kenneth... add a new run_hdl parameter to TestRunner
2021-09-22 Luke Kenneth... completely borked python segfault, workaround to copy...
2021-09-22 Luke Kenneth... add test of expected results against last sim state
2021-09-22 Luke Kenneth... whoops broken run_sim_state function
2021-09-22 Luke Kenneth... split out HDL from Simulator into separate functions
2021-09-22 Luke Kenneth... split out HDL test from Simulator test,
2021-09-22 Tobias PlatenMerge branch 'master' of ssh://git.libre-riscv.org...
2021-09-22 Tobias Platencompldst_multi: add op_is_dcbz signal
2021-09-22 Jacob Lifshayfix mul fu test helper.py not passing immediate to...
2021-09-22 Tobias Platenwhitespace cleanup
2021-09-22 Luke Kenneth... alter setup_tst_memory to take a test.mem rather than...
2021-09-22 Luke Kenneth... whoops forgot to do with self.subTest()
2021-09-21 Tobias PlatenMerge branch 'master' of ssh://git.libre-riscv.org...
2021-09-21 Tobias Platentestcase: add mmu, link mmu and dcache together
2021-09-21 klehmanchanged test_runner to use state mem compare
2021-09-21 klehmanchanged over to use state mem compare
2021-09-21 Tobias PlatenMerge branch 'master' of ssh://git.libre-riscv.org...
2021-09-21 Tobias Platencomment out lines that cause test_compldst_multi_mmu...
2021-09-21 Luke Kenneth... convert HDLState.get_mem() to a dictionary of memory...
2021-09-20 Tobias Platenupdate test_compldst_multi_mmu.py
2021-09-20 Luke Kenneth... use get_l0_mem in HDLState to get memory data
2021-09-19 Cesar StraussFix rel_o/go_i signal names
2021-09-19 Cesar StraussReplace "Display" with "print" on simulation process
2021-09-19 Las SafinUse LiteX from 2020-08-22
2021-09-19 Las SafinAdd ppc64le cross compiler
2021-09-19 Cesar StraussFix import
2021-09-19 Las SafinLitex work
2021-09-18 Cesar StraussUse a pre-compiled version of maturin
2021-09-18 Las SafinLitex work
2021-09-18 Luke Kenneth... allow individual unit tests to be named in test_issuer.py
2021-09-18 Luke Kenneth... always store full memory state (including zeros)
2021-09-18 klehmanadded get_mem
2021-09-17 Luke Kenneth... update comments
2021-09-16 Luke Kenneth... moving teststate_check_regs written by klehman into...
2021-09-16 Las SafinSplit up into several derivations
2021-09-16 Las Safinwip
2021-09-15 Las SafinInclude Litex dependency
2021-09-15 isengaaraMerge branch 'master' of ssh://git.libre-riscv.org...
2021-09-15 isengaaraadd new testcase for ompldst_multi using mmu
2021-09-15 Las SafinWIP
2021-09-14 Luke Kenneth... convert to using TestState and State after moving to...
2021-09-14 klehmanfactory add and intro doc string
2021-09-13 Las SafinFix nmigen dependencies
2021-09-13 Las SafinGet pinmux working
2021-09-13 Cesar StraussSave Gitlab runner cache, even on a failed test
2021-09-12 Las SafinFix c4m-jtag
2021-09-12 Las SafinPackage c4m-jtag
2021-09-12 Las SafinFix openpower-isa
2021-09-12 Luke Kenneth... use log instead of print
2021-09-12 Luke Kenneth... code comments
2021-09-12 Luke Kenneth... create new function teststate_check_regs which is calle...
2021-09-12 klehmanchanges to utilize full teststate class
2021-09-12 klehmanadded compare function
2021-09-12 klehmanadded factory function for test class creation
2021-09-11 Las SafinGet build starting
2021-09-11 Las SafinPackage dependencies successfully
2021-09-11 Las SafinPython dependencies
2021-09-11 Las Safinwip
2021-09-10 klehmanimplement base class in state class
2021-09-10 klehmanchanges made to utilize teststate class
2021-09-10 Luke Kenneth... update explanatory comments on LD/ST exception handling
2021-09-09 klehmanmade sim into generators and some uniformity changes
2021-09-09 klehmanfinished remaining hdl items
2021-09-09 klehmanHDL int reg added
2021-09-09 klehmanmore sim class registers add
2021-09-08 Cesar StraussMonitor exceptions, re-decoding the instruction in...
2021-09-08 klehmaninitial commit of sim state class
2021-09-08 Cesar StraussMonitor the exception input to PowerDecoder2
2021-09-08 Cesar StraussRemove default argument for dict.get()
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