soc.git
2020-08-11 Luke Kenneth... reduce regfile port usage for INT and FAST
2020-08-11 Luke Kenneth... prepare write ports to be shared
2020-08-11 Luke Kenneth... move write regfile picker creation to new function
2020-08-11 Luke Kenneth... reduce regfile ports by creating separate STATE regfile
2020-08-11 Luke Kenneth... whoops fix change of variable (state) msr/pc
2020-08-11 Luke Kenneth... reducing regfile port usage by sharing read ports
2020-08-10 Samuel A. Falvo IIWIP!! Make MUL pipeline proof run again.
2020-08-10 Cole PoirierFix typo in mmu.py
2020-08-10 Cole PoirierFix typo mmu.py
2020-08-10 Cole PoirierGlobal search and replace (^, |), fixes bug 450 comment...
2020-08-10 Cole Poirierfix bug 450 comments 8,9,10
2020-08-10 Cole PoirierFix bug 450 comment 7
2020-08-10 Cole Poiriermmu.py add line I forgot to translate from mmu.vhdl
2020-08-10 Cole PoirierMerge branch 'master' of git.libre-soc.org:soc
2020-08-10 Cole Poiriermmu.vhdl translation to mmu.py 95 percent complete
2020-08-09 Luke Kenneth... stop combinatorial loop in pi2ls
2020-08-09 Luke Kenneth... write pulse in issuer
2020-08-09 Luke Kenneth... fix combinatorial loop in ldst compunit
2020-08-09 Luke Kenneth... use rising edge detection on st go_i/rel_o
2020-08-09 Luke Kenneth... add logical test issuer case
2020-08-09 Luke Kenneth... get rid of MSR read combinatorial loop
2020-08-09 Luke Kenneth... delay go_st by one cycle, break combinatorial loop
2020-08-09 Luke Kenneth... divwo case makes test_issuer stay busy!
2020-08-09 Luke Kenneth... add extra divwo regression test
2020-08-09 Luke Kenneth... compalu combinatorial loop detected
2020-08-08 Cole PoirierMerge branch 'master' of git.libre-soc.org:soc
2020-08-08 Cole PoirierUpdate test case_mulli
2020-08-08 Tobias Platenaddr_split.py: shift bytes not bits
2020-08-07 Cole PoirierUpdate test case_mulli
2020-08-07 Cole PoirierUpdate test case_mulli, I think it now works correctly
2020-08-07 Cole PoirierUpdate mulli to try to use immediates not registers
2020-08-06 Cole PoirierFix mmu.py formatting
2020-08-06 Cole PoirierFix formatting
2020-08-06 Cole PoirierInitial commit of translation of microwatt mmu.vhdl...
2020-08-06 Cole PoirierMerge branch 'master' of git.libre-soc.org:soc
2020-08-06 Cole PoirierUpdate test case_all_rb_close_to_ov
2020-08-06 Cole PoirierUpdate test case_all_rb_close_to_ov
2020-08-06 Luke Kenneth... fix LDST PortInterface FSM interaction
2020-08-06 Luke Kenneth... MULS on parameter b needed to check whether it was...
2020-08-06 Cole PoirierAdd special test for case_mulli, apply autopep8
2020-08-05 Cole PoirierAdd test case_all_rb_close_to_ov
2020-08-05 Cole PoirierRemove mulli from instrs in test case_all*, add TODO...
2020-08-05 Cole PoirierAdd new test_values to tests case_all and case_all_rb_r...
2020-08-05 Cole PoirierAdd second case_all test where rb is randint
2020-08-05 Tobias PlatenMerge branch 'master' of ssh://git.libre-riscv.org...
2020-08-05 Tobias Platenundo changes that fix unit test, but do not solve anything
2020-08-05 Luke Kenneth... rename ibus/dbus (shorten)
2020-08-05 Luke Kenneth... clear sel on loadstore
2020-08-05 Tobias Platenfix LDSTSplitter
2020-08-05 Cole PoirierRemove madd* isns, added madd* isns test TODO
2020-08-05 Cole PoirierMerge branch 'master' of git.libre-soc.org:soc
2020-08-05 Luke Kenneth... adding bus data width of 64 in litex sim doesnt work
2020-08-05 Luke Kenneth... add div test cases into test_issuer.py
2020-08-05 Luke Kenneth... add div FSM as default for test_issuer in verilog and...
2020-08-05 Cole PoirierMerge branch 'master' of git.libre-soc.org:soc
2020-08-05 Jacob LifshayFixed div pipe with FSM
2020-08-05 Cole PoirierFix pysim deprecation warning
2020-08-05 Cole PoirierAdd case_all to MUL unit tests, remove duplicate test...
2020-08-04 Luke Kenneth... read/set pc outside of FSM so that DMI interface can...
2020-08-04 Luke Kenneth... swap over byte-reverse if/else in LDSTCompUnit
2020-08-04 Luke Kenneth... tracked down byte-reversal in LDST ISACaller and LDSTCo...
2020-08-04 Luke Kenneth... whitespace after autopep8 messed up
2020-08-04 Luke Kenneth... msr and pc moved to "state" in PowerDecode2
2020-08-04 Luke Kenneth... whoops must output NIA not PC to debug DMI query in...
2020-08-04 Luke Kenneth... allow instruction to run if initiated whilst "stopped...
2020-08-04 Luke Kenneth... cycle through INT regs, read and debug in litex sim
2020-08-04 Luke Kenneth... add DMI debug interface to libresoc litex sim
2020-08-04 Luke Kenneth... single-step and print out PC using DMI in litex sim
2020-08-04 Luke Kenneth... get litex sim to kick off a "STEP" via the DMI interfac...
2020-08-04 Luke Kenneth... connect up a DMI FSM to litex sim
2020-08-04 Luke Kenneth... more remove wildcard imports
2020-08-04 Luke Kenneth... do not use wildcard imports
2020-08-04 Luke Kenneth... adding litex sim experimentation.
2020-08-04 Samuel A. Falvo IIRemove XXX; this seems done otherwise.
2020-08-03 Luke Kenneth... add quick demo/test of reading DMI reg 9
2020-08-03 Luke Kenneth... add extra port for debug read of int regs via DMI
2020-08-03 Luke Kenneth... pass state (MSR/PC) around between PowerDecode2, DMI...
2020-08-03 Luke Kenneth... https://bugs.libre-soc.org/show_bug.cgi?id=446
2020-08-03 Luke Kenneth... use new soc.config.state CoreState class in DMI and...
2020-08-03 Tobias PlatenLDSTSplitter: report exception
2020-08-03 Tobias PlatenMerge branch 'master' of ssh://git.libre-riscv.org...
2020-08-03 Tobias PlatenTstDataMerger2
2020-08-03 Luke Kenneth... change over to DMI debug start/stop interface
2020-08-03 Luke Kenneth... move debug to record
2020-08-03 Samuel A. Falvo IIWIP: check MB > ME and select mask appropriately
2020-08-02 Luke Kenneth... convert microwatt core_debug.vhdl to nmigen
2020-08-02 Luke Kenneth... add debug dir
2020-08-01 Luke Kenneth... add quick test of litex bios IMM64 macro
2020-08-01 Luke Kenneth... add rlwnm test showing that shift rot OP_RLC proof...
2020-08-01 Luke Kenneth... line-length / whitespace
2020-08-01 Luke Kenneth... expand out for-loop setting up input record subset
2020-07-31 Luke Kenneth... reorg DecodeB in power_decoder2.py to sign-extend immed...
2020-07-31 Luke Kenneth... add more instructions to litex trampoline test (not...
2020-07-31 Luke Kenneth... restrict external port list further in test_issuer
2020-07-31 Luke Kenneth... missed go_i/rel_o rename
2020-07-31 Samuel A. Falvo IIWIP: more debugging signals for inspection
2020-07-30 Samuel A. Falvo IIWIP: rlwinm/rlwnm/rlwimi-type proofs
2020-07-30 Tobias Platenbegin work on TestCase for two DataMergers/Cache
2020-07-30 Tobias Platenadd CacheRecord
2020-07-30 Luke Kenneth... core_start/stop/endian were inverted (output)
next