2021-12-11 |
Tobias Platen | add skeleton for test_loadstore1_ifetch_multi() |
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2021-12-11 |
Luke Kenneth... | add start of test_loadstore1_ifetch_unit_interface() |
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2021-12-11 |
Luke Kenneth... | connect up I-Cache to FetchUnitInterface |
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2021-12-11 |
Luke Kenneth... | add new ConfigFetchUnit option "mmu_cache_wb" which... |
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2021-12-10 |
Jacob Lifshay | add ternlogi to shift_rot formal test |
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2021-12-10 |
Jacob Lifshay | fix shift_rot formal proof |
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2021-12-10 |
Jacob Lifshay | add formal_test_temp to .gitignore |
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2021-12-10 |
Tobias Platen | use icache_read in one place |
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2021-12-10 |
Tobias Platen | test_loadstore1.py: begin code deduplication |
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2021-12-09 |
Luke Kenneth... | add some examination of the failed-fetched instruction |
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2021-12-09 |
Luke Kenneth... | add some debug string info to gtkwave |
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2021-12-09 |
Tobias Platen | implement main part of test_loadstore1_ifetch_invalid() |
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2021-12-09 |
Tobias Platen | cleanup test_loadstore1.py |
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2021-12-09 |
Luke Kenneth... | add I-Cache to FSM local variables |
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2021-12-09 |
Luke Kenneth... | wire fetch_failed from I-Cache to PowerDecoder2 |
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2021-12-09 |
Luke Kenneth... | make icache accessible to core, working back to TestIssuer |
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2021-12-09 |
Luke Kenneth... | include SPR.TB in SPR FU |
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2021-12-09 |
Jacob Lifshay | add bitmanip tests |
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2021-12-09 |
Jacob Lifshay | add CommonPipeSpec.__getattr__ to forward attributes... |
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2021-12-09 |
Jacob Lifshay | add parent_pspec everywhere |
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2021-12-09 |
Jacob Lifshay | make argv handling more flexible |
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2021-12-09 |
Jacob Lifshay | format code |
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2021-12-08 |
Luke Kenneth... | got fed up of staring at magic constants in the MMU |
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2021-12-08 |
Luke Kenneth... | add special pagetable to ifetch_invalid with execute... |
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2021-12-08 |
Luke Kenneth... | do not try priv_mode on the instruction fetch (not... |
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2021-12-08 |
Luke Kenneth... | add an example pagetable where executable permission... |
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2021-12-08 |
Tobias Platen | begin working on _test_loadstore1_ifetch_invalid()... |
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2021-12-08 |
Tobias Platen | more work on test_loadstore1_ifetch_invalid() |
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2021-12-08 |
Tobias Platen | Merge branch 'master' of ssh://git.libre-riscv.org... |
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2021-12-08 |
Tobias Platen | add skeleton for test_loadstore1_ifetch_invalid() |
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2021-12-08 |
Luke Kenneth... | check that no exception occurs in the virtual-memory... |
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2021-12-08 |
Luke Kenneth... | add OP_FETCH_FAILED to MMU Function Unit |
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2021-12-08 |
Luke Kenneth... | make LoadStore1 intsr_fault a "captured flag" - strictl... |
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2021-12-08 |
Luke Kenneth... | remove MSR and add CIA to MMU Input Record |
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2021-12-08 |
Luke Kenneth... | add instr_fault to LoadStore1 FSM |
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2021-12-08 |
Luke Kenneth... | add new PortInterfaceBase external_busy() option |
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2021-12-08 |
Jacob Lifshay | add comment about draft instructions |
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2021-12-08 |
Jacob Lifshay | account for Mock absurdities |
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2021-12-07 |
Luke Kenneth... | complete the i-cache fetch through the MMU, including... |
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2021-12-07 |
Luke Kenneth... | set separate "iside" signal in LoadStore1 to not confuse it |
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2021-12-07 |
Luke Kenneth... | start extending icache loadstore test |
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2021-12-07 |
Luke Kenneth... | whoops another serious error in the CacheTagArray |
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2021-12-07 |
Luke Kenneth... | add first i-cache fetch (non-virtual), no MMU lookup... |
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2021-12-07 |
Luke Kenneth... | code-comments |
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2021-12-07 |
Luke Kenneth... | add in I-Cache into LoadStore1 - presently unused ... |
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2021-12-07 |
Luke Kenneth... | add discussion links and bugreport |
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2021-12-07 |
Luke Kenneth... | invert mmureq statements |
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2021-12-07 |
Luke Kenneth... | submodule tidyup |
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2021-12-07 |
Jacob Lifshay | make bitmanip operations conditional on pspec.draft_bit... |
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2021-12-07 |
Jacob Lifshay | format code |
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2021-12-07 |
Jacob Lifshay | move rotator mode assignments as requested by lkcl |
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2021-12-07 |
Jacob Lifshay | format code |
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2021-12-07 |
Luke Kenneth... | tidyup, comments |
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2021-12-07 |
Luke Kenneth... | debug print |
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2021-12-06 |
Luke Kenneth... | another major bug, CacheTagArray valid was only 1 bit... |
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2021-12-06 |
Luke Kenneth... | tidyup: move hit_set to DCachePendingHit in dcache.py |
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2021-12-06 |
Luke Kenneth... | dcache.py tidyup |
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2021-12-06 |
Luke Kenneth... | rename dtlb to dtlb_valid and tidyup |
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2021-12-06 |
Luke Kenneth... | convert TLBArray to TLBValidArray |
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2021-12-06 |
Luke Kenneth... | convert DTLBUpdate to use a pair of Memorys |
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2021-12-06 |
Luke Kenneth... | more signals local to DTLBUpdate |
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2021-12-06 |
Luke Kenneth... | more signals local to DTLBUpdate |
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2021-12-06 |
Luke Kenneth... | update DTLBUpdate to reflect internal API now |
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2021-12-06 |
Luke Kenneth... | ooo nasty bug. used tlb_hit.way instead of tlb_hit... |
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2021-12-06 |
Luke Kenneth... | move DTLB Tags/Valids/PTEs into DTLBUpdate module |
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2021-12-06 |
Luke Kenneth... | start moving TLBArray into DTLBUpdate |
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2021-12-06 |
Luke Kenneth... | PLRUs were selecting an output index, only one selected |
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2021-12-06 |
Luke Kenneth... | repeated copies of read/write addr/sel to Cache SRAMs |
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2021-12-06 |
Luke Kenneth... | move bank of PLRUs to their own submodule in both dcach... |
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2021-12-06 |
Luke Kenneth... | code-comments |
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2021-12-06 |
Luke Kenneth... | use binary-to-unary encoders in dcache.py |
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2021-12-06 |
Luke Kenneth... | global (one) do_read signal in cache_rams dcache.py |
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2021-12-06 |
Luke Kenneth... | use one-hot binary-to-unary in dcache.py |
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2021-12-06 |
Luke Kenneth... | use i_in.req to gate hit_way via Decoder in icache.py |
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2021-12-06 |
Luke Kenneth... | use Decoder (binary-to-unary) in icache.py to deal... |
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2021-12-05 |
Luke Kenneth... | use unary encoding (one-hot) for replace_way hit_way... |
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2021-12-05 |
Luke Kenneth... | code-comments |
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2021-12-05 |
Luke Kenneth... | whitespace and minor cleanup of D-Cache |
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2021-12-05 |
Luke Kenneth... | more use of TLBHit Record in D-Cache |
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2021-12-05 |
Luke Kenneth... | correct tlb_hit_way and index sizes, use TLBHit Record... |
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2021-12-05 |
Luke Kenneth... | use TLBRecord in D-Cache for which TLB is selected |
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2021-12-05 |
Luke Kenneth... | split out TLBRecord, correct number of valid bits |
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2021-12-05 |
Luke Kenneth... | use Record in DCache for TLB |
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2021-12-05 |
Luke Kenneth... | use Record in D-Cache Cache Tags |
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2021-12-05 |
Luke Kenneth... | whitespace |
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2021-12-05 |
Luke Kenneth... | use Record for I-Cache Cache Tag/Valid |
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2021-12-05 |
Luke Kenneth... | whitespace |
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2021-12-05 |
Luke Kenneth... | use Record for ICache TLB |
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2021-12-05 |
Luke Kenneth... | sorting out test_mmu_dcache.py to use wb_get |
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2021-12-05 |
Luke Kenneth... | convert icache.py to standard wishbone Interface |
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2021-12-05 |
Luke Kenneth... | fake up wishbone stall signal in icache. |
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2021-12-05 |
Luke Kenneth... | fix icache row store issue |
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2021-12-05 |
Luke Kenneth... | using same tag/row functions as in dcache.py |
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2021-12-05 |
Luke Kenneth... | more signal sizes in icache.py |
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2021-12-05 |
Luke Kenneth... | incorrect Signal sizes in icache.py, |
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2021-12-05 |
Luke Kenneth... | sorting out icache.py, used to work |
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2021-12-05 |
Luke Kenneth... | remove redundant code |
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2021-12-05 |
Luke Kenneth... | add I-Cache standard bus (not used yet) |
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2021-12-05 |
Luke Kenneth... | remove yet another duplicate copy of wb_get, possible... |
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2021-12-05 |
Luke Kenneth... | replace yet another duplicate copy of wb_get, possible... |
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