soc.git
2021-12-11 Tobias Platenadd skeleton for test_loadstore1_ifetch_multi()
2021-12-11 Luke Kenneth... add start of test_loadstore1_ifetch_unit_interface()
2021-12-11 Luke Kenneth... connect up I-Cache to FetchUnitInterface
2021-12-11 Luke Kenneth... add new ConfigFetchUnit option "mmu_cache_wb" which...
2021-12-10 Jacob Lifshayadd ternlogi to shift_rot formal test
2021-12-10 Jacob Lifshayfix shift_rot formal proof
2021-12-10 Jacob Lifshayadd formal_test_temp to .gitignore
2021-12-10 Tobias Platenuse icache_read in one place
2021-12-10 Tobias Platentest_loadstore1.py: begin code deduplication
2021-12-09 Luke Kenneth... add some examination of the failed-fetched instruction
2021-12-09 Luke Kenneth... add some debug string info to gtkwave
2021-12-09 Tobias Platenimplement main part of test_loadstore1_ifetch_invalid()
2021-12-09 Tobias Platencleanup test_loadstore1.py
2021-12-09 Luke Kenneth... add I-Cache to FSM local variables
2021-12-09 Luke Kenneth... wire fetch_failed from I-Cache to PowerDecoder2
2021-12-09 Luke Kenneth... make icache accessible to core, working back to TestIssuer
2021-12-09 Luke Kenneth... include SPR.TB in SPR FU
2021-12-09 Jacob Lifshayadd bitmanip tests
2021-12-09 Jacob Lifshayadd CommonPipeSpec.__getattr__ to forward attributes...
2021-12-09 Jacob Lifshayadd parent_pspec everywhere
2021-12-09 Jacob Lifshaymake argv handling more flexible
2021-12-09 Jacob Lifshayformat code
2021-12-08 Luke Kenneth... got fed up of staring at magic constants in the MMU
2021-12-08 Luke Kenneth... add special pagetable to ifetch_invalid with execute...
2021-12-08 Luke Kenneth... do not try priv_mode on the instruction fetch (not...
2021-12-08 Luke Kenneth... add an example pagetable where executable permission...
2021-12-08 Tobias Platenbegin working on _test_loadstore1_ifetch_invalid()...
2021-12-08 Tobias Platenmore work on test_loadstore1_ifetch_invalid()
2021-12-08 Tobias PlatenMerge branch 'master' of ssh://git.libre-riscv.org...
2021-12-08 Tobias Platenadd skeleton for test_loadstore1_ifetch_invalid()
2021-12-08 Luke Kenneth... check that no exception occurs in the virtual-memory...
2021-12-08 Luke Kenneth... add OP_FETCH_FAILED to MMU Function Unit
2021-12-08 Luke Kenneth... make LoadStore1 intsr_fault a "captured flag" - strictl...
2021-12-08 Luke Kenneth... remove MSR and add CIA to MMU Input Record
2021-12-08 Luke Kenneth... add instr_fault to LoadStore1 FSM
2021-12-08 Luke Kenneth... add new PortInterfaceBase external_busy() option
2021-12-08 Jacob Lifshayadd comment about draft instructions
2021-12-08 Jacob Lifshayaccount for Mock absurdities
2021-12-07 Luke Kenneth... complete the i-cache fetch through the MMU, including...
2021-12-07 Luke Kenneth... set separate "iside" signal in LoadStore1 to not confuse it
2021-12-07 Luke Kenneth... start extending icache loadstore test
2021-12-07 Luke Kenneth... whoops another serious error in the CacheTagArray
2021-12-07 Luke Kenneth... add first i-cache fetch (non-virtual), no MMU lookup...
2021-12-07 Luke Kenneth... code-comments
2021-12-07 Luke Kenneth... add in I-Cache into LoadStore1 - presently unused ...
2021-12-07 Luke Kenneth... add discussion links and bugreport
2021-12-07 Luke Kenneth... invert mmureq statements
2021-12-07 Luke Kenneth... submodule tidyup
2021-12-07 Jacob Lifshaymake bitmanip operations conditional on pspec.draft_bit...
2021-12-07 Jacob Lifshayformat code
2021-12-07 Jacob Lifshaymove rotator mode assignments as requested by lkcl
2021-12-07 Jacob Lifshayformat code
2021-12-07 Luke Kenneth... tidyup, comments
2021-12-07 Luke Kenneth... debug print
2021-12-06 Luke Kenneth... another major bug, CacheTagArray valid was only 1 bit...
2021-12-06 Luke Kenneth... tidyup: move hit_set to DCachePendingHit in dcache.py
2021-12-06 Luke Kenneth... dcache.py tidyup
2021-12-06 Luke Kenneth... rename dtlb to dtlb_valid and tidyup
2021-12-06 Luke Kenneth... convert TLBArray to TLBValidArray
2021-12-06 Luke Kenneth... convert DTLBUpdate to use a pair of Memorys
2021-12-06 Luke Kenneth... more signals local to DTLBUpdate
2021-12-06 Luke Kenneth... more signals local to DTLBUpdate
2021-12-06 Luke Kenneth... update DTLBUpdate to reflect internal API now
2021-12-06 Luke Kenneth... ooo nasty bug. used tlb_hit.way instead of tlb_hit...
2021-12-06 Luke Kenneth... move DTLB Tags/Valids/PTEs into DTLBUpdate module
2021-12-06 Luke Kenneth... start moving TLBArray into DTLBUpdate
2021-12-06 Luke Kenneth... PLRUs were selecting an output index, only one selected
2021-12-06 Luke Kenneth... repeated copies of read/write addr/sel to Cache SRAMs
2021-12-06 Luke Kenneth... move bank of PLRUs to their own submodule in both dcach...
2021-12-06 Luke Kenneth... code-comments
2021-12-06 Luke Kenneth... use binary-to-unary encoders in dcache.py
2021-12-06 Luke Kenneth... global (one) do_read signal in cache_rams dcache.py
2021-12-06 Luke Kenneth... use one-hot binary-to-unary in dcache.py
2021-12-06 Luke Kenneth... use i_in.req to gate hit_way via Decoder in icache.py
2021-12-06 Luke Kenneth... use Decoder (binary-to-unary) in icache.py to deal...
2021-12-05 Luke Kenneth... use unary encoding (one-hot) for replace_way hit_way...
2021-12-05 Luke Kenneth... code-comments
2021-12-05 Luke Kenneth... whitespace and minor cleanup of D-Cache
2021-12-05 Luke Kenneth... more use of TLBHit Record in D-Cache
2021-12-05 Luke Kenneth... correct tlb_hit_way and index sizes, use TLBHit Record...
2021-12-05 Luke Kenneth... use TLBRecord in D-Cache for which TLB is selected
2021-12-05 Luke Kenneth... split out TLBRecord, correct number of valid bits
2021-12-05 Luke Kenneth... use Record in DCache for TLB
2021-12-05 Luke Kenneth... use Record in D-Cache Cache Tags
2021-12-05 Luke Kenneth... whitespace
2021-12-05 Luke Kenneth... use Record for I-Cache Cache Tag/Valid
2021-12-05 Luke Kenneth... whitespace
2021-12-05 Luke Kenneth... use Record for ICache TLB
2021-12-05 Luke Kenneth... sorting out test_mmu_dcache.py to use wb_get
2021-12-05 Luke Kenneth... convert icache.py to standard wishbone Interface
2021-12-05 Luke Kenneth... fake up wishbone stall signal in icache.
2021-12-05 Luke Kenneth... fix icache row store issue
2021-12-05 Luke Kenneth... using same tag/row functions as in dcache.py
2021-12-05 Luke Kenneth... more signal sizes in icache.py
2021-12-05 Luke Kenneth... incorrect Signal sizes in icache.py,
2021-12-05 Luke Kenneth... sorting out icache.py, used to work
2021-12-05 Luke Kenneth... remove redundant code
2021-12-05 Luke Kenneth... add I-Cache standard bus (not used yet)
2021-12-05 Luke Kenneth... remove yet another duplicate copy of wb_get, possible...
2021-12-05 Luke Kenneth... replace yet another duplicate copy of wb_get, possible...
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