2021-10-08 |
Luke Kenneth... | use yield from on StateRunners |
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2021-10-08 |
Luke Kenneth... | add comments, remove unneeded code |
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2021-10-08 |
Luke Kenneth... | move pc_i and svstate_i to HDLRunner |
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2021-10-08 |
klehman | add end_test, minor cleanup, added hdlrun.cleanup(... |
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2021-10-08 |
klehman | moved pc_i and sv_state to constructor, remove hdl_stat... |
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2021-10-08 |
klehman | change over run_hdl_state to TestRunner class |
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2021-10-08 |
Luke Kenneth... | add dummy call to simrun and end_test() |
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2021-10-08 |
Luke Kenneth... | code-comments and dummy functions |
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2021-10-08 |
Luke Kenneth... | move contents of run_sim_state into SimRunner run_test... |
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2021-10-08 |
Luke Kenneth... | add a SimRunner prepare_for_test and run_test function |
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2021-10-06 |
Las Safin | flake.nix: Clean up |
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2021-10-05 |
Las Safin | ecp5-program: Delete garbage |
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2021-10-05 |
Las Safin | Update lock file |
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2021-09-26 |
Las Safin | Add script for loading Libre-SOC onto Versa ECP5 board! |
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2021-09-25 |
Las Safin | Merge remote-tracking branch 'upstream/master' into pr |
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2021-09-25 |
Las Safin | Update libresoc-litex submodule |
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2021-09-25 |
Las Safin | Update libresoc-litex submodule |
commit | commitdiff | tree |
2021-09-25 |
Las Safin | Fix building for a Versa ECP5 |
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2021-09-25 |
Las Safin | Pin version of yosys |
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2021-09-25 |
klehman | start of HDLRunner |
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2021-09-25 |
Las Safin | Get further building for versa ecp5 |
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2021-09-24 |
Las Safin | Attempt to build for versa ecp5 |
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2021-09-24 |
Las Safin | Update nix-litex |
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2021-09-24 |
Luke Kenneth... | create initial SimRunner |
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2021-09-24 |
Luke Kenneth... | add shiftrot2 tests to test_issuer.py |
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2021-09-23 |
Luke Kenneth... | move pc_i and svstate_i inside if self.run_hdl |
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2021-09-23 |
Luke Kenneth... | more comments |
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2021-09-23 |
Luke Kenneth... | add in a stack of comments for identifying match-points... |
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2021-09-23 |
Luke Kenneth... | add option to run ISACaller Sim (or not) |
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2021-09-23 |
Luke Kenneth... | add a new run_hdl parameter to TestRunner |
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2021-09-22 |
Luke Kenneth... | completely borked python segfault, workaround to copy... |
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2021-09-22 |
Luke Kenneth... | add test of expected results against last sim state |
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2021-09-22 |
Luke Kenneth... | whoops broken run_sim_state function |
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2021-09-22 |
Luke Kenneth... | split out HDL from Simulator into separate functions |
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2021-09-22 |
Luke Kenneth... | split out HDL test from Simulator test, |
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2021-09-22 |
Tobias Platen | Merge branch 'master' of ssh://git.libre-riscv.org... |
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2021-09-22 |
Tobias Platen | compldst_multi: add op_is_dcbz signal |
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2021-09-22 |
Jacob Lifshay | fix mul fu test helper.py not passing immediate to... |
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2021-09-22 |
Tobias Platen | whitespace cleanup |
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2021-09-22 |
Luke Kenneth... | alter setup_tst_memory to take a test.mem rather than... |
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2021-09-22 |
Luke Kenneth... | whoops forgot to do with self.subTest() |
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2021-09-21 |
Tobias Platen | Merge branch 'master' of ssh://git.libre-riscv.org... |
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2021-09-21 |
Tobias Platen | testcase: add mmu, link mmu and dcache together |
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2021-09-21 |
klehman | changed test_runner to use state mem compare |
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2021-09-21 |
klehman | changed over to use state mem compare |
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2021-09-21 |
Tobias Platen | Merge branch 'master' of ssh://git.libre-riscv.org... |
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2021-09-21 |
Tobias Platen | comment out lines that cause test_compldst_multi_mmu... |
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2021-09-21 |
Luke Kenneth... | convert HDLState.get_mem() to a dictionary of memory... |
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2021-09-20 |
Tobias Platen | update test_compldst_multi_mmu.py |
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2021-09-20 |
Luke Kenneth... | use get_l0_mem in HDLState to get memory data |
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2021-09-19 |
Cesar Strauss | Fix rel_o/go_i signal names |
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2021-09-19 |
Cesar Strauss | Replace "Display" with "print" on simulation process |
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2021-09-19 |
Las Safin | Use LiteX from 2020-08-22 |
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2021-09-19 |
Las Safin | Add ppc64le cross compiler |
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2021-09-19 |
Cesar Strauss | Fix import |
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2021-09-19 |
Las Safin | Litex work |
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2021-09-18 |
Cesar Strauss | Use a pre-compiled version of maturin |
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2021-09-18 |
Las Safin | Litex work |
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2021-09-18 |
Luke Kenneth... | allow individual unit tests to be named in test_issuer.py |
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2021-09-18 |
Luke Kenneth... | always store full memory state (including zeros) |
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2021-09-18 |
klehman | added get_mem |
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2021-09-17 |
Luke Kenneth... | update comments |
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2021-09-16 |
Luke Kenneth... | moving teststate_check_regs written by klehman into... |
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2021-09-16 |
Las Safin | Split up into several derivations |
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2021-09-16 |
Las Safin | wip |
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2021-09-15 |
Las Safin | Include Litex dependency |
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2021-09-15 |
isengaara | Merge branch 'master' of ssh://git.libre-riscv.org... |
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2021-09-15 |
isengaara | add new testcase for ompldst_multi using mmu |
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2021-09-15 |
Las Safin | WIP |
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2021-09-14 |
Luke Kenneth... | convert to using TestState and State after moving to... |
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2021-09-14 |
klehman | factory add and intro doc string |
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2021-09-13 |
Las Safin | Fix nmigen dependencies |
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2021-09-13 |
Las Safin | Get pinmux working |
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2021-09-13 |
Cesar Strauss | Save Gitlab runner cache, even on a failed test |
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2021-09-12 |
Las Safin | Fix c4m-jtag |
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2021-09-12 |
Las Safin | Package c4m-jtag |
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2021-09-12 |
Las Safin | Fix openpower-isa |
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2021-09-12 |
Luke Kenneth... | use log instead of print |
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2021-09-12 |
Luke Kenneth... | code comments |
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2021-09-12 |
Luke Kenneth... | create new function teststate_check_regs which is calle... |
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2021-09-12 |
klehman | changes to utilize full teststate class |
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2021-09-12 |
klehman | added compare function |
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2021-09-12 |
klehman | added factory function for test class creation |
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2021-09-11 |
Las Safin | Get build starting |
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2021-09-11 |
Las Safin | Package dependencies successfully |
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2021-09-11 |
Las Safin | Python dependencies |
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2021-09-11 |
Las Safin | wip |
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2021-09-10 |
klehman | implement base class in state class |
commit | commitdiff | tree |
2021-09-10 |
klehman | changes made to utilize teststate class |
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2021-09-10 |
Luke Kenneth... | update explanatory comments on LD/ST exception handling |
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2021-09-09 |
klehman | made sim into generators and some uniformity changes |
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2021-09-09 |
klehman | finished remaining hdl items |
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2021-09-09 |
klehman | HDL int reg added |
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2021-09-09 |
klehman | more sim class registers add |
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2021-09-08 |
Cesar Strauss | Monitor exceptions, re-decoding the instruction in... |
commit | commitdiff | tree |
2021-09-08 |
klehman | initial commit of sim state class |
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2021-09-08 |
Cesar Strauss | Monitor the exception input to PowerDecoder2 |
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2021-09-08 |
Cesar Strauss | Remove default argument for dict.get() |
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2021-09-07 |
Luke Kenneth... | fun fixing of get_core_hdl_regs, "yield from" |
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2021-09-07 |
Luke Kenneth... | move functions to above where they are called |
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next |