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riscv-tests.git
2013-10-17
Yunsup Lee
fix broken amoor_w rv64uv test
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2013-10-10
Christopher...
Merge branch 'master' of github.com:ucb-bar/riscv-tests
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2013-10-10
Christopher...
Benchmarks now run in user-mode.
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2013-10-10
Yunsup Lee
revamp hwacha tests
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2013-09-21
Andrew Waterman
Re-enable virtual memory tests
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2013-09-21
Andrew Waterman
New AUIPC semantics
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2013-09-15
Andrew Waterman
Don't emit vector instructions for now
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2013-09-11
Andrew Waterman
Add AMOXOR test
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2013-08-25
Andrew Waterman
Don't build vector benchmarks for now
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2013-08-25
Andrew Waterman
don't emit vvcfg for now
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2013-08-24
Andrew Waterman
Add autoconf-generated configure
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2013-08-24
Andrew Waterman
Reflect changes to ISA
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2013-08-24
Sebastien Mirolo
Merge pull request #1 from smirolo/configure
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2013-08-12
Sebastien Mirolo
Merge branch 'master' of git://github.com/ucb-bar/riscv...
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2013-07-26
Andrew Waterman
Remove JALR static hints
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2013-07-24
Sebastien Mirolo
feature: add autoconf
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2013-06-14
Henry Cook
removed bad mt test
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2013-06-13
Henry Cook
multithreading tests from 152 lab 5
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2013-06-10
Andrew Waterman
Don't disassemble zeros
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2013-05-16
Yunsup Lee
add failing multiply test
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2013-05-14
Yunsup Lee
change riscv-isa-run to spike
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2013-05-02
Andrew Waterman
use RVTEST_RV64UF macro for FPU tests
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2013-05-02
Andrew Waterman
pass all FP tests if FPU not present
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2013-04-30
Andrew Waterman
add first RV32 tests
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2013-04-30
Yunsup Lee
add benchmarks gitignore
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2013-04-30
Yunsup Lee
benchmarks initial commit
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2013-04-24
Yunsup Lee
add gitignore
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2013-04-24
Yunsup Lee
cleanup Makefiles in isa
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2013-04-24
Yunsup Lee
add missing RVTEST_CODE_END macros
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2013-04-24
Yunsup Lee
add more header information to test_macros
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2013-04-24
Yunsup Lee
change label names to avoid conflicts with test code
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2013-04-22
Yunsup Lee
get rid of RVTEST_PASS_NOFP
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2013-04-22
Yunsup Lee
initial commit
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