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soc.git
2021-12-11 Luke Kenneth... get FetchUnitInterface I-Cache test working (sort-of) commit | commitdiff | tree
2021-12-11 Luke Kenneth... comment out broken test commit | commitdiff | tree
2021-12-11 Luke Kenneth... whoops forgot to add pspec commit | commitdiff | tree
2021-12-11 Tobias Platentypo fix, add missing stop statement to _test_loadstore... commit | commitdiff | tree
2021-12-11 Tobias Platenadd loop with multiple instructions for testing commit | commitdiff | tree
2021-12-11 Tobias Platenadd skeleton for test_loadstore1_ifetch_multi() commit | commitdiff | tree
2021-12-11 Luke Kenneth... add start of test_loadstore1_ifetch_unit_interface() commit | commitdiff | tree
2021-12-11 Luke Kenneth... connect up I-Cache to FetchUnitInterface commit | commitdiff | tree
2021-12-11 Luke Kenneth... add new ConfigFetchUnit option "mmu_cache_wb" which... commit | commitdiff | tree
2021-12-10 Jacob Lifshayadd ternlogi to shift_rot formal test commit | commitdiff | tree
2021-12-10 Jacob Lifshayfix shift_rot formal proof commit | commitdiff | tree
2021-12-10 Jacob Lifshayadd formal_test_temp to .gitignore commit | commitdiff | tree
2021-12-10 Tobias Platenuse icache_read in one place commit | commitdiff | tree
2021-12-10 Tobias Platentest_loadstore1.py: begin code deduplication commit | commitdiff | tree
2021-12-09 Luke Kenneth... add some examination of the failed-fetched instruction commit | commitdiff | tree
2021-12-09 Luke Kenneth... add some debug string info to gtkwave commit | commitdiff | tree
2021-12-09 Tobias Platenimplement main part of test_loadstore1_ifetch_invalid() commit | commitdiff | tree
2021-12-09 Tobias Platencleanup test_loadstore1.py commit | commitdiff | tree
2021-12-09 Luke Kenneth... add I-Cache to FSM local variables commit | commitdiff | tree
2021-12-09 Luke Kenneth... wire fetch_failed from I-Cache to PowerDecoder2 commit | commitdiff | tree
2021-12-09 Luke Kenneth... make icache accessible to core, working back to TestIssuer commit | commitdiff | tree
2021-12-09 Luke Kenneth... include SPR.TB in SPR FU commit | commitdiff | tree
2021-12-09 Jacob Lifshayadd bitmanip tests commit | commitdiff | tree
2021-12-09 Jacob Lifshayadd CommonPipeSpec.__getattr__ to forward attributes... commit | commitdiff | tree
2021-12-09 Jacob Lifshayadd parent_pspec everywhere commit | commitdiff | tree
2021-12-09 Jacob Lifshaymake argv handling more flexible commit | commitdiff | tree
2021-12-09 Jacob Lifshayformat code commit | commitdiff | tree
2021-12-08 Luke Kenneth... got fed up of staring at magic constants in the MMU commit | commitdiff | tree
2021-12-08 Luke Kenneth... add special pagetable to ifetch_invalid with execute... commit | commitdiff | tree
2021-12-08 Luke Kenneth... do not try priv_mode on the instruction fetch (not... commit | commitdiff | tree
2021-12-08 Luke Kenneth... add an example pagetable where executable permission... commit | commitdiff | tree
2021-12-08 Tobias Platenbegin working on _test_loadstore1_ifetch_invalid()... commit | commitdiff | tree
2021-12-08 Tobias Platenmore work on test_loadstore1_ifetch_invalid() commit | commitdiff | tree
2021-12-08 Tobias PlatenMerge branch 'master' of ssh://git.libre-riscv.org... commit | commitdiff | tree
2021-12-08 Tobias Platenadd skeleton for test_loadstore1_ifetch_invalid() commit | commitdiff | tree
2021-12-08 Luke Kenneth... check that no exception occurs in the virtual-memory... commit | commitdiff | tree
2021-12-08 Luke Kenneth... add OP_FETCH_FAILED to MMU Function Unit commit | commitdiff | tree
2021-12-08 Luke Kenneth... make LoadStore1 intsr_fault a "captured flag" - strictl... commit | commitdiff | tree
2021-12-08 Luke Kenneth... remove MSR and add CIA to MMU Input Record commit | commitdiff | tree
2021-12-08 Luke Kenneth... add instr_fault to LoadStore1 FSM commit | commitdiff | tree
2021-12-08 Luke Kenneth... add new PortInterfaceBase external_busy() option commit | commitdiff | tree
2021-12-08 Jacob Lifshayadd comment about draft instructions commit | commitdiff | tree
2021-12-08 Jacob Lifshayaccount for Mock absurdities commit | commitdiff | tree
2021-12-07 Luke Kenneth... complete the i-cache fetch through the MMU, including... commit | commitdiff | tree
2021-12-07 Luke Kenneth... set separate "iside" signal in LoadStore1 to not confuse it commit | commitdiff | tree
2021-12-07 Luke Kenneth... start extending icache loadstore test commit | commitdiff | tree
2021-12-07 Luke Kenneth... whoops another serious error in the CacheTagArray commit | commitdiff | tree
2021-12-07 Luke Kenneth... add first i-cache fetch (non-virtual), no MMU lookup... commit | commitdiff | tree
2021-12-07 Luke Kenneth... code-comments commit | commitdiff | tree
2021-12-07 Luke Kenneth... add in I-Cache into LoadStore1 - presently unused ... commit | commitdiff | tree
2021-12-07 Luke Kenneth... add discussion links and bugreport commit | commitdiff | tree
2021-12-07 Luke Kenneth... invert mmureq statements commit | commitdiff | tree
2021-12-07 Luke Kenneth... submodule tidyup commit | commitdiff | tree
2021-12-07 Jacob Lifshaymake bitmanip operations conditional on pspec.draft_bit... commit | commitdiff | tree
2021-12-07 Jacob Lifshayformat code commit | commitdiff | tree
2021-12-07 Jacob Lifshaymove rotator mode assignments as requested by lkcl commit | commitdiff | tree
2021-12-07 Jacob Lifshayformat code commit | commitdiff | tree
2021-12-07 Luke Kenneth... tidyup, comments commit | commitdiff | tree
2021-12-07 Luke Kenneth... debug print commit | commitdiff | tree
2021-12-06 Luke Kenneth... another major bug, CacheTagArray valid was only 1 bit... commit | commitdiff | tree
2021-12-06 Luke Kenneth... tidyup: move hit_set to DCachePendingHit in dcache.py commit | commitdiff | tree
2021-12-06 Luke Kenneth... dcache.py tidyup commit | commitdiff | tree
2021-12-06 Luke Kenneth... rename dtlb to dtlb_valid and tidyup commit | commitdiff | tree
2021-12-06 Luke Kenneth... convert TLBArray to TLBValidArray commit | commitdiff | tree
2021-12-06 Luke Kenneth... convert DTLBUpdate to use a pair of Memorys commit | commitdiff | tree
2021-12-06 Luke Kenneth... more signals local to DTLBUpdate commit | commitdiff | tree
2021-12-06 Luke Kenneth... more signals local to DTLBUpdate commit | commitdiff | tree
2021-12-06 Luke Kenneth... update DTLBUpdate to reflect internal API now commit | commitdiff | tree
2021-12-06 Luke Kenneth... ooo nasty bug. used tlb_hit.way instead of tlb_hit... commit | commitdiff | tree
2021-12-06 Luke Kenneth... move DTLB Tags/Valids/PTEs into DTLBUpdate module commit | commitdiff | tree
2021-12-06 Luke Kenneth... start moving TLBArray into DTLBUpdate commit | commitdiff | tree
2021-12-06 Luke Kenneth... PLRUs were selecting an output index, only one selected commit | commitdiff | tree
2021-12-06 Luke Kenneth... repeated copies of read/write addr/sel to Cache SRAMs commit | commitdiff | tree
2021-12-06 Luke Kenneth... move bank of PLRUs to their own submodule in both dcach... commit | commitdiff | tree
2021-12-06 Luke Kenneth... code-comments commit | commitdiff | tree
2021-12-06 Luke Kenneth... use binary-to-unary encoders in dcache.py commit | commitdiff | tree
2021-12-06 Luke Kenneth... global (one) do_read signal in cache_rams dcache.py commit | commitdiff | tree
2021-12-06 Luke Kenneth... use one-hot binary-to-unary in dcache.py commit | commitdiff | tree
2021-12-06 Luke Kenneth... use i_in.req to gate hit_way via Decoder in icache.py commit | commitdiff | tree
2021-12-06 Luke Kenneth... use Decoder (binary-to-unary) in icache.py to deal... commit | commitdiff | tree
2021-12-05 Luke Kenneth... use unary encoding (one-hot) for replace_way hit_way... commit | commitdiff | tree
2021-12-05 Luke Kenneth... code-comments commit | commitdiff | tree
2021-12-05 Luke Kenneth... whitespace and minor cleanup of D-Cache commit | commitdiff | tree
2021-12-05 Luke Kenneth... more use of TLBHit Record in D-Cache commit | commitdiff | tree
2021-12-05 Luke Kenneth... correct tlb_hit_way and index sizes, use TLBHit Record... commit | commitdiff | tree
2021-12-05 Luke Kenneth... use TLBRecord in D-Cache for which TLB is selected commit | commitdiff | tree
2021-12-05 Luke Kenneth... split out TLBRecord, correct number of valid bits commit | commitdiff | tree
2021-12-05 Luke Kenneth... use Record in DCache for TLB commit | commitdiff | tree
2021-12-05 Luke Kenneth... use Record in D-Cache Cache Tags commit | commitdiff | tree
2021-12-05 Luke Kenneth... whitespace commit | commitdiff | tree
2021-12-05 Luke Kenneth... use Record for I-Cache Cache Tag/Valid commit | commitdiff | tree
2021-12-05 Luke Kenneth... whitespace commit | commitdiff | tree
2021-12-05 Luke Kenneth... use Record for ICache TLB commit | commitdiff | tree
2021-12-05 Luke Kenneth... sorting out test_mmu_dcache.py to use wb_get commit | commitdiff | tree
2021-12-05 Luke Kenneth... convert icache.py to standard wishbone Interface commit | commitdiff | tree
2021-12-05 Luke Kenneth... fake up wishbone stall signal in icache. commit | commitdiff | tree
2021-12-05 Luke Kenneth... fix icache row store issue commit | commitdiff | tree
2021-12-05 Luke Kenneth... using same tag/row functions as in dcache.py commit | commitdiff | tree
2021-12-05 Luke Kenneth... more signal sizes in icache.py commit | commitdiff | tree
2021-12-05 Luke Kenneth... incorrect Signal sizes in icache.py, commit | commitdiff | tree
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