2020-06-19 |
Luke Kenneth... | add true and floor div to SelectableInt |
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2020-06-19 |
Luke Kenneth... | add simulator test for divw |
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2020-06-19 |
Luke Kenneth... | do mix-in for test_sim.py so that jacob can write some... |
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2020-06-19 |
Luke Kenneth... | add TODO comments to upgrade L0CacheBuffer to a new... |
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2020-06-19 |
Luke Kenneth... | parameterise LoadStoreUnitInterface to be expandable |
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2020-06-18 |
Jacob Lifshay | div pipe completed except for tests |
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2020-06-18 |
Jacob Lifshay | finish code to calculate the 64-bit output of the div... |
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2020-06-18 |
Jacob Lifshay | actually remove todo comment for manually checking... |
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2020-06-18 |
Jacob Lifshay | Merge branch 'master' of ssh://git.libre-riscv.org... |
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2020-06-18 |
Jacob Lifshay | fix bug and manually check div overflow code against... |
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2020-06-18 |
Luke Kenneth... | enable general test cases in test_issuer |
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2020-06-18 |
Luke Kenneth... | got loop example operational by noting when PC fastreg... |
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2020-06-18 |
Luke Kenneth... | use different way to pass instructions to test_issuer... |
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2020-06-18 |
Luke Kenneth... | debugging test_issuer.py general test cases |
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2020-06-18 |
Luke Kenneth... | get instructions immediately from assembly code |
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2020-06-18 |
Luke Kenneth... | move test_sim.py unit tests to different class (split) |
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2020-06-18 |
Luke Kenneth... | slightly hacky way to keep an eye on the PC |
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2020-06-18 |
Luke Kenneth... | whoops generate core ilang not TestIssuer |
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2020-06-18 |
Luke Kenneth... | use while / exception in test_compunit loop |
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2020-06-18 |
Luke Kenneth... | investigating mtocrf/mtcrf issue |
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2020-06-18 |
Jacob Lifshay | working on adding rest of stage classes for div pipeline |
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2020-06-17 |
Luke Kenneth... | add bug reference to mtocrf/mtcrf name decoding |
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2020-06-17 |
Luke Kenneth... | decoding assembly instruction name, move to separate... |
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2020-06-17 |
Luke Kenneth... | getting sim instruction decoder to reproduce asm instru... |
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2020-06-17 |
Luke Kenneth... | update submodule |
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2020-06-17 |
Luke Kenneth... | add comment/assembly decode in power enums |
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2020-06-17 |
Luke Kenneth... | update test_sim.py to do a simple execution loop: decod... |
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2020-06-17 |
Luke Kenneth... | add loop example, required a bit of munging. |
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2020-06-17 |
Luke Kenneth... | get fu compunit test to use ISACaller instruction-memory |
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2020-06-17 |
Luke Kenneth... | got fed up of adding arguments to ISACaller / ISA,... |
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2020-06-17 |
Luke Kenneth... | split execute and setup of ISACaller instruction execution |
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2020-06-17 |
Luke Kenneth... | comment ISACaller setup |
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2020-06-17 |
Luke Kenneth... | start to add in independent execution into ISACaller |
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2020-06-17 |
Luke Kenneth... | add a fake program counter to ISACaller |
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2020-06-17 |
Luke Kenneth... | use an independent power decoder in ISACaller |
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2020-06-17 |
Luke Kenneth... | add "respect_pc" boolean to ISACaller |
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2020-06-17 |
Luke Kenneth... | add optional instruction memory |
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2020-06-17 |
Luke Kenneth... | split out TestIssuer into separate module |
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2020-06-17 |
Luke Kenneth... | remove unneeded yield |
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2020-06-17 |
Luke Kenneth... | enable all tests again in test_core.py and test_issuer.py |
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2020-06-17 |
Luke Kenneth... | got test_issuer FSM operating. bit of a hack |
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2020-06-17 |
Luke Kenneth... | debugging test_issuer, getting FSM working |
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2020-06-17 |
Luke Kenneth... | output to issuer_simulator.vcd |
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2020-06-16 |
Luke Kenneth... | add first version unit test for TestIssuer |
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2020-06-16 |
Luke Kenneth... | reduce instruction depth to 6 bits in TestIssuer |
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2020-06-16 |
Luke Kenneth... | move debug statements to check function |
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2020-06-16 |
Luke Kenneth... | hack LD/ST ad/st together, allow PC to be set externally |
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2020-06-16 |
Luke Kenneth... | move check regs in simple core to separate function |
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2020-06-16 |
Luke Kenneth... | move test core reg set up into separate function |
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2020-06-16 |
Luke Kenneth... | set up a TestIssuer class with a FSM for doing instruct... |
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2020-06-16 |
Luke Kenneth... | add ports to TestMemory |
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2020-06-16 |
Luke Kenneth... | add beginnings of TestIssuer class, to issue instructio... |
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2020-06-16 |
Luke Kenneth... | weird: adding TestMemory with no port causes nmigen... |
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2020-06-16 |
Luke Kenneth... | refer to signals directly in Test Core |
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2020-06-16 |
Luke Kenneth... | add test instruction memory SRAM |
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2020-06-16 |
Luke Kenneth... | update popcount docstring |
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2020-06-15 |
Luke Kenneth... | start trying to fill in some comments in Minerva L1... |
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2020-06-15 |
Luke Kenneth... | whitespace cleanup |
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2020-06-15 |
Luke Kenneth... | imports and syntax errors fixed (found test_cache.py) |
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2020-06-15 |
Luke Kenneth... | more whitespace |
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2020-06-15 |
Luke Kenneth... | more whitespace on minerva (no unit tests, so cannot... |
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2020-06-15 |
Luke Kenneth... | whitespace cleanup, remove minerva DataSelector class |
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2020-06-15 |
Luke Kenneth... | have to set up addr/st rel-go link before setting up... |
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2020-06-15 |
Luke Kenneth... | add in memory setup/check but disable LDST Unit Tests... |
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2020-06-15 |
Luke Kenneth... | move setup/check memory into helper functions for use... |
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2020-06-15 |
Luke Kenneth... | whoops LDSTCompUnit was identified as a Function.ALU... |
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2020-06-15 |
Luke Kenneth... | add in TstL0CacheBuffer but disable temporarily |
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2020-06-14 |
Luke Kenneth... | add optional LDSTFunctionUnit to compunits |
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2020-06-14 |
Luke Kenneth... | unit tests showing byte-reverse works |
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2020-06-14 |
Luke Kenneth... | add sim-qemu test for byte-reversed LD/ST |
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2020-06-14 |
Luke Kenneth... | add in byte-reverse from op PowerDecode2 field |
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2020-06-14 |
Luke Kenneth... | error in address width (truncated) in setting up L0Cach... |
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2020-06-14 |
Luke Kenneth... | error in naming that ended up in gtkwave from a proxy |
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2020-06-14 |
Luke Kenneth... | add another LD/ST example to qemu-sim test, |
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2020-06-14 |
Luke Kenneth... | add byte-reversal on LD and ST in L0CacheBuffer |
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2020-06-14 |
Luke Kenneth... | reasonably certain that the careful and slow use of... |
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2020-06-13 |
Cesar Strauss | Wait for all active rel signals to be high, and only... |
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2020-06-12 |
Luke Kenneth... | first cut at qemu memory dump and compare |
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2020-06-12 |
Luke Kenneth... | note possible BE/LE mode needed for memory reads/writes |
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2020-06-12 |
Luke Kenneth... | update ld/st test to see what is going on |
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2020-06-12 |
Luke Kenneth... | tracking down what looks like an error in the Simulator... |
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2020-06-12 |
Luke Kenneth... | debug printout of sim and hardware memory, shows mismat... |
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2020-06-12 |
Luke Kenneth... | use ALUHelpers in LDSTCompUnit test |
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2020-06-11 |
Luke Kenneth... | some ugly hacks that get LD/ST immediate working |
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2020-06-11 |
Luke Kenneth... | even more complexity in CompALUMulti, to deal with... |
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2020-06-11 |
Luke Kenneth... | must distinguish between rd/write xer_ca sim helpers |
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2020-06-11 |
Luke Kenneth... | fixing get_rd_sim_xer_ca, has to only read carry if... |
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2020-06-11 |
Luke Kenneth... | yield needed for unit tests to work (has to go) |
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2020-06-11 |
Luke Kenneth... | read and write version of get_sim_xer_ca are different |
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2020-06-11 |
Luke Kenneth... | use ALUHelpers in shift_rot |
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2020-06-11 |
Luke Kenneth... | add fast spr1/2 sim ALUHelpers |
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2020-06-11 |
Luke Kenneth... | rename get_sim_cr_a to get_wr_sim_cr_a for now |
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2020-06-10 |
Luke Kenneth... | move Decode2ToExecute1Type to separate module |
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2020-06-10 |
Luke Kenneth... | whitespace |
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2020-06-10 |
Michael Nolan | modify qemu.py to set qemu's cr to 0 |
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2020-06-10 |
Luke Kenneth... | link ST.go directly to ST.rel |
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2020-06-10 |
Luke Kenneth... | rename unit test function in ld/st compalu_multi |
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2020-06-10 |
Luke Kenneth... | hmmm very confused about LD/ST CompUnit unit test |
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2020-06-10 |
Luke Kenneth... | wrong data structure being imported, duplicate CompLDST... |
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2020-06-10 |
Luke Kenneth... | remove old code |
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next |