soc.git
2020-06-19 Luke Kenneth... add true and floor div to SelectableInt
2020-06-19 Luke Kenneth... add simulator test for divw
2020-06-19 Luke Kenneth... do mix-in for test_sim.py so that jacob can write some...
2020-06-19 Luke Kenneth... add TODO comments to upgrade L0CacheBuffer to a new...
2020-06-19 Luke Kenneth... parameterise LoadStoreUnitInterface to be expandable
2020-06-18 Jacob Lifshaydiv pipe completed except for tests
2020-06-18 Jacob Lifshayfinish code to calculate the 64-bit output of the div...
2020-06-18 Jacob Lifshayactually remove todo comment for manually checking...
2020-06-18 Jacob LifshayMerge branch 'master' of ssh://git.libre-riscv.org...
2020-06-18 Jacob Lifshayfix bug and manually check div overflow code against...
2020-06-18 Luke Kenneth... enable general test cases in test_issuer
2020-06-18 Luke Kenneth... got loop example operational by noting when PC fastreg...
2020-06-18 Luke Kenneth... use different way to pass instructions to test_issuer...
2020-06-18 Luke Kenneth... debugging test_issuer.py general test cases
2020-06-18 Luke Kenneth... get instructions immediately from assembly code
2020-06-18 Luke Kenneth... move test_sim.py unit tests to different class (split)
2020-06-18 Luke Kenneth... slightly hacky way to keep an eye on the PC
2020-06-18 Luke Kenneth... whoops generate core ilang not TestIssuer
2020-06-18 Luke Kenneth... use while / exception in test_compunit loop
2020-06-18 Luke Kenneth... investigating mtocrf/mtcrf issue
2020-06-18 Jacob Lifshayworking on adding rest of stage classes for div pipeline
2020-06-17 Luke Kenneth... add bug reference to mtocrf/mtcrf name decoding
2020-06-17 Luke Kenneth... decoding assembly instruction name, move to separate...
2020-06-17 Luke Kenneth... getting sim instruction decoder to reproduce asm instru...
2020-06-17 Luke Kenneth... update submodule
2020-06-17 Luke Kenneth... add comment/assembly decode in power enums
2020-06-17 Luke Kenneth... update test_sim.py to do a simple execution loop: decod...
2020-06-17 Luke Kenneth... add loop example, required a bit of munging.
2020-06-17 Luke Kenneth... get fu compunit test to use ISACaller instruction-memory
2020-06-17 Luke Kenneth... got fed up of adding arguments to ISACaller / ISA,...
2020-06-17 Luke Kenneth... split execute and setup of ISACaller instruction execution
2020-06-17 Luke Kenneth... comment ISACaller setup
2020-06-17 Luke Kenneth... start to add in independent execution into ISACaller
2020-06-17 Luke Kenneth... add a fake program counter to ISACaller
2020-06-17 Luke Kenneth... use an independent power decoder in ISACaller
2020-06-17 Luke Kenneth... add "respect_pc" boolean to ISACaller
2020-06-17 Luke Kenneth... add optional instruction memory
2020-06-17 Luke Kenneth... split out TestIssuer into separate module
2020-06-17 Luke Kenneth... remove unneeded yield
2020-06-17 Luke Kenneth... enable all tests again in test_core.py and test_issuer.py
2020-06-17 Luke Kenneth... got test_issuer FSM operating. bit of a hack
2020-06-17 Luke Kenneth... debugging test_issuer, getting FSM working
2020-06-17 Luke Kenneth... output to issuer_simulator.vcd
2020-06-16 Luke Kenneth... add first version unit test for TestIssuer
2020-06-16 Luke Kenneth... reduce instruction depth to 6 bits in TestIssuer
2020-06-16 Luke Kenneth... move debug statements to check function
2020-06-16 Luke Kenneth... hack LD/ST ad/st together, allow PC to be set externally
2020-06-16 Luke Kenneth... move check regs in simple core to separate function
2020-06-16 Luke Kenneth... move test core reg set up into separate function
2020-06-16 Luke Kenneth... set up a TestIssuer class with a FSM for doing instruct...
2020-06-16 Luke Kenneth... add ports to TestMemory
2020-06-16 Luke Kenneth... add beginnings of TestIssuer class, to issue instructio...
2020-06-16 Luke Kenneth... weird: adding TestMemory with no port causes nmigen...
2020-06-16 Luke Kenneth... refer to signals directly in Test Core
2020-06-16 Luke Kenneth... add test instruction memory SRAM
2020-06-16 Luke Kenneth... update popcount docstring
2020-06-15 Luke Kenneth... start trying to fill in some comments in Minerva L1...
2020-06-15 Luke Kenneth... whitespace cleanup
2020-06-15 Luke Kenneth... imports and syntax errors fixed (found test_cache.py)
2020-06-15 Luke Kenneth... more whitespace
2020-06-15 Luke Kenneth... more whitespace on minerva (no unit tests, so cannot...
2020-06-15 Luke Kenneth... whitespace cleanup, remove minerva DataSelector class
2020-06-15 Luke Kenneth... have to set up addr/st rel-go link before setting up...
2020-06-15 Luke Kenneth... add in memory setup/check but disable LDST Unit Tests...
2020-06-15 Luke Kenneth... move setup/check memory into helper functions for use...
2020-06-15 Luke Kenneth... whoops LDSTCompUnit was identified as a Function.ALU...
2020-06-15 Luke Kenneth... add in TstL0CacheBuffer but disable temporarily
2020-06-14 Luke Kenneth... add optional LDSTFunctionUnit to compunits
2020-06-14 Luke Kenneth... unit tests showing byte-reverse works
2020-06-14 Luke Kenneth... add sim-qemu test for byte-reversed LD/ST
2020-06-14 Luke Kenneth... add in byte-reverse from op PowerDecode2 field
2020-06-14 Luke Kenneth... error in address width (truncated) in setting up L0Cach...
2020-06-14 Luke Kenneth... error in naming that ended up in gtkwave from a proxy
2020-06-14 Luke Kenneth... add another LD/ST example to qemu-sim test,
2020-06-14 Luke Kenneth... add byte-reversal on LD and ST in L0CacheBuffer
2020-06-14 Luke Kenneth... reasonably certain that the careful and slow use of...
2020-06-13 Cesar StraussWait for all active rel signals to be high, and only...
2020-06-12 Luke Kenneth... first cut at qemu memory dump and compare
2020-06-12 Luke Kenneth... note possible BE/LE mode needed for memory reads/writes
2020-06-12 Luke Kenneth... update ld/st test to see what is going on
2020-06-12 Luke Kenneth... tracking down what looks like an error in the Simulator...
2020-06-12 Luke Kenneth... debug printout of sim and hardware memory, shows mismat...
2020-06-12 Luke Kenneth... use ALUHelpers in LDSTCompUnit test
2020-06-11 Luke Kenneth... some ugly hacks that get LD/ST immediate working
2020-06-11 Luke Kenneth... even more complexity in CompALUMulti, to deal with...
2020-06-11 Luke Kenneth... must distinguish between rd/write xer_ca sim helpers
2020-06-11 Luke Kenneth... fixing get_rd_sim_xer_ca, has to only read carry if...
2020-06-11 Luke Kenneth... yield needed for unit tests to work (has to go)
2020-06-11 Luke Kenneth... read and write version of get_sim_xer_ca are different
2020-06-11 Luke Kenneth... use ALUHelpers in shift_rot
2020-06-11 Luke Kenneth... add fast spr1/2 sim ALUHelpers
2020-06-11 Luke Kenneth... rename get_sim_cr_a to get_wr_sim_cr_a for now
2020-06-10 Luke Kenneth... move Decode2ToExecute1Type to separate module
2020-06-10 Luke Kenneth... whitespace
2020-06-10 Michael Nolanmodify qemu.py to set qemu's cr to 0
2020-06-10 Luke Kenneth... link ST.go directly to ST.rel
2020-06-10 Luke Kenneth... rename unit test function in ld/st compalu_multi
2020-06-10 Luke Kenneth... hmmm very confused about LD/ST CompUnit unit test
2020-06-10 Luke Kenneth... wrong data structure being imported, duplicate CompLDST...
2020-06-10 Luke Kenneth... remove old code
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