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soc-cocotb-sim.git
2021-04-16
Luke Kenneth...
upload 32-bit wishbone data not 64-bit test data
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2021-04-16
Luke Kenneth...
corrections to wishbone test
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2021-04-16
Luke Kenneth...
corrections to wishbone test
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2021-04-14
Luke Kenneth...
add test boundary scan hard-coded test
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2021-04-14
Luke Kenneth...
try chip_r adder test (works)
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2021-04-14
Luke Kenneth...
remove async, use yield
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2021-04-13
Luke Kenneth...
get jtag tests running on basic adder
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2021-04-13
Luke Kenneth...
convert wb test to async
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2021-04-13
Luke Kenneth...
resolving pin names (to litex ls180)
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2021-04-13
Luke Kenneth...
more post-processing of vst files
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2021-04-12
Luke Kenneth...
more vst corrections, for chip definition
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2021-04-11
Luke Kenneth...
sorting out cts (post p&r)
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2021-04-10
Luke Kenneth...
adding edited versions of chip/corona
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2021-04-10
Luke Kenneth...
use vcd for wave output not ghw
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2021-04-10
Luke Kenneth...
sigh, no wrap - use direct
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2021-04-10
Luke Kenneth...
add ghdl wishbone basic test
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2021-04-07
Luke Kenneth...
correct iverilog script errors
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2021-04-07
Luke Kenneth...
add verilator cocotb runner
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2021-04-06
Luke Kenneth...
remove wb test from test.py
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2021-04-06
Luke Kenneth...
add test wishbone (separate from test.py)
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2021-04-06
Staf Verhaegen
Function is a generator.
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2021-04-06
Staf Verhaegen
Fix pre-layout simulation with 4K SRAM blocks.
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2021-04-06
Staf Verhaegen
Add sim models for SRAM block.
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2021-04-06
Luke Kenneth...
add wishbone sim gtk test script
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2021-04-06
Luke Kenneth...
add comments
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2021-04-06
Luke Kenneth...
fix wishbone jtag test to run: results not correct yet
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2021-04-06
Luke Kenneth...
add first cut at wishbone jtag unit test
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2021-04-06
Luke Kenneth...
whitespace
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2021-04-04
Luke Kenneth...
80 char linewrap
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2021-04-04
Staf Verhaegen
Test different combinations of i, o, oe for InTriOut
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2021-04-03
Staf Verhaegen
Support running tb on test_issuer subblock.
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2021-04-03
Staf Verhaegen
Update gitignore.
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2021-04-02
Staf Verhaegen
Full boundary scan.
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2021-04-02
Staf Verhaegen
Typo.
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2021-04-02
Staf Verhaegen
Add helper class JTAGPin
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2021-04-02
Staf Verhaegen
First version of boundary scan test bench.
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2021-04-02
Staf Verhaegen
pre_pnr/test.py: Fix idcode SVF test name.
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2021-04-02
Staf Verhaegen
pre_pnr/test.py: Reset JTAG before executing SVF.
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2021-04-01
Luke Kenneth...
TWI enabled in boundary scan
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2021-04-01
Luke Kenneth...
show how to get the boundary scan information from...
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2021-04-01
Luke Kenneth...
add one more up to path
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2021-04-01
Luke Kenneth...
move pre_pnr cocotb sim to soc-cocotb-sim directory
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2021-04-01
Luke Kenneth...
move post-pnr to new subdirectory
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2021-04-01
Luke Kenneth...
update README
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2021-04-01
Luke Kenneth...
sort out Makefile for building
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2021-04-01
Luke Kenneth...
ha! got IDCODE and reset test to work
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2021-04-01
Luke Kenneth...
match ir_width with experiment10 and do not overwrite...
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2021-04-01
Luke Kenneth...
connect up jtag corona pads
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2021-04-01
Luke Kenneth...
add cocotb testbench
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2021-04-01
Luke Kenneth...
remove not-needed thing from cocotb Makefile
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2021-04-01
Luke Kenneth...
add first cocotb Makefile
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2021-04-01
Luke Kenneth...
add "make corona" option
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2021-04-01
Luke Kenneth...
compile all libraries, use --std=08 it passes
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2021-04-01
Luke Kenneth...
add vst corrections program
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2021-04-01
Luke Kenneth...
do niolib conversion as well as nsxlib
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2021-03-31
Luke Kenneth...
build vhd objects
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2021-03-31
Luke Kenneth...
add conversion from alliance vbe to vst using coriolis2...
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2021-03-31
Luke Kenneth...
start on Makefile, add notes, add alliance-check-toolki...
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2021-03-29
Luke Kenneth...
add vst to .gitignore so that generated files do not...
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2021-03-29
Luke Kenneth...
add initial empty README.txt in ls180 directory
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