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soc.git
2021-03-22
Cesar Strauss
Add traces for the new FSM and integer predicate decoding
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2021-03-22
Cesar Strauss
Decode and fetch integer predicate registers
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2021-03-21
Cesar Strauss
Fix typo
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2021-03-21
Cesar Strauss
Add unique name to decoded predication signals
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2021-03-21
Cesar Strauss
Revert removal of *.value from Enums
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2021-03-21
Cesar Strauss
Fix syntax
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2021-03-21
Luke Kenneth...
more TODO comments
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2021-03-21
Luke Kenneth...
add for-loop pseudocode for CR predicate mask reading
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2021-03-21
Luke Kenneth...
code comments in TestIssuer
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2021-03-21
Luke Kenneth...
adjust syntax of SVP64 predicate test cas
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2021-03-21
Luke Kenneth...
naah. back to "sv." syntax for SVP64 assembly
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2021-03-21
Cesar Strauss
Start work on the predicate fetch FSM
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2021-03-21
Cesar Strauss
Add predication test case, initially disabled
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2021-03-21
Luke Kenneth...
add override for build commands powerpc64-linux-gnu...
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2021-03-21
Luke Kenneth...
enable -mregnames in assembly syntax for unit tests
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2021-03-20
Luke Kenneth...
more pseudocode in TestIssuer
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2021-03-20
Luke Kenneth...
move radixmmu to unit test format
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2021-03-20
Luke Kenneth...
add harmless code and commented-out pseudocode for...
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2021-03-20
Luke Kenneth...
sort out predicate zeroing in ISACaller
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2021-03-20
Luke Kenneth...
attempting to add src/dest-zeroing to ISACaller
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2021-03-19
Luke Kenneth...
more comments for TestIssuer when adding predication
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2021-03-19
Tobias Platen
testcase for _get_pgtable_addr
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2021-03-19
Luke Kenneth...
decode predicate src/dest zeroing in SVP64RMModeDecode
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2021-03-19
Luke Kenneth...
comments for TestIssuer get_predint and get_predcr
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2021-03-19
Luke Kenneth...
add more pieces of predication reading puzzle to TestIssuer
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2021-03-19
Luke Kenneth...
cleanup TestIssuer (comments)
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2021-03-19
Luke Kenneth...
spelling
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2021-03-19
Luke Kenneth...
code-shuffle in TestIssuer, split out setting up periph...
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2021-03-19
Luke Kenneth...
move duplicated code to a function in TestIssuer
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2021-03-18
Luke Kenneth...
more hint/comments
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2021-03-18
Luke Kenneth...
comments / code-shuffle
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2021-03-18
Luke Kenneth...
update TestIssuer comments
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2021-03-18
Luke Kenneth...
add comments on most likely place to put predicate...
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2021-03-18
Luke Kenneth...
comments TestIssuer, add a stub FSM
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2021-03-18
Luke Kenneth...
add MSR PR read in RADIXMMU ISACaller
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2021-03-18
Luke Kenneth...
re-add auto-generated file simplev.py to gitignore
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2021-03-18
Jacob Lifshay
re-add nmigen-type-annotations with libre-soc url
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2021-03-18
Luke Kenneth...
experiment in radixmmu with returning addr_next (and...
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2021-03-18
Luke Kenneth...
add sv_out2 to PowerDecode and PowerDecoder2
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2021-03-18
Luke Kenneth...
cross-reference to bug #619
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2021-03-18
Luke Kenneth...
add auto-generation of out2 column in SVP64RM
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2021-03-18
Luke Kenneth...
remove nmigen-type-annotations temporarily
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2021-03-18
Luke Kenneth...
remove nmigen-type-annotations temporarily
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2021-03-18
Luke Kenneth...
add option to move RS in CSV file reading, for compatib...
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2021-03-17
Luke Kenneth...
correct comments
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2021-03-17
Luke Kenneth...
re-enable SVP64 ISACaller predicate tests
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2021-03-17
Luke Kenneth...
add ascii graphic for extsw svp64 operation
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2021-03-17
Luke Kenneth...
add more explanatory comments
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2021-03-17
Luke Kenneth...
add twin-predicated extsw SVP64 ISACaller unit test
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2021-03-17
Luke Kenneth...
add SVP64 dststep incrementing in PowerDecoder2, Testis...
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2021-03-17
Luke Kenneth...
add CR-based predication to ISACaller
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2021-03-17
Tobias Platen
cleanup raduxmmu._walk_tree
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2021-03-17
Tobias Platen
create iterative mmu lookup loop
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2021-03-17
Luke Kenneth...
add SVP64 INT-style predication to ISACaller
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2021-03-17
Luke Kenneth...
add predication SVP64 unit test
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2021-03-17
Luke Kenneth...
add predication read ports (CR and INT)
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2021-03-17
Luke Kenneth...
whoops shift has to be done at same bitwidth
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2021-03-17
Luke Kenneth...
split out new_lookup function
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2021-03-17
Luke Kenneth...
link up SVP64 RM Mode decoding into PowerDecoder2
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2021-03-17
Luke Kenneth...
add priv and mode to RADIXMMU
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2021-03-17
Luke Kenneth...
add instr_fetch mode to ISACaller Mem and RADIXMMU
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2021-03-17
Luke Kenneth...
whitespace
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2021-03-17
Luke Kenneth...
add in SVP64 RM Mode decoder
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2021-03-16
Tobias Platen
radixmmu: detect badtree
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2021-03-16
Tobias Platen
add valid, leaf to loop
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2021-03-16
Cesar Strauss
Use symbolic values for subfields and bits
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2021-03-16
Cesar Strauss
Add subfield and bit definitions for the SVP64 RM mode...
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2021-03-16
Cesar Strauss
Define and initialise the mode variable, to be used...
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2021-03-16
Cesar Strauss
Rename class so it does not clash with the enum
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2021-03-15
Cesar Strauss
Fix import
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2021-03-15
Tobias Platen
add rpte bitfields valid and leaf
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2021-03-14
Luke Kenneth...
remove "sv." and replace with "sv" in all SVP64Asm
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2021-03-14
Luke Kenneth...
remove "sv." and replace with "sv" in all SVP64Asm
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2021-03-14
Cesar Strauss
Activate the VL==0 loop with any SVP64 prefix whatsoever
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2021-03-13
Luke Kenneth...
add setvl unit test assertions, add 2nd test
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2021-03-13
Luke Kenneth...
get first revision setvl operational in ISACaller
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2021-03-13
Luke Kenneth...
add setvl-to-long converter in SVP64Asm (sigh)
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2021-03-13
Luke Kenneth...
add setvl unit test
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2021-03-13
Luke Kenneth...
update submodule to include simplev setvl
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2021-03-13
Luke Kenneth...
include SVSTATE in namespace, passing to ISACaller
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2021-03-12
Jacob Lifshay
update submodule
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2021-03-12
Jacob Lifshay
add setvl to decoder
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2021-03-12
Jacob Lifshay
autoformat code
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2021-03-12
Luke Kenneth...
add OP_SETVL to MicrOp in power_enums.py
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2021-03-12
Luke Kenneth...
add ability to set and distinguish RT=0 (RT_OR_ZERO...
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2021-03-12
Luke Kenneth...
use PowerDecoder2.loop_continue instead of no_out_vec
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2021-03-12
Luke Kenneth...
remove old code
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2021-03-12
Luke Kenneth...
remove old code
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2021-03-12
Luke Kenneth...
remove old code
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2021-03-12
Luke Kenneth...
add more sophisticated checking of whether SVP64 loop...
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2021-03-12
Luke Kenneth...
**FOR NOW** LD/ST relies on detection of twin-predicati...
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2021-03-12
Luke Kenneth...
decoding of svp64 reg by name has to occur after immedi...
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2021-03-12
Jacob Lifshay
add forgotten PO (primary opcode) field to DecodeFields
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2021-03-11
Cesar Strauss
Bring a few test cases from test_caller_64.py
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2021-03-11
Cesar Strauss
Test case for two successive SV instructions
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2021-03-11
Luke Kenneth...
add link of RA_OR_ZERO SVP64 detection
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2021-03-11
Luke Kenneth...
add detection of whether *full* 7-bit of RA is zero...
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2021-03-11
Luke Kenneth...
add in SVP64 LD/ST basic test for ISACaller
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2021-03-11
Luke Kenneth...
whoops sort out when svstate not active in ISACaller
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2021-03-11
Luke Kenneth...
whoops PIDR is defined as 32-bits in SPRs.csv (and...
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