soc.git
2021-05-01 Luke Kenneth... store data in microwatt dcache goes in one cycle AFTER...
2021-05-01 Luke Kenneth... dcache store test: data goes in one cycle AFTER valid...
2021-05-01 Luke Kenneth... only do dcache lookup for now
2021-05-01 Cesar StraussAdd GTKWave documents to each DCache unit test
2021-05-01 Luke Kenneth... add LD/ST cases to MMU, which should all still work
2021-05-01 Luke Kenneth... add MMUTestCaseROM
2021-05-01 Luke Kenneth... whitespace
2021-05-01 Luke Kenneth... use new AllFunctionUnits.get_fu function
2021-05-01 Luke Kenneth... use SPRreduced to match PowerDecoder2
2021-05-01 Luke Kenneth... missing self.
2021-05-01 Luke Kenneth... resolve DriverConflict in TstL0CacheBuffer, really...
2021-04-30 Luke Kenneth... debug and stop on mmu test_pipe_caller.py
2021-04-30 Luke Kenneth... comments on dcache-to-mmu link
2021-04-30 Luke Kenneth... add a TestSRAM variant of LoadStore1, for being able...
2021-04-30 Luke Kenneth... add basic test_issuer_mmu.py
2021-04-30 Luke Kenneth... add option to use new mmu_cache_wb ConfigMemoryPortInte...
2021-04-30 Luke Kenneth... hook up dcache wb_in/out to PortInterfaceBase Wishbone...
2021-04-30 Luke Kenneth... sort out spblock 4k sram cell instance name to match...
2021-04-30 Luke Kenneth... https://bugs.libre-soc.org/show_bug.cgi?id=635
2021-04-30 Luke Kenneth... better reporting on gpr comparisons
2021-04-30 Luke Kenneth... set up LoadStore1 in ConfigMemoryPortInterface and...
2021-04-29 Luke Kenneth... comment out adding mmu and dcache to pspec in MMU FSM
2021-04-29 Luke Kenneth... move dcache into Loadstore1
2021-04-27 Luke Kenneth... add option to disable bus forwarding on SPRs and FAST...
2021-04-27 Luke Kenneth... add option to enable/disable bus forwarding mode on...
2021-04-27 Luke Kenneth... return read data out from Loadstore1 only when valid
2021-04-26 Luke Kenneth... hook up MSR into MMU (TODO, use a lot less bits)
2021-04-26 Luke Kenneth... simple regression dcache test was faulty. wishbone...
2021-04-26 Luke Kenneth... comment read ack in sram
2021-04-26 Luke Kenneth... incorrect indentation in dcache rams
2021-04-26 Luke Kenneth... simplify dcache test
2021-04-25 Luke Kenneth... spelling mistake
2021-04-25 Luke Kenneth... remove RegStage1.real_adr temporary from dcache
2021-04-25 Luke Kenneth... do not overwrite parameter ra in dcache
2021-04-25 Luke Kenneth... comment out dcache_store from test, not the problem
2021-04-25 Luke Kenneth... remove unneeded code
2021-04-25 Luke Kenneth... read req in wb_in.stall, dcache
2021-04-25 Cesar StraussShift-out skipped mask bits for both crpred and intpred
2021-04-25 Luke Kenneth... add single regression test for dcache
2021-04-25 Luke Kenneth... add TODO comment in dcache
2021-04-25 Luke Kenneth... move Signals in dcache to relevant context
2021-04-25 Luke Kenneth... dcache Elif used where If should have been
2021-04-25 Luke Kenneth... whoops should be cyc & ~ack
2021-04-25 Luke Kenneth... hard-code dcache stall signal to non-pipelined mode
2021-04-24 Luke Kenneth... increase memory size in dcache test
2021-04-24 Luke Kenneth... increase size of random dcache testing by 10
2021-04-24 Luke Kenneth... fix errors in dcache unit test
2021-04-24 Luke Kenneth... whitespace
2021-04-24 Luke Kenneth... add additional external libre-soc sphinx references...
2021-04-24 Luke Kenneth... add additional external libre-soc sphinx references
2021-04-24 Luke Kenneth... remove code moved to openpower-isa repo
2021-04-23 Luke Kenneth... add comments on TestIssuer TestRunner
2021-04-23 Luke Kenneth... comment tests back in
2021-04-23 Luke Kenneth... fix import error
2021-04-23 Luke Kenneth... error in setting fast regs test values
2021-04-23 Luke Kenneth... import from openpower.tests
2021-04-23 Luke Kenneth... whitespace
2021-04-23 Luke Kenneth... move logical tests to openpower.test
2021-04-23 Luke Kenneth... add trap test cases
2021-04-23 Luke Kenneth... move SPR tests to openpower.test
2021-04-23 Luke Kenneth... move branch test cases to openpower.test
2021-04-23 Luke Kenneth... move LDST tests to openpower.test
2021-04-23 Luke Kenneth... move mul tests to openpower.test
2021-04-23 Luke Kenneth... move div tests to openpower.test
2021-04-23 Luke Kenneth... move div tests to openpower.test
2021-04-23 Luke Kenneth... move ALU test cases to openpower.test
2021-04-23 Luke Kenneth... move MMU Testcase to openpower.test
2021-04-23 Luke Kenneth... move CR test cases to openpower.test
2021-04-23 Luke Kenneth... move shiftrot test cases to openpower.test
2021-04-23 Luke Kenneth... import from openpower.endian
2021-04-23 Luke Kenneth... use openpower.test.common
2021-04-23 Luke Kenneth... remove openpower-isa submodule
2021-04-23 Luke Kenneth... submodule update, can probably delete it though, now
2021-04-23 Luke Kenneth... move more files to openpower-isa
2021-04-23 Luke Kenneth... move to import from openpower-isa for reg enums
2021-04-23 Luke Kenneth... svanalysis and pywriter now command-line scripts
2021-04-23 Luke Kenneth... removed submodule
2021-04-23 Luke Kenneth... remove pseudo, moved to openpower-isa
2021-04-23 Luke Kenneth... remove simulator directory, moved to openpower-isa
2021-04-23 Luke Kenneth... more openpower-isa conversion
2021-04-23 Luke Kenneth... correct migration of openpower-isa
2021-04-23 Luke Kenneth... more openpower import conversion
2021-04-23 Luke Kenneth... more openpower import conversion
2021-04-23 Luke Kenneth... move over to from openpower imports
2021-04-23 Luke Kenneth... move over to openpower-isa repo
2021-04-23 Luke Kenneth... move over to openpower-isa
2021-04-23 Luke Kenneth... moving more over to openpower-isa repo
2021-04-23 Luke Kenneth... removing more as moved over to openpower-isa
2021-04-23 Luke Kenneth... submodule update
2021-04-22 Luke Kenneth... add debugging and buffering to CacheRam
2021-04-22 Luke Kenneth... whitespace
2021-04-22 Luke Kenneth... r1.end_row_ix off-by-one in dcache
2021-04-22 Luke Kenneth... sync missing in dcache
2021-04-22 Luke Kenneth... dcache.py code-comments
2021-04-22 Luke Kenneth... cleanup dcache
2021-04-22 Luke Kenneth... error using sync, should have been comb
2021-04-22 Cesar StraussImplement CR predication
2021-04-21 Cesar StraussCR sub-fields are stored in MSB0 order
2021-04-21 Luke Kenneth... experimenting with dcache
2021-04-21 Tobias Platentestcase: pass PRTBL to mmu
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