git.libre-soc.org Git - soc-cocotb-sim.git/summary

2021-06-05	Luke Kenneth...	use git submodule soclayout for source files, rather... master	commit \| commitdiff \| tree
2021-06-05	Luke Kenneth...	disallow adding verilog files	commit \| commitdiff \| tree
2021-06-05	Luke Kenneth...	sort out build of chip/corona using experiments10_verilog	commit \| commitdiff \| tree
2021-06-04	Staf Verhaegen	Use cocotb test on ls180/experiments9 with reconnected...	commit \| commitdiff \| tree
2021-04-17	Luke Kenneth...	add verilator post-pnr cocotb sim	commit \| commitdiff \| tree
2021-04-17	Luke Kenneth...	add chip conversion from ghdl to verilog	commit \| commitdiff \| tree
2021-04-17	Luke Kenneth...	fix iovdd/iovss in-to-std_logic conversion	commit \| commitdiff \| tree
2021-04-16	Luke Kenneth...	get pre-coriolis2 verilator (wishbone) functional	commit \| commitdiff \| tree
2021-04-16	Luke Kenneth...	upload 32-bit wishbone data not 64-bit test data	commit \| commitdiff \| tree
2021-04-16	Luke Kenneth...	corrections to wishbone test	commit \| commitdiff \| tree
2021-04-16	Luke Kenneth...	corrections to wishbone test	commit \| commitdiff \| tree
2021-04-14	Luke Kenneth...	add test boundary scan hard-coded test	commit \| commitdiff \| tree
2021-04-14	Luke Kenneth...	try chip_r adder test (works)	commit \| commitdiff \| tree
2021-04-14	Luke Kenneth...	remove async, use yield	commit \| commitdiff \| tree
2021-04-13	Luke Kenneth...	get jtag tests running on basic adder	commit \| commitdiff \| tree
2021-04-13	Luke Kenneth...	convert wb test to async	commit \| commitdiff \| tree
...

3 years ago