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aaagh found bug in litex setup, 64 bit WB bus was truncated
[soclayout.git] / experiments11 / coriolis2 /
drwxr-xr-x   ..
-rw-r--r-- 0 __init__.py blob | history | raw
-rw-r--r-- 243 katana.py blob | history | raw
-rw-r--r-- 1508 settings.py blob | history | raw