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[soc-cocotb-sim.git] / ls180 / experiment9_recon /

drwxr-xr-x		..
-rw-r--r--	10	.gitignore	blob \| history \| raw
-rw-r--r--	392	Makefile	blob \| history \| raw
lrwxrwxrwx	21	idcode.svf -> ../pre_pnr/idcode.svf	blob \| history \| raw
-rwxr-xr-x	587	run_iverilog_ls180.sh	blob \| history \| raw
lrwxrwxrwx	18	test.py -> ../pre_pnr/test.py	blob \| history \| raw