Add extra bits (carry, overflow, etc) to input and output structs
[soc.git] / src / soc / alu /
drwxr-xr-x   ..
-rw-r--r-- 2899 alu_input_record.py
drwxr-xr-x - formal
-rw-r--r-- 802 input_stage.py
-rw-r--r-- 873 main_stage.py
-rw-r--r-- 2414 pipe_data.py