add traptype and trapaddr to PowerDecoder2. idea is to actually *change*
[soc.git] / src / soc / fu / trap /
drwxr-xr-x   ..
-rw-r--r-- 7969 main_stage.py
-rw-r--r-- 1174 pipe_data.py
drwxr-xr-x - test
-rw-r--r-- 1370 trap_input_data.py