Handle newer nMigen adding a "bench" hierarchy root in VCD files
[soc.git] / src / soc / fu / trap /
drwxr-xr-x   ..
-rw-r--r-- 0 __init__.py
drwxr-xr-x - formal
-rw-r--r-- 16011 main_stage.py
-rw-r--r-- 1582 pipe_data.py
-rw-r--r-- 1411 pipeline.py
drwxr-xr-x - test
-rw-r--r-- 1007 trap_input_record.py