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add simple GPIO peripheral to verilog TestIssuer
[soc.git] / src / soc / simple /
drwxr-xr-x   ..
-rw-r--r-- 0 __init__.py blob | history | raw
-rw-r--r-- 20088 core.py blob | history | raw
-rw-r--r-- 14563 issuer.py blob | history | raw
-rw-r--r-- 1199 issuer_verilog.py blob | history | raw
drwxr-xr-x - test tree | history