projects / soc.git / tree
? search:
summary | shortlog | log | commit | commitdiff | tree
history | HEAD
ha! have to explicitly specify the ports when writing out to ilang or verilog
[soc.git] / src / soc / simple /
drwxr-xr-x   ..
-rw-r--r-- 0 __init__.py blob | history | raw
-rw-r--r-- 15939 core.py blob | history | raw
-rw-r--r-- 10553 issuer.py blob | history | raw
-rw-r--r-- 930 issuer_verilog.py blob | history | raw
drwxr-xr-x - test tree | history