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add "nocore" option to build verilog
[soc.git]
/
src
/
soc
/
simple
/
drwxr-xr-x
..
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0
__init__.py
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-rw-r--r--
21870
core.py
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-rw-r--r--
18004
issuer.py
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-rw-r--r--
1331
issuer_verilog.py
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projects / soc.git / tree