c4m/vhdl/jtag/c4m_jtag_tap_controller.vhdl

   1 -- A JTAG complient tap controller implementation
   2 -- This is implemented based on the IEEE 1149.1 standard
   3
   4 library ieee;
   5 use ieee.std_logic_1164.ALL;
   6
   7 use work.c4m_jtag.ALL;
   8
   9 entity c4m_jtag_tap_controller is
  10   generic (
  11     DEBUG:              boolean := false;
  12
  13     IR_WIDTH:           integer := 2;
  14     IOTYPES:            IOTYPE_VECTOR := IOTYPES_NULL;
  15
  16     MANUFACTURER:       std_logic_vector(10 downto 0) := "10001111111";
  17     PART_NUMBER:        std_logic_vector(15 downto 0) := "0000000000000001";
  18     VERSION:            std_logic_vector(3 downto 0) := "0000"
  19   );
  20   port (
  21     -- The TAP signals
  22     TCK:        in std_logic;
  23     TMS:        in std_logic;
  24     TDI:        in std_logic;
  25     TDO:        out std_logic;
  26     TRST_N:     in std_logic;
  27
  28     -- The Instruction Register
  29     IR:         out std_logic_vector(IR_WIDTH-1 downto 0);
  30
  31     -- The FSM state indicators
  32     RESET:      out std_logic;
  33     CAPTURE:    out std_logic;
  34     SHIFT:      out std_logic;
  35     UPDATE:     out std_logic;
  36
  37     -- The I/O access ports
  38     CORE_IN:    out std_logic_vector(IOTYPES'range);
  39     CORE_EN:    in std_logic_vector(IOTYPES'range);
  40     CORE_OUT:   in std_logic_vector(IOTYPES'range);
  41
  42     -- The pad connections
  43     PAD_IN:     in std_logic_vector(IOTYPES'range);
  44     PAD_EN:     out std_logic_vector(IOTYPES'range);
  45     PAD_OUT:    out std_logic_vector(IOTYPES'range)
  46   );
  47 end c4m_jtag_tap_controller;
  48
  49 architecture rtl of c4m_jtag_tap_controller is
  50   constant null_logic_vector: std_logic_vector(1 to 0) := (others => 'X');
  51
  52   signal S_RESET:       std_logic;
  53   signal S_ISIR:        std_logic;
  54   signal S_ISDR:        std_logic;
  55   signal S_CAPTURE:     std_logic;
  56   signal S_SHIFT:       std_logic;
  57   signal S_UPDATE:      std_logic;
  58   signal S_IR:          std_logic_vector(IR_WIDTH-1 downto 0);
  59
  60   signal IR_TDO:        std_logic;
  61   signal IR_TDO_EN:     std_logic;
  62   signal ID_TDO:        std_logic;
  63   signal ID_TDO_EN:     std_logic;
  64   signal IO_TDO:        std_logic;
  65   signal IO_TDO_EN:     std_logic;
  66 begin
  67   IR <= S_IR;
  68   RESET <= S_RESET;
  69   CAPTURE <= S_CAPTURE and S_ISDR;
  70   SHIFT <= S_SHIFT and S_ISDR;
  71   UPDATE <= S_UPDATE and S_ISDR;
  72
  73   -- JTAG state machine
  74   FSM:  c4m_jtag_tap_fsm
  75     port map (
  76       TCK => TCK,
  77       TMS => TMS,
  78       TRST_N => TRST_N,
  79       RESET => S_RESET,
  80       ISIR => S_ISIR,
  81       ISDR => S_ISDR,
  82       CAPTURE => S_CAPTURE,
  83       SHIFT => S_SHIFT,
  84       UPDATE => S_UPDATE
  85     );
  86
  87   -- The instruction register
  88   IRBLOCK: c4m_jtag_irblock
  89     generic map (
  90       IR_WIDTH => IR_WIDTH
  91     )
  92     port map (
  93       TCK => TCK,
  94       TDI => TDI,
  95       TDO => IR_TDO,
  96       TDO_EN => IR_TDO_EN,
  97       IR => S_IR,
  98       RESET => S_RESET,
  99       CAPTURE => S_CAPTURE and S_ISIR,
 100       SHIFT => S_SHIFT and S_ISIR,
 101       UPDATE => S_UPDATE and S_ISIR
 102     );
 103
 104   -- The ID
 105   IDBLOCK: c4m_jtag_idblock
 106     generic map (
 107       IR_WIDTH => IR_WIDTH,
 108       PART_NUMBER => PART_NUMBER,
 109       MANUFACTURER => MANUFACTURER,
 110       VERSION => VERSION
 111     )
 112     port map (
 113       TCK => TCK,
 114       TDI => TDI,
 115       TDO => ID_TDO,
 116       TDO_EN => ID_TDO_EN,
 117       IR => S_IR,
 118       CAPTURE => S_CAPTURE and S_ISDR,
 119       SHIFT => S_SHIFT and S_ISDR,
 120       UPDATE => S_UPDATE and S_ISDR
 121     );
 122
 123   -- The IOs
 124   IOBLOCK_gen: if IOTYPES'length > 0 generate
 125     IOBLOCK: c4m_jtag_ioblock
 126       generic map (
 127         IR_WIDTH => IR_WIDTH,
 128         IOTYPES => IOTYPES
 129       )
 130       port map (
 131         TCK => TCK,
 132         TDI => TDI,
 133         TDO => IO_TDO,
 134         TDO_EN => IO_TDO_EN,
 135         IR => S_IR,
 136         CAPTURE => S_CAPTURE and S_ISDR,
 137         SHIFT => S_SHIFT and S_ISDR,
 138         UPDATE => S_UPDATE and S_ISDR,
 139         CORE_OUT => CORE_OUT,
 140         CORE_IN => CORE_IN,
 141         CORE_EN => CORE_EN,
 142         PAD_OUT => PAD_OUT,
 143         PAD_IN => PAD_IN,
 144         PAD_EN => PAD_EN
 145       );
 146   end generate IOBLOCK_gen;
 147   NOIOBLOCK_gen: if IOTYPES'length = 0 generate
 148     IO_TDO <= '0';
 149     IO_TDO_EN <= '0';
 150     CORE_IN <= null_logic_vector;
 151     PAD_EN <= null_logic_vector;
 152     PAD_OUT <= null_logic_vector;
 153   end generate NOIOBLOCK_gen;
 154
 155   TDO <= IR_TDO when IR_TDO_EN = '1' else
 156          ID_TDO when ID_TDO_EN = '1' else
 157          IO_TDO when IO_TDO_EN = '1' else
 158          '0';
 159
 160   CHECK_EN: if DEBUG generate
 161     signal EN:  std_logic_vector(2 downto 0) := "000";
 162   begin
 163     EN <= IR_TDO_EN & ID_TDO_EN & IO_TDO_EN;
 164     assert EN = "000" or EN = "100" or EN = "010" or EN = "001"
 165       report "TDO conflict in c4m_jtag_tap_controller"
 166       severity ERROR;
 167   end generate CHECK_EN;
 168 end rtl;