turn FPOp into module

diff --git a/src/add/fpbase.py b/src/add/fpbase.py
index fcd69a5c8ec13d58f9c4fc6dc5f23dd0542b92aa..bfd946219b65ec8a026eeab04f56c497d558775d 100644 (file)
--- a/src/add/fpbase.py
+++ b/src/add/fpbase.py
@@ -348,6 +348,12 @@ class FPOp:
         self.v   = Signal(width)
         self.stb = Signal(reset=0)
         self.ack = Signal()
+        self.trigger = Signal(reset_less=True)
+
+    def elaborate(self, platform):
+        m = Module()
+        m.d.sync += self.trigger.eq(self.stb & self.ack)
+        return m
 
     def chain_inv(self, in_op, extra=None):
         stb = in_op.stb

diff --git a/src/add/nmigen_add_experiment.py b/src/add/nmigen_add_experiment.py
index f6d44509f43dfe8e410f9448e9c35797cd7a2cd5..f5070f744373e5e6a1c29b8c71e7e824c46c3129 100644 (file)
--- a/src/add/nmigen_add_experiment.py
+++ b/src/add/nmigen_add_experiment.py
@@ -760,9 +760,14 @@ class FPPack(FPState):
 
 class FPPutZ(FPState):
 
+    def __init__(self, state, in_z, out_z):
+        FPState.__init__(self, state)
+        self.in_z = in_z
+        self.out_z = out_z
+
     def action(self, m):
         m.d.sync += [
-          self.out_z.v.eq(self.z.v)
+          self.out_z.v.eq(self.in_z.v)
         ]
         with m.If(self.out_z.stb & self.out_z.ack):
             m.d.sync += self.out_z.stb.eq(0)
@@ -791,6 +796,9 @@ class FPADD:
         """ creates the HDL code-fragment for FPAdd
         """
         m = Module()
+        m.submodules.in_a = self.in_a
+        m.submodules.in_b = self.in_b
+        m.submodules.out_z = self.out_z
 
         geta = self.add_state(FPGetOp("get_a", "get_b",
                                       self.in_a, self.width))
@@ -844,13 +852,9 @@ class FPADD:
         pa = self.add_state(FPPack(self.width))
         pa.setup(m, cor.out_z)
 
-        ppz = self.add_state(FPPutZ("pack_put_z"))
-        ppz.set_inputs({"z": pa.out_z})
-        ppz.set_outputs({"out_z": self.out_z})
+        ppz = self.add_state(FPPutZ("pack_put_z", pa.out_z, self.out_z))
 
-        pz = self.add_state(FPPutZ("put_z"))
-        pz.set_inputs({"z": sc.out_z})
-        pz.set_outputs({"out_z": self.out_z})
+        pz = self.add_state(FPPutZ("put_z", sc.out_z, self.out_z))
 
         with m.FSM() as fsm: