create base multi-in ports function

diff --git a/src/add/multipipe.py b/src/add/multipipe.py
index 8abdc172d405cd8039a79625825ec9f5da06c1f9..e07818a7922739ac987ef93d41880899f7feaa9d 100644 (file)
--- a/src/add/multipipe.py
+++ b/src/add/multipipe.py
@@ -71,10 +71,24 @@ class MultiInControlBase:
     def ports(self):
         res = []
         for i in range(len(self.p)):
-            res += [self.p[i].i_valid, self.p[i].o_ready,
-                    self.p[i].i_data]# XXX need flattening!]
-        res += [self.n.i_ready, self.n.o_valid,
-                self.n.o_data]   # XXX need flattening!]
+            p = self.p[i]
+            res += [p.i_valid, p.o_ready]
+            if hasattr(p.i_data, "ports"):
+                res += p.i_data.ports()
+            else:
+                rres = p.i_data
+                if not isinstance(rres, Sequence):
+                    rres = [rres]
+                res += rres
+        n = self.n
+        res += [n.i_ready, n.o_valid]
+        if hasattr(n.o_data, "ports"):
+            res += n.o_data.ports()
+        else:
+            rres = n.o_data
+            if not isinstance(rres, Sequence):
+                rres = [rres]
+            res += rres
         return res
 
 

diff --git a/src/add/test_prioritymux_pipe.py b/src/add/test_prioritymux_pipe.py
index d216736664b2775e24669b56d224588c456d7c12..0795cccd789ce2f2091cf7bdd8b1725dc468637b 100644 (file)
--- a/src/add/test_prioritymux_pipe.py
+++ b/src/add/test_prioritymux_pipe.py
@@ -4,17 +4,7 @@ from nmigen import Module, Signal, Cat
 from nmigen.compat.sim import run_simulation
 from nmigen.cli import verilog, rtlil
 
-from multipipe import CombMultiInPipeline, InputPriorityArbiter
-
-
-class PriorityUnbufferedPipeline(CombMultiInPipeline):
-    def __init__(self, stage, p_len=4):
-        p_mux = InputPriorityArbiter(self, p_len)
-        CombMultiInPipeline.__init__(self, stage, p_len=p_len, p_mux=p_mux)
-
-    def ports(self):
-        return self.p_mux.ports()
-        #return UnbufferedPipeline.ports(self) + self.p_mux.ports()
+from multipipe import (CombMultiInPipeline, PriorityCombMuxInPipe)
 
 
 class PassData:
@@ -29,12 +19,12 @@ class PassData:
     def ports(self):
         return [self.mid, self.idx, self.data]
 
+
 class PassThroughStage:
     def ispec(self):
         return PassData()
     def ospec(self):
         return self.ispec() # same as ospec
-                
     def process(self, i):
         return i # pass-through
 
@@ -214,20 +204,11 @@ class InputTest:
                 break
 
 
-class TestPriorityMuxPipe(PriorityUnbufferedPipeline):
+class TestPriorityMuxPipe(PriorityCombMuxInPipe):
     def __init__(self):
         self.num_rows = 4
         stage = PassThroughStage()
-        PriorityUnbufferedPipeline.__init__(self, stage, p_len=self.num_rows)
-
-    def ports(self):
-        res = []
-        for i in range(len(self.p)):
-            res += [self.p[i].i_valid, self.p[i].o_ready] + \
-                    self.p[i].i_data.ports()
-        res += [self.n.i_ready, self.n.o_valid] + \
-                self.n.o_data.ports()
-        return res
+        PriorityCombMuxInPipe.__init__(self, stage, p_len=self.num_rows)
 
 
 if __name__ == '__main__':