powerpc-add/src/glossary.tex

   1 % Glossary
   2 % Yes: some of them are obvious, but it does no harm.
   3
   4 % In the main documentation text I have not tagged every use of the glossary
   5 % entries below, I have tagged the first in a chapter, or first use for some
   6 % number of paragraphs.
   7
   8 % Put the definition of terms of the glossary terms in here I did try to keep
   9 % in alphabetic order - for easier editing, but then decided that keeping
  10 % related terms together helped (in which case put some blank lines
  11 % before/after the related items). They will be generated (in the PDF) in
  12 % alphabetic order regardless of the order below
  13
  14 % To use one do something like: \gls{PowerPC}
  15 % Note that the entries are case sensitive.
  16
  17 % Having an entry below will not make it appear in the glossary,
  18 % it will only appear if it is used, eg: \gls{PowerPC}
  19
  20 % How to use:
  21 % GlsName       The text that should be used in the document, eg: \gls{GlsName}
  22 % GlsText       The text that will be shown in the document in place of \gls{GlsName}
  23 %               GlsName and GlsText can be different but you will probably want
  24 %               to make them the same.
  25 % \newglossaryentry{GlsName}
  26 % {
  27 %   name=GlsText,
  28 %   description={
  29 %     See: \href{}{}
  30 %     }
  31 % }
  32
  33 % See:
  34 % https://en.wikibooks.org/wiki/LaTeX/Glossary
  35 % http://tug.ctan.org/macros/latex/contrib/glossaries/glossariesbegin.pdf
  36
  37 % An empty entry to use as a template:
  38 % \newglossaryentry{}
  39 % {
  40 %   name=,
  41 %   description={
  42 %     See: \href{}{}
  43 %     }
  44 % }
  45
  46 % BUG: the glossary entries have a '.' after them that I am not expecting.
  47
  48 % BEWARE: the documentation may need to be built more than once for all of the
  49 % entries below to appear. This seems to be if an entry is only mentioned in another
  50 % glossary entry.
  51
  52 \newglossaryentry{ALU}
  53 {
  54   name=ALU,
  55   description={
  56     Arithmetic Logic Unit.
  57     The part of the computer that does calculations of integer data.
  58     Contrast to the \gls{FPU}.
  59     See: \href{https://en.wikipedia.org/wiki/Arithmetic_logic_unit}{Wikipedia}
  60     }
  61 }
  62
  63 \newglossaryentry{Binutils}
  64 {
  65   name=Binutils,
  66   description={
  67     GNU Binary Utilities is part of the toolchain used for creating and managing
  68     binary objects (compiled code).
  69     Used with \gls{gcc}.
  70     See: \href{https://www.gnu.org/software/binutils/}{GNU web site}
  71     }
  72 }
  73
  74 \newglossaryentry{CPU}
  75 {
  76   name=CPU,
  77   description={
  78     Central Processing Unit.
  79     The brain of a conventional computer that executes general purpose programs.
  80     Contrast with \gls{GPU} and \gls{VPU}.
  81 %    See: \href{}{}
  82     }
  83 }
  84
  85 \newglossaryentry{CSR}
  86 {
  87   name=CSR,
  88   description={
  89      Control and Status Register.
  90      A special register that records CPU status and processing options.
  91      One important option to this project is that the special instructions
  92      that we have created will be recognised.
  93 %    See: \href{}{}
  94     }
  95 }
  96
  97 \newglossaryentry{FPGA}
  98 {
  99   name=FPGA,
 100   description={
 101     Field-programmable gate array.
 102     An integrated circuit where the circuitry can be reconfigured.
 103     See: \href{https://en.wikipedia.org/wiki/Field-programmable_gate_array}{Wikipedia}
 104     }
 105 }
 106
 107 \newglossaryentry{FPU}
 108 {
 109   name=FPU,
 110   description={
 111     Floating Point Unit.
 112     The part of the computer that does calculations of data in, probably, \gls{IEEE754} format.
 113     See: \href{https://en.wikipedia.org/wiki/Floating-point_unit}{Wikipedia}
 114     }
 115 }
 116
 117 \newglossaryentry{FU}
 118 {
 119   name=FU,
 120   description={
 121     Functional Unit.
 122     A computer typically has five main functional units:
 123     \gls{CPU}, Input (get data from: keyboard, network, microphone, ...),
 124     Output (send data to: screen, network, audio, ...), Memory (RAM, disk, ...) \&
 125     Control (coordinates the other FUs).
 126     Many of these FUs are built out of smaller FUs.
 127     }
 128 }
 129
 130 \newglossaryentry{gcc}
 131 {
 132   name=gcc,
 133   description={
 134     \gls{GNU} Compiler Collection.
 135     A popular open source compiler for C (\& related), Fortran, Ada \& Go and able to generate
 136     object code for many \gls{ISA}s including \gls{PowerPC}.
 137     See: \href{https://en.wikipedia.org/wiki/GNU_Compiler_Collection}{Wikipedia}
 138     }
 139 }
 140
 141
 142 \newglossaryentry{GNU}
 143 {
 144   name=GNU,
 145   description={
 146     The GNU project is a large collection of free software.
 147     It provides many of the core programs that are used by many \gls{Linux} distributions.
 148     See: \href{https://www.gnu.org/}{GNU website}
 149     }
 150 }
 151
 152 \newglossaryentry{GPU}
 153 {
 154   name=GPU,
 155   description={
 156     Graphics processing unit.
 157     Special purpose processor optimised for graphics and image generation,
 158     often able to run in parallel -- the same instructions on
 159     different data at the same time.
 160     Contrast with \gls{CPU} and \gls{VPU}.
 161     See: \href{https://en.wikipedia.org/wiki/Graphics_processing_unit}{Wikipedia}
 162     }
 163 }
 164
 165 \newglossaryentry{ICubeCorpIC3128}
 166 {
 167   name=ICubeCorp IC3128,
 168   description={
 169     A \gls{SoC} from ICube that has both \gls{CPU} and \gls{GPU} on a single chip.
 170     See: \href{https://www.cnx-software.com/2014/10/15/icube-mvp-socs-combine-cpu-and-gpu-into-a-single-unified-processing-unit-upu/}{CNX Software}
 171     }
 172 }
 173
 174 \newglossaryentry{IEEE754}
 175 {
 176   name=IEEE754,
 177   description={
 178     A popular standard way of representing and manipulating floating point numbers.
 179     Initiated by the  Institute of Electrical and Electronics Engineers in 1985.
 180     Different precisions from 16 to 256 bits are described.
 181     See: \gls{FPU} \href{https://en.wikipedia.org/wiki/IEEE_754}{Wikipedia}
 182     }
 183 }
 184
 185 \newglossaryentry{IOMMU}
 186 {
 187   name=IOMMU,
 188   description={
 189     Input Output Memory Management Unit.
 190     Mediates between Input/Output devices and main memory mapping virtual
 191     addresses to physical ones and, maybe, enforcing protection restrictions.
 192     See: \href{https://en.wikipedia.org/wiki/Input\%E2\%80\%93output_memory_management_unit}{Wikipedia}
 193     }
 194 }
 195
 196 \newglossaryentry{ISA}
 197 {
 198   name=ISA,
 199   description={
 200     Instruction Set Architecture.
 201     An abstract model of a computer a definition that includes: registers, memory access,
 202     input/output, data types, CPU instruction set.
 203     Everything that is needed to be able to create programs to run on the machine.
 204     See: \href{https://en.wikipedia.org/wiki/Instruction_set_architecture}{Wikipedia}
 205     }
 206 }
 207
 208 \newglossaryentry{ISAMUX}
 209 {
 210   name=ISAMUX,
 211   description={
 212     \gls{ISA} \gls{MUX} -- having the same bits in the ISA mean different things.
 213     }
 214 }
 215
 216 \newglossaryentry{H.265}
 217 {
 218   name=H.265,
 219   description={
 220     High Efficiency Video Coding, also known as HEVC \& MPEG-H Part 2.
 221     Released in 2013.
 222     Its data compression is better, for the same video quality, than previous standards:
 223     AVC, H.264, or MPEG-4 Part 10.
 224     Patent license may be required for H.265 use.
 225     See: \gls{VP9}
 226     \href{https://en.wikipedia.org/wiki/High_Efficiency_Video_Coding}{Wikipedia}
 227     }
 228 }
 229
 230 \newglossaryentry{JIT}
 231 {
 232   name=JIT,
 233   description={
 234     Just In Time compilation.
 235     Translate when the program runs, only when needed.
 236     See: \href{https://en.wikipedia.org/wiki/Just-in-time_compilation}{Wikipedia}
 237     }
 238 }
 239
 240 \newglossaryentry{Linux}
 241 {
 242   name=Linux,
 243   description={
 244     A free kernel on which free operating systems and specialised environments are built.
 245     Linux is found all the way for small, embedded systems, to desktops, to servers
 246     and the world's biggest super computers.
 247     It runs on many \gls{ISA}s and supports a huge variety of peripheral devices.
 248     Linux was inspired by Unix and is upwards compatible with POSIX.
 249     See: \href{https://www.linuxfoundation.org/}{Linux Foundation}
 250     }
 251 }
 252
 253
 254 \newglossaryentry{LLVM}
 255 {
 256   name=LLVM,
 257   description={
 258     A compiler and related toolchain.
 259     An open source and able to compileAda, C, C++, D, Delphi, Fortran, Haskell, Julia, Objective-C, Rust, and Swift
 260     able to generate object code for many \gls{ISA}s including \gls{PowerPC}.
 261     See: \href{https://en.wikipedia.org/wiki/LLVM}{Wikipedia}
 262     }
 263 }
 264
 265
 266
 267 \newglossaryentry{LSB}
 268 {
 269   name=LSB,
 270   description={
 271     Least Significant Bit.
 272     In an integer represented in binary, the bit that has the smallest value.
 273     In this document the LSB is called 'bit 0', if this is the only bit set the
 274     integer will have the value 1.
 275     See: \gls{MSB}
 276 %    See: \href{}{}
 277     }
 278 }
 279
 280 \newglossaryentry{MSB}
 281 {
 282   name=MSB,
 283   description={
 284     Most Significant Bit.
 285     In an integer represented in binary, the bit that has the greatest value.
 286     If the integer is signed, this bit will make the integer negative if it is 1.
 287     In this document the MSB is given the highest number in the integer, eg:
 288     in 8 bits it is called 'bit 7'; in 32 bits it is called 'bit 31'.
 289     See: \gls{LSB}
 290 %    See: \href{}{}
 291     }
 292 }
 293
 294
 295
 296 % microwatt     https://github.com/antonblanchard/microwatt/blob/master/decode1.vhdl
 297 % https://www.zephyrproject.org/microwatt-and-the-power-isa-support-in-renode/
 298 % I did see references to this somewhere ... cannot see them now
 299 \newglossaryentry{microwatt}
 300 {
 301   name=microwatt,
 302   description={
 303      An open source implementation of POWER by IBM in 2019.
 304 %    See: \href{}{}
 305     }
 306 }
 307
 308 \newglossaryentry{MISA}
 309 {
 310   name=MISA,
 311   description={
 312     Multiple Instruction Sets Architecture.
 313     The ability to run more than one \gls{ISA} on the same hardware.
 314     A setting in a \gls{CSR} controls which instructions will be
 315     recognised at any time.
 316 %    See: \href{}{}
 317     }
 318 }
 319 % https://ieeexplore.ieee.org/document/6136696 - paywalled
 320 % https://www.researchgate.net/figure/Overview-of-the-MISA-instructional-system-design-method_fig2_245165034
 321 % https://people.eecs.berkeley.edu/~krste/papers/riscv-privileged-v1.9.pdf page 15
 322
 323 \newglossaryentry{MUX}
 324 {
 325   name=MUX,
 326   description={
 327     Multiplex, a way of compressing several things into the same data.
 328 %    See: \href{}{}
 329     }
 330 }
 331
 332 \newglossaryentry{PC}
 333 {
 334   name=PC,
 335   description={
 336     Program Counter.
 337     A register that holds the address of the instruction being executed.
 338     }
 339 }
 340
 341 \newglossaryentry{PowerPC}
 342 {
 343   name=PowerPC,
 344   description={
 345     A \gls{RISC} \gls{ISA} created in 1991 by Apple, IBM and Motorola.
 346     The name is a backronym: Performance Optimization With Enhanced RISC
 347     Performance Computing, sometimes abbreviated as PPC or called POWER).
 348     See: \href{https://en.wikipedia.org/wiki/PowerPC}{Wikipedia}
 349   }
 350 }
 351
 352 \newglossaryentry{RISC}
 353 {
 354   name=RISC,
 355   description={
 356     Reduced Instruction Set Computer.
 357     A computer design philosophy that features simple but fast instructions,
 358     often with many registers.
 359     See: \href{https://en.wikipedia.org/wiki/Reduced_instruction_set_computer}{Wikipedia}
 360     }
 361 }
 362
 363 \newglossaryentry{RISCV}
 364 {
 365   name=RISC-V,
 366   description={
 367     An open sourced \gls{RISC} \gls{ISA} started in 2010 at the University of California, Berkeley.
 368     See: \href{https://en.wikipedia.org/wiki/RISC-V}{Wikipedia}
 369     }
 370 }
 371
 372 \newglossaryentry{SoC}
 373 {
 374   name=SoC,
 375   description={
 376     System on a Chip.
 377     An integrated circuit that has (almost all) the components needed to
 378     make a fully running system.
 379     See: \href{https://en.wikipedia.org/wiki/System_on_a_chip}{Wikipedia}
 380     }
 381 }
 382
 383 \newglossaryentry{SP}
 384 {
 385   name=SP,
 386   description={
 387     Stack Pointer.
 388     A register that holds the address of the current function stack
 389     frame -- used for variables local to a function.
 390     }
 391 }
 392
 393 \newglossaryentry{SPARC}
 394 {
 395   name=SPARC,
 396   description={
 397     A \gls{RISC} \gls{ISA} created by Sun Microsystems.
 398     See: \href{https://en.wikipedia.org/wiki/SPARC}{Wikipedia}
 399     }
 400 }
 401
 402 \newglossaryentry{SupervisorMode}
 403 {
 404   name=Supervisor Mode,
 405   description={
 406     A privileged CPU state where the program can execute instructions or otherwise
 407     do things that a non-privileged program would not be allowed to do.
 408 %    See: \href{}{}
 409     }
 410 }
 411
 412 \newglossaryentry{VideoCoreIV}
 413 {
 414   name=VideoCore IV,
 415   description={
 416     Low power \gls{SoC} from Broadcom. ARM CPU that is used in the Raspberry Pi.
 417     See: \href{https://en.wikipedia.org/wiki/VideoCore}{Wikipedia}
 418     }
 419 }
 420
 421 \newglossaryentry{VP9}
 422 {
 423   name=VP9,
 424   description={
 425     Video encoding format released by Google in 2013.
 426     Released open \& royalty free although Sisvel has made some claims.
 427     See: \href{https://en.wikipedia.org/wiki/VP9}{Wikipedia}
 428     }
 429 }
 430
 431 % https://libre-soc.org/vpu/
 432 \newglossaryentry{VPU}
 433 {
 434   name=VPU,
 435   description={
 436      Video Processing Unit.
 437      Similar to a \gls{CPU} but has extra hardware instructions to speed up things
 438 %     like the decoding and encoding of \gls{H.265}, or \gls{VP9}.
 439     }
 440 }
 441
 442 \newglossaryentry{Z80}
 443 {
 444   name=Zilog Z80,
 445   description={
 446     An 8 bit processor produced by the Zilog Inc in 1986.
 447     It is compatible with the Intel 8080 processor.
 448     See: \href{https://en.wikipedia.org/wiki/Z80}{Wikiedia}
 449     }
 450 }
 451
 452
 453
 454 \newglossaryentry{LE}
 455 {
 456   name=LE,
 457   description={
 458     Little Endian.
 459     When 2/4/8 bytes are loaded into a 16/32/64 bit register the bytes at \textbf{lower}
 460     memory addresses are put into \textbf{lower -- less significant} places in the register.
 461     Intel/AMD are LE.
 462     See: \gls{BE} and \gls{endian}
 463     }
 464 }
 465 \newglossaryentry{BE}
 466 {
 467   name=BE,
 468   description={
 469     Big Endian.
 470     When 2/4/8 bytes are loaded into a 16/32/64 bit register the bytes at \textbf{lower}
 471     memory addresses are put into \textbf{higher -- more significant} places in the register.
 472     IBM z is BE.
 473     See: \gls{LE} and \gls{endian}
 474     }
 475 }
 476 \newglossaryentry{endian}
 477 {
 478   name=endian,
 479   description={
 480     Describes in a multi-byte word, which byte contains the most significant bits.
 481     Two choices Little Endian \gls{LE} and and Big Endian \gls{BE} predominate,
 482     but it can be more complicated when a word is made of 4 or more bytes.
 483     \gls{PowerPC}, ARM \& \gls{SPARC} can be either LE or BE.
 484     See: \href{https://en.wikipedia.org/wiki/Endianness}{Wikipedia}
 485     }
 486 }
 487
 488
 489
 490 % Other entries to consider:
 491 % emulator
 492 % namespace
 493 % MSB
 494 % PCR
 495 % SIMD
 496 % RA
 497 % RB
 498 % 6600          https://libre-soc.org/3d_gpu/architecture/6600scoreboard/
 499 % DAG           Directed Acyclic Graph
 500 % SR latch
 501 %
 502 % WAR           https://libre-soc.org/3d_gpu/architecture/6600scoreboard/ #10
 503 % FU-FU function to function    https://libre-soc.org/3d_gpu/architecture/6600scoreboard/       #14
 504 % GORD GOWR     GO read/write
 505 % ISANS
 506 %  Unified Processing Unit (UPU)
 507 %  MVP (Multi-thread Virtual Pipeline
 508 % SIE
 509 % WARL
 510 % WLRL
 511 % xepc -- in isamux.tex
 512 % RV - as in RV mode    Description isamux
 513 % RVS - see SVPrefix
 514 % VL MVL        see SVPrefix
 515 % SVorig