README.txt

   1 # sim openocd test
   2
   3 in the soc directory, create the verilog file
   4     "python issuer_verilog.py libresoc.v"
   5
   6 copy to libresoc/ directory
   7 terminal 1: ./sim.py
   8 terminal 2: openocd -f openocd.cfg -c init -c 'svf idcode_test2.svf'
   9
  10 # ecp5 build
  11
  12 same thing: first build libresoc.v and copy it to the libresoc/ directory
  13
  14 ./versa_ecp5.py --sys-clk-freq=55e6 --build
  15 ./versa_ecp5.py --sys-clk-freq=55e6 --load