git.libre-soc.org Git - litex.git/history

2020-05-12	enjoy-digital	Merge pull request #478 from antmicro/extended_spi_flash	blob \| commitdiff \| raw
2020-05-11	enjoy-digital	Merge branch 'master' into rdimm_bside_init	blob \| commitdiff \| raw
2020-05-11	enjoy-digital	Merge pull request #484 from ilya-epifanov/lattice...	blob \| commitdiff \| raw
2020-05-11	enjoy-digital	Merge branch 'master' into cpu-imac-config-for-vexriscv	blob \| commitdiff \| raw
2020-05-07	Dave Marples	Merge branch 'master' of https://github.com/enjoy-digit...	blob \| commitdiff \| raw
2020-05-06	enjoy-digital	Merge pull request #499 from DurandA/patch-2	blob \| commitdiff \| raw
2020-05-05	Arnaud Durand	Add data dirs to manifest	blob \| commitdiff \| raw
2020-04-28	enjoy-digital	Merge pull request #399 from mithro/litex-sm2py	blob \| commitdiff \| raw \| diff to current
2020-04-27	enjoy-digital	Merge branch 'master' into litex-sm2py	blob \| commitdiff \| raw \| diff to current
2020-04-12	Tim 'mithro' Ansell	Remove directories from submodules from MANIFEST.in...	blob \| commitdiff \| raw \| diff to current
2019-07-04	Tim Ansell	Merge pull request #210 from DurandA/master	blob \| commitdiff \| raw \| diff to current
2019-07-03	Arnaud Durand	Add verilog submodule from CPU cores to manifest	blob \| commitdiff \| raw \| diff to current
2016-03-31	Florent Kermarrec	initial RISC-V support (with picorv32), still some...	blob \| commitdiff \| raw \| diff to current
2015-11-07	Florent Kermarrec	litex: get verilator simulation working and add sim...	blob \| commitdiff \| raw \| diff to current
2015-11-07	Florent Kermarrec	litex: reorganize things, first work working version	blob \| commitdiff \| raw \| diff to current
2015-11-07	Florent Kermarrec	import misoc in litex/soc	blob \| commitdiff \| raw
2015-11-04	Sebastien Bourdeauducq	Merge 'new' branch	blob \| commitdiff \| raw \| diff to current
2015-10-19	Sebastien Bourdeauducq	MANIFEST.in: fix lm32 data directory	blob \| commitdiff \| raw \| diff to current
2015-10-05	Sebastien Bourdeauducq	setup: include software and Verilog files	blob \| commitdiff \| raw \| diff to current

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