more work on orangecrab dram

diff --git a/src/ls2.py b/src/ls2.py
index 2e313ce7b5cb4aae794cb63bb04411f7042efab0..cb620c21c86e6dbdd08541de76943bab7830f091 100644 (file)
--- a/src/ls2.py
+++ b/src/ls2.py
@@ -292,11 +292,12 @@ class DDR3SoC(SoC, Elaboratable):
         sync_bits = 26
         need_bridge=False
         if fpga in ['versa_ecp5', 'versa_ecp5_85', 'isim', 'ulx3s',
-                    'orangecrab', 'rcs_arctic_tern_bmc_card']:
-            if fpga in ['isim']:
+                    'orangecrab','orangecrab_isim', 'rcs_arctic_tern_bmc_card']:
+            if fpga in ['isim','orangecrab_isim']:
                 pod_bits = 5
                 sync_bits = 6
-            if fpga in ['orangecrab', 'rcs_arctic_tern_bmc_card']:
+            if fpga in ['orangecrab', 'orangecrab_sim',
+                        'rcs_arctic_tern_bmc_card']:
                 need_bridge=True
             self.crg = ECP5CRG(clk_freq, dram_clk_freq=dram_clk_freq,
                                pod_bits=pod_bits, sync_bits=sync_bits,
@@ -552,6 +553,7 @@ class DDR3SoC(SoC, Elaboratable):
                                              'isim',
                                              'rcs_arctic_tern_bmc_card',
                                              'orangecrab',
+                                             'orangecrab_isim',
                                              'versa_ecp5',
                                              'versa_ecp5_85',
                                              'arty_a7']:
@@ -563,6 +565,7 @@ class DDR3SoC(SoC, Elaboratable):
                         'versa_ecp5_85',
                         'rcs_arctic_tern_bmc_card',
                         'orangecrab',
+                        'orangecrab_isim',
                         'isim']:
                 spi0_is_lattice_ecp5_clk = True
 
@@ -584,7 +587,7 @@ class DDR3SoC(SoC, Elaboratable):
         # Ethernet MAC
         if ethmac_0_pins is not None and fpga in ['versa_ecp5',
                                                   'versa_ecp5_85',
-                                                  'isim']:
+                                                  'isim']: # not orangecrab
             self.eth_irq = IRQLine()
             # The OpenCores Ethernet MAC contains two independent Wishbone
             # interfaces, a slave (configuration) interface and a master (DMA)
@@ -828,13 +831,14 @@ def build_platform(fpga, firmware):
                      'orangecrab': OrangeCrabR0_2_85k_Platform,
                      'arty_a7': ArtyA7_100Platform,
                      'isim': IcarusVersaPlatform,
+                     'orangecrab_isim': IcarusVersaPlatform,
                      'rcs_arctic_tern_bmc_card':None, #TODO
                      'sim': None,
                     }[fpga]
     toolchain = {'arty_a7': "yosys_nextpnr",
                  'versa_ecp5': 'Trellis',
                  'versa_ecp5_85': 'Trellis',
-                 'orangecrab': 'Trellis',
+                 'orangecrab_isim': 'Trellis',
                  'isim': 'Trellis',
                  'ulx3s': 'Trellis',
                  'rcs_arctic_tern_bmc_card': 'Trellis',
@@ -844,9 +848,10 @@ def build_platform(fpga, firmware):
                  'versa_ecp5': MT41K64M16,
                  'versa_ecp5_85': MT41K64M16,
                  'orangecrab': MT41K64M16,
+                 'orangecrab_isim': MT41K64M16,
                  #'versa_ecp5': MT41K256M16,
                  'ulx3s': None,
-                 'rcs_arctic_tern_bmc_card': None, # TODO
+                 'rcs_arctic_tern_bmc_card': None, #TODO
                  'sim': MT41K256M16,
                  'isim': MT41K64M16,
                 }.get(fpga, None)
@@ -881,7 +886,7 @@ def build_platform(fpga, firmware):
         clk_freq = 27.0e6 # urrr "working" with the QSPI core (25 mhz does not)
     if fpga == 'ulx3s':
         clk_freq = 40.0e6
-    if fpga == 'orangecrab':
+    if fpga == 'orangecrab' or fpga=='orangecrab_isim':
         clk_freq = 50e6
 
     # merge dram_clk_freq with clk_freq if the same
@@ -917,7 +922,7 @@ def build_platform(fpga, firmware):
     ddr_pins = None
     if (enable_dram and platform is not None and
         fpga in ['versa_ecp5', 'versa_ecp5_85', 'isim',
-                 'orangecrab']): # not yet 'arty_a7',
+                 'orangecrab','orangecrab_isim']): # not yet 'arty_a7',
         ddr_pins = platform.request("ddr3", 0,
                                     dir={"dq":"-", "dqs":"-"},
                                     xdr={"rst": 4, "clk":4, "a":4,
@@ -1106,9 +1111,8 @@ def build_platform(fpga, firmware):
 
     if toolchain == 'Trellis':
         # add -abc9 option to yosys synth_ecp5
-        os.environ['NMIGEN_synth_opts'] = '-abc9'              # optimize for speed
-        # os.environ['NMIGEN_synth_opts'] = '-nowidelut'       # optimize for size
-        # os.environ['NMIGEN_synth_opts'] = '-abc9 -nowidelut' # conflicting goals
+        os.environ['NMIGEN_synth_opts'] = '-abc9'              # speed
+        # os.environ['NMIGEN_synth_opts'] = '-nowidelut'       # size
 
     if toolchain == 'yosys_nextpnr':
         # add --seed 2 to arty a7 compile-time options
@@ -1118,7 +1122,7 @@ def build_platform(fpga, firmware):
 
     if platform is not None:
         # build and upload it
-        if fpga == 'isim':
+        if fpga == 'isim' or fpga == 'orangecrab_isim':
             platform.build(soc, do_program=False,
                                 do_build=True, build_dir="build_simsoc")
         else: