| 2022-04-07 |
Raptor Engineering... | Move simulation HyperRAM pins off of DDR3 pins |
tree | commitdiff |
| 2022-04-06 |
Luke Kenneth Casso... | add QSPI support to arty_a7 |
tree | commitdiff |
| 2022-04-04 |
Luke Kenneth Casso... | allow setting individual directions on QSPI dq0-dq3 |
tree | commitdiff |
| 2022-04-04 |
Luke Kenneth Casso... | sigh put firmware.hex qspi file in correct place |
tree | commitdiff |
| 2022-04-04 |
Luke Kenneth Casso... | increase power-on-delay for icarus sim to allow reset... |
tree | commitdiff |
| 2022-04-04 |
Luke Kenneth Casso... | disable ethmac for now, pass firmware.hex to cypress... |
tree | commitdiff |
| 2022-04-04 |
Luke Kenneth Casso... | redo start address of firmware so it can be specified... |
tree | commitdiff |
| 2022-04-04 |
Raptor Engineering... | Fix SPI device simulation model MISO/MOSI wiring |
tree | commitdiff |
| 2022-04-02 |
Raptor Engineering... | Add 10/100 MAC pins for Versa boards and enable MAC |
tree | commitdiff |
| 2022-03-31 |
Luke Kenneth Casso... | got icarus verilog model of QSPI working and it returns... |
tree | commitdiff |
| 2022-03-31 |
Luke Kenneth Casso... | whitespace cleanup |
tree | commitdiff |
| 2022-03-31 |
Raptor Engineering... | Fix Tercel QSPI master connections |
tree | commitdiff |
| 2022-03-31 |
Luke Kenneth Casso... | remove {err} feature from Tercel |
tree | commitdiff |
| 2022-03-29 |
Luke Kenneth Casso... | add err wishbone feature to Tercel |
tree | commitdiff |
| 2022-03-29 |
Luke Kenneth Casso... | remove clk from spi_flash, |
tree | commitdiff |
| 2022-03-29 |
Luke Kenneth Casso... | add qspi module to arty_a7 |
tree | commitdiff |
| 2022-03-29 |
Luke Kenneth Casso... | use nmigen_boards naming conventions for SPIFlash |
tree | commitdiff |
| 2022-03-29 |
Luke Kenneth Casso... | update comments, link/setup of peripherals |
tree | commitdiff |
| 2022-03-29 |
Luke Kenneth Casso... | add TODO comments about using platform.add_resources |
tree | commitdiff |
| 2022-03-29 |
Luke Kenneth Casso... | whitespace cleanup, 80 char limit |
tree | commitdiff |
| 2022-03-29 |
Raptor Engineering... | Add initial integration for OpenCores 10/100 Ethernet MAC |
tree | commitdiff |
| 2022-03-28 |
Raptor Engineering... | Fix instructions in comment |
tree | commitdiff |
| 2022-03-27 |
Luke Kenneth Casso... | set reset from ResetSignal not straight to 1 for HyperRAM |
tree | commitdiff |
| 2022-03-27 |
Luke Kenneth Casso... | try latency of 7 for winbond hyperram |
tree | commitdiff |
| 2022-03-27 |
Luke Kenneth Casso... | set upper CSns on HyperRAM to zero and set reset_n HI |
tree | commitdiff |
| 2022-03-26 |
Luke Kenneth Casso... | add clock output on hyperram sim |
tree | commitdiff |
| 2022-03-26 |
Luke Kenneth Casso... | add all 4 CSn lines for Quad HyperRAM PMOD |
tree | commitdiff |
| 2022-03-26 |
Luke Kenneth Casso... | grr |
tree | commitdiff |
| 2022-03-26 |
Luke Kenneth Casso... | reduce power-on-delay bits to 2 for icarus sim ecp5 |
tree | commitdiff |
| 2022-03-26 |
Luke Kenneth Casso... | remove switches from hyperram iverilog test |
tree | commitdiff |
| 2022-03-26 |
Luke Kenneth Casso... | remove unneeded model variable |
tree | commitdiff |
| 2022-03-26 |
Luke Kenneth Casso... | add missing ECP5 model OBZ.v and rename testbench |
tree | commitdiff |
| 2022-03-26 |
Luke Kenneth Casso... | sort out platform IO pads for iverilog hyperram sim |
tree | commitdiff |
| 2022-03-26 |
Luke Kenneth Casso... | add hyperram iverilog runner including s27kl0641.v... |
tree | commitdiff |
| 2022-03-25 |
Luke Kenneth Casso... | rename ECP5 CRG, move source, remove duplicate version |
tree | commitdiff |
| 2022-03-25 |
Luke Kenneth Casso... | up arty a7 frequency to 40 mhz |
tree | commitdiff |
| 2022-03-25 |
Luke Kenneth Casso... | increase time for power-on-delay to 2^25 in ECP5 |
tree | commitdiff |
| 2022-03-24 |
Luke Kenneth Casso... | increase delay on ECP5 ulx3s |
tree | commitdiff |
| 2022-03-24 |
Luke Kenneth Casso... | check ulx3s, add CRG support for ulx3s |
tree | commitdiff |
| 2022-03-24 |
Luke Kenneth Casso... | establish power-on reset stabilisation for Arty A7... |
tree | commitdiff |
| 2022-03-22 |
Luke Kenneth Casso... | add hack to modify VERSA_ECP5 85F platform to speed... |
tree | commitdiff |
| 2022-03-22 |
Luke Kenneth Casso... | adding hyperram for arty a7 and also adding a workaroun... |
tree | commitdiff |
| 2022-03-20 |
Luke Kenneth Casso... | crank A7 FPGA speed down to experiment |
tree | commitdiff |
| 2022-03-20 |
Luke Kenneth Casso... | code-comments |
tree | commitdiff |
| 2022-03-20 |
Luke Kenneth Casso... | fix Arty A7-100t PLL with quick demo |
tree | commitdiff |
| 2022-03-20 |
Luke Kenneth Casso... | first cut at Arty A7 Clock-Reset-Generator with S7 PLL |
tree | commitdiff |
| 2022-03-20 |
Luke Kenneth Casso... | beginnings of arty a7 clock-reset-generator |
tree | commitdiff |
| 2022-03-19 |
Luke Kenneth Casso... | add VERSA_ECP5 85F custom board |
tree | commitdiff |
| 2022-03-19 |
Luke Kenneth Casso... | set IO_TYPE 3.3v attribute on HyperRAM not IOSTANDARD |
tree | commitdiff |
| 2022-03-19 |
Luke Kenneth Casso... | correct pin names for HyperRAMResource, indent spi0... |
tree | commitdiff |
| 2022-03-19 |
Luke Kenneth Casso... | fixed hyperram pin names which was stopping verilator... |
tree | commitdiff |
| 2022-03-19 |
Luke Kenneth Casso... | disable hyperram for now (under investigation) |
tree | commitdiff |
| 2022-03-19 |
Luke Kenneth Casso... | adding in hyperram peripheral |
tree | commitdiff |
| 2022-03-18 |
Luke Kenneth Casso... | whitespace / module-import / comments / tidyup |
tree | commitdiff |
| 2022-03-18 |
Luke Kenneth Casso... | beginning to add hyperram module |
tree | commitdiff |
| 2022-03-18 |
Luke Kenneth Casso... | whitespace cleanup and make SPI core (temporarily)... |
tree | commitdiff |
| 2022-03-17 |
Luke Kenneth Casso... | work-in-progress on DDR3 firmware. sigh |
tree | commitdiff |
| 2022-03-16 |
Raptor Engineering... | Add initial Tercel SPI controller |
tree | commitdiff |
| 2022-03-10 |
Luke Kenneth Casso... | sigh gramWishbone is not WB4-pipeline-burst-compliant |
tree | commitdiff |
| 2022-03-09 |
Luke Kenneth Casso... | fix WB6to32 downconverter with stall signalling |
tree | commitdiff |
| 2022-03-09 |
Luke Kenneth Casso... | add stall signal to arbiter, assume nmigen-soc takes |
tree | commitdiff |
| 2022-03-04 |
Luke Kenneth Casso... | add experimental stall-capable 64-to-32 wishbone converter |
tree | commitdiff |
| 2022-03-02 |
Luke Kenneth Casso... | invert reset and chip-select on dram, and initialise... |
tree | commitdiff |
| 2022-03-01 |
Luke Kenneth Casso... | add new icarus-versa-ecp5 platform in ls2.py |
tree | commitdiff |
| 2022-02-28 |
Luke Kenneth Casso... | increase timescale of icarus simulation |
tree | commitdiff |
| 2022-02-28 |
Luke Kenneth Casso... | fix undefined uart_tx in icarus simulation, icarus... |
tree | commitdiff |
| 2022-02-28 |
Luke Kenneth Casso... | add icarus simulation of ls2 with DDR3 and ECP5 models |
tree | commitdiff |
| 2022-02-23 |
Luke Kenneth Casso... | invert CRG reset on PLL see if it makes any difference |
tree | commitdiff |
| 2022-02-23 |
Luke Kenneth Casso... | add comments about DRAM sync clock being identical... |
tree | commitdiff |
| 2022-02-22 |
Luke Kenneth Casso... | xdr=4 missing on ddr3 platform request for VERSA_ECP5 |
tree | commitdiff |
| 2022-02-21 |
Luke Kenneth Casso... | * use readl and writel for accessing memory |
tree | commitdiff |
| 2022-02-20 |
Luke Kenneth Casso... | for simulatio keep the simulated dram in the |
tree | commitdiff |
| 2022-02-20 |
Luke Kenneth Casso... | add fake (sim) DRAM from gram library |
tree | commitdiff |
| 2022-02-19 |
Luke Kenneth Casso... | match up dram initialisation parameters |
tree | commitdiff |
| 2022-02-19 |
Luke Kenneth Casso... | hm -abc9 seems to be working, and without -nowidelut |
tree | commitdiff |
| 2022-02-18 |
Luke Kenneth Casso... | add DRAM class to DDR3Soc |
tree | commitdiff |
| 2022-02-18 |
Luke Kenneth Casso... | add FPGA argument to DDR3SoC |
tree | commitdiff |
| 2022-02-18 |
Luke Kenneth Casso... | add microwatt console lib and #includes |
tree | commitdiff |
| 2022-02-18 |
Luke Kenneth Casso... | make cpu optional (test purposes), make bios optional, |
tree | commitdiff |
| 2022-02-16 |
Luke Kenneth Casso... | remove minerva cpu |
tree | commitdiff |
| 2022-02-16 |
Luke Kenneth Casso... | drop clock frequency to 25 mhz and disable abc9 (it... |
tree | commitdiff |
| 2022-02-16 |
Luke Kenneth Casso... | wildcards never ok. update comments |
tree | commitdiff |
| 2022-02-16 |
Luke Kenneth Casso... | add copyright notices |
tree | commitdiff |
| 2022-02-16 |
Luke Kenneth Casso... | update ECP5 PLL to accept parameters for setting arbitr... |
tree | commitdiff |
| 2022-02-16 |
Luke Kenneth Casso... | * add uart_pins to UART16550 peripheral so they get... |
tree | commitdiff |
| 2022-02-16 |
Luke Kenneth Casso... | * disable DDR3 for now |
tree | commitdiff |
| 2022-02-15 |
Luke Kenneth Casso... | connect up stall signals (fake) for WB Classic compliance |
tree | commitdiff |
| 2022-02-15 |
Luke Kenneth Casso... | alternative uart wishbone mapping which just takes... |
tree | commitdiff |
| 2022-02-15 |
Luke Kenneth Casso... | attempt to do 8-bit downconvert on wishbone bus for... |
tree | commitdiff |
| 2022-02-15 |
Luke Kenneth Casso... | correct syscon bus address to 0xC000_0000 |
tree | commitdiff |
| 2022-02-15 |
Luke Kenneth Casso... | add microwatt SYSCON peripheral at 0xc000_0000 |
tree | commitdiff |
| 2022-02-15 |
Luke Kenneth Casso... | increase size of bootmem |
tree | commitdiff |
| 2022-02-15 |
Luke Kenneth Casso... | add interrupt controller module, remove stall feature... |
tree | commitdiff |
| 2022-02-14 |
Luke Kenneth Casso... | add external cpu |
tree | commitdiff |
| 2022-02-14 |
Luke Kenneth Casso... | convert boot rom to bootmem and get first hello_world... |
tree | commitdiff |
| 2022-02-14 |
Luke Kenneth Casso... | add first cut of verilator simulation, over from microwatt |
tree | commitdiff |
| 2022-02-14 |
Luke Kenneth Casso... | add verilog build option, make DDR3 PHY optional, add... |
tree | commitdiff |
| 2022-02-13 |
Luke Kenneth Casso... | add future sim option (needs Simulated DDR PHY) |
tree | commitdiff |
| 2022-02-13 |
Luke Kenneth Casso... | rename examples to src |
tree | commitdiff |
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projects / ls2.git / history