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ac/radeonsi: add tcs_rel_ids to the abi
[mesa.git] / src / amd / common / ac_nir_to_llvm.c
1 /*
2 * Copyright © 2016 Bas Nieuwenhuizen
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 */
23
24 #include "ac_nir_to_llvm.h"
25 #include "ac_llvm_build.h"
26 #include "ac_llvm_util.h"
27 #include "ac_binary.h"
28 #include "sid.h"
29 #include "nir/nir.h"
30 #include "../vulkan/radv_descriptor_set.h"
31 #include "util/bitscan.h"
32 #include <llvm-c/Transforms/Scalar.h>
33 #include "ac_shader_abi.h"
34 #include "ac_shader_info.h"
35 #include "ac_shader_util.h"
36 #include "ac_exp_param.h"
37
38 enum radeon_llvm_calling_convention {
39 RADEON_LLVM_AMDGPU_VS = 87,
40 RADEON_LLVM_AMDGPU_GS = 88,
41 RADEON_LLVM_AMDGPU_PS = 89,
42 RADEON_LLVM_AMDGPU_CS = 90,
43 RADEON_LLVM_AMDGPU_HS = 93,
44 };
45
46 #define CONST_ADDR_SPACE 2
47 #define LOCAL_ADDR_SPACE 3
48
49 #define RADEON_LLVM_MAX_INPUTS (VARYING_SLOT_VAR31 + 1)
50 #define RADEON_LLVM_MAX_OUTPUTS (VARYING_SLOT_VAR31 + 1)
51
52 struct nir_to_llvm_context;
53
54 struct ac_nir_context {
55 struct ac_llvm_context ac;
56 struct ac_shader_abi *abi;
57
58 gl_shader_stage stage;
59
60 struct hash_table *defs;
61 struct hash_table *phis;
62 struct hash_table *vars;
63
64 LLVMValueRef main_function;
65 LLVMBasicBlockRef continue_block;
66 LLVMBasicBlockRef break_block;
67
68 LLVMValueRef outputs[RADEON_LLVM_MAX_OUTPUTS * 4];
69
70 int num_locals;
71 LLVMValueRef *locals;
72
73 struct nir_to_llvm_context *nctx; /* TODO get rid of this */
74 };
75
76 struct nir_to_llvm_context {
77 struct ac_llvm_context ac;
78 const struct ac_nir_compiler_options *options;
79 struct ac_shader_variant_info *shader_info;
80 struct ac_shader_abi abi;
81 struct ac_nir_context *nir;
82
83 unsigned max_workgroup_size;
84 LLVMContextRef context;
85 LLVMModuleRef module;
86 LLVMBuilderRef builder;
87 LLVMValueRef main_function;
88
89 struct hash_table *defs;
90 struct hash_table *phis;
91
92 LLVMValueRef descriptor_sets[AC_UD_MAX_SETS];
93 LLVMValueRef ring_offsets;
94 LLVMValueRef push_constants;
95 LLVMValueRef view_index;
96 LLVMValueRef num_work_groups;
97 LLVMValueRef workgroup_ids[3];
98 LLVMValueRef local_invocation_ids;
99 LLVMValueRef tg_size;
100
101 LLVMValueRef vertex_buffers;
102 LLVMValueRef rel_auto_id;
103 LLVMValueRef vs_prim_id;
104 LLVMValueRef ls_out_layout;
105 LLVMValueRef es2gs_offset;
106
107 LLVMValueRef tcs_offchip_layout;
108 LLVMValueRef tcs_out_offsets;
109 LLVMValueRef tcs_out_layout;
110 LLVMValueRef tcs_in_layout;
111 LLVMValueRef oc_lds;
112 LLVMValueRef merged_wave_info;
113 LLVMValueRef tess_factor_offset;
114 LLVMValueRef tes_rel_patch_id;
115 LLVMValueRef tes_u;
116 LLVMValueRef tes_v;
117
118 LLVMValueRef gsvs_ring_stride;
119 LLVMValueRef gsvs_num_entries;
120 LLVMValueRef gs2vs_offset;
121 LLVMValueRef gs_wave_id;
122 LLVMValueRef gs_vtx_offset[6];
123
124 LLVMValueRef esgs_ring;
125 LLVMValueRef gsvs_ring;
126 LLVMValueRef hs_ring_tess_offchip;
127 LLVMValueRef hs_ring_tess_factor;
128
129 LLVMValueRef prim_mask;
130 LLVMValueRef sample_pos_offset;
131 LLVMValueRef persp_sample, persp_center, persp_centroid;
132 LLVMValueRef linear_sample, linear_center, linear_centroid;
133
134 gl_shader_stage stage;
135
136 LLVMValueRef inputs[RADEON_LLVM_MAX_INPUTS * 4];
137
138 uint64_t input_mask;
139 uint64_t output_mask;
140 uint8_t num_output_clips;
141 uint8_t num_output_culls;
142
143 bool is_gs_copy_shader;
144 LLVMValueRef gs_next_vertex;
145 unsigned gs_max_out_vertices;
146
147 unsigned tes_primitive_mode;
148 uint64_t tess_outputs_written;
149 uint64_t tess_patch_outputs_written;
150
151 uint32_t tcs_patch_outputs_read;
152 uint64_t tcs_outputs_read;
153 };
154
155 static inline struct nir_to_llvm_context *
156 nir_to_llvm_context_from_abi(struct ac_shader_abi *abi)
157 {
158 struct nir_to_llvm_context *ctx = NULL;
159 return container_of(abi, ctx, abi);
160 }
161
162 static LLVMTypeRef
163 nir2llvmtype(struct ac_nir_context *ctx,
164 const struct glsl_type *type)
165 {
166 switch (glsl_get_base_type(glsl_without_array(type))) {
167 case GLSL_TYPE_UINT:
168 case GLSL_TYPE_INT:
169 return ctx->ac.i32;
170 case GLSL_TYPE_UINT64:
171 case GLSL_TYPE_INT64:
172 return ctx->ac.i64;
173 case GLSL_TYPE_DOUBLE:
174 return ctx->ac.f64;
175 case GLSL_TYPE_FLOAT:
176 return ctx->ac.f32;
177 default:
178 assert(!"Unsupported type in nir2llvmtype()");
179 break;
180 }
181 return 0;
182 }
183
184 static LLVMValueRef get_sampler_desc(struct ac_nir_context *ctx,
185 const nir_deref_var *deref,
186 enum ac_descriptor_type desc_type,
187 const nir_tex_instr *instr,
188 bool image, bool write);
189
190 static unsigned radeon_llvm_reg_index_soa(unsigned index, unsigned chan)
191 {
192 return (index * 4) + chan;
193 }
194
195 static unsigned shader_io_get_unique_index(gl_varying_slot slot)
196 {
197 /* handle patch indices separate */
198 if (slot == VARYING_SLOT_TESS_LEVEL_OUTER)
199 return 0;
200 if (slot == VARYING_SLOT_TESS_LEVEL_INNER)
201 return 1;
202 if (slot >= VARYING_SLOT_PATCH0 && slot <= VARYING_SLOT_TESS_MAX)
203 return 2 + (slot - VARYING_SLOT_PATCH0);
204
205 if (slot == VARYING_SLOT_POS)
206 return 0;
207 if (slot == VARYING_SLOT_PSIZ)
208 return 1;
209 if (slot == VARYING_SLOT_CLIP_DIST0)
210 return 2;
211 /* 3 is reserved for clip dist as well */
212 if (slot >= VARYING_SLOT_VAR0 && slot <= VARYING_SLOT_VAR31)
213 return 4 + (slot - VARYING_SLOT_VAR0);
214 unreachable("illegal slot in get unique index\n");
215 }
216
217 static void set_llvm_calling_convention(LLVMValueRef func,
218 gl_shader_stage stage)
219 {
220 enum radeon_llvm_calling_convention calling_conv;
221
222 switch (stage) {
223 case MESA_SHADER_VERTEX:
224 case MESA_SHADER_TESS_EVAL:
225 calling_conv = RADEON_LLVM_AMDGPU_VS;
226 break;
227 case MESA_SHADER_GEOMETRY:
228 calling_conv = RADEON_LLVM_AMDGPU_GS;
229 break;
230 case MESA_SHADER_TESS_CTRL:
231 calling_conv = HAVE_LLVM >= 0x0500 ? RADEON_LLVM_AMDGPU_HS : RADEON_LLVM_AMDGPU_VS;
232 break;
233 case MESA_SHADER_FRAGMENT:
234 calling_conv = RADEON_LLVM_AMDGPU_PS;
235 break;
236 case MESA_SHADER_COMPUTE:
237 calling_conv = RADEON_LLVM_AMDGPU_CS;
238 break;
239 default:
240 unreachable("Unhandle shader type");
241 }
242
243 LLVMSetFunctionCallConv(func, calling_conv);
244 }
245
246 #define MAX_ARGS 23
247 struct arg_info {
248 LLVMTypeRef types[MAX_ARGS];
249 LLVMValueRef *assign[MAX_ARGS];
250 unsigned array_params_mask;
251 uint8_t count;
252 uint8_t sgpr_count;
253 uint8_t num_sgprs_used;
254 uint8_t num_vgprs_used;
255 };
256
257 enum ac_arg_regfile {
258 ARG_SGPR,
259 ARG_VGPR,
260 };
261
262 static void
263 add_arg(struct arg_info *info, enum ac_arg_regfile regfile, LLVMTypeRef type,
264 LLVMValueRef *param_ptr)
265 {
266 assert(info->count < MAX_ARGS);
267
268 info->assign[info->count] = param_ptr;
269 info->types[info->count] = type;
270 info->count++;
271
272 if (regfile == ARG_SGPR) {
273 info->num_sgprs_used += ac_get_type_size(type) / 4;
274 info->sgpr_count++;
275 } else {
276 assert(regfile == ARG_VGPR);
277 info->num_vgprs_used += ac_get_type_size(type) / 4;
278 }
279 }
280
281 static inline void
282 add_array_arg(struct arg_info *info, LLVMTypeRef type, LLVMValueRef *param_ptr)
283 {
284 info->array_params_mask |= (1 << info->count);
285 add_arg(info, ARG_SGPR, type, param_ptr);
286 }
287
288 static void assign_arguments(LLVMValueRef main_function,
289 struct arg_info *info)
290 {
291 unsigned i;
292 for (i = 0; i < info->count; i++) {
293 if (info->assign[i])
294 *info->assign[i] = LLVMGetParam(main_function, i);
295 }
296 }
297
298 static LLVMValueRef
299 create_llvm_function(LLVMContextRef ctx, LLVMModuleRef module,
300 LLVMBuilderRef builder, LLVMTypeRef *return_types,
301 unsigned num_return_elems,
302 struct arg_info *args,
303 unsigned max_workgroup_size,
304 bool unsafe_math)
305 {
306 LLVMTypeRef main_function_type, ret_type;
307 LLVMBasicBlockRef main_function_body;
308
309 if (num_return_elems)
310 ret_type = LLVMStructTypeInContext(ctx, return_types,
311 num_return_elems, true);
312 else
313 ret_type = LLVMVoidTypeInContext(ctx);
314
315 /* Setup the function */
316 main_function_type =
317 LLVMFunctionType(ret_type, args->types, args->count, 0);
318 LLVMValueRef main_function =
319 LLVMAddFunction(module, "main", main_function_type);
320 main_function_body =
321 LLVMAppendBasicBlockInContext(ctx, main_function, "main_body");
322 LLVMPositionBuilderAtEnd(builder, main_function_body);
323
324 LLVMSetFunctionCallConv(main_function, RADEON_LLVM_AMDGPU_CS);
325 for (unsigned i = 0; i < args->sgpr_count; ++i) {
326 if (args->array_params_mask & (1 << i)) {
327 LLVMValueRef P = LLVMGetParam(main_function, i);
328 ac_add_function_attr(ctx, main_function, i + 1, AC_FUNC_ATTR_BYVAL);
329 ac_add_attr_dereferenceable(P, UINT64_MAX);
330 }
331 else {
332 ac_add_function_attr(ctx, main_function, i + 1, AC_FUNC_ATTR_INREG);
333 }
334 }
335
336 if (max_workgroup_size) {
337 ac_llvm_add_target_dep_function_attr(main_function,
338 "amdgpu-max-work-group-size",
339 max_workgroup_size);
340 }
341 if (unsafe_math) {
342 /* These were copied from some LLVM test. */
343 LLVMAddTargetDependentFunctionAttr(main_function,
344 "less-precise-fpmad",
345 "true");
346 LLVMAddTargetDependentFunctionAttr(main_function,
347 "no-infs-fp-math",
348 "true");
349 LLVMAddTargetDependentFunctionAttr(main_function,
350 "no-nans-fp-math",
351 "true");
352 LLVMAddTargetDependentFunctionAttr(main_function,
353 "unsafe-fp-math",
354 "true");
355 }
356 return main_function;
357 }
358
359 static LLVMTypeRef const_array(LLVMTypeRef elem_type, int num_elements)
360 {
361 return LLVMPointerType(LLVMArrayType(elem_type, num_elements),
362 CONST_ADDR_SPACE);
363 }
364
365 static int get_elem_bits(struct ac_llvm_context *ctx, LLVMTypeRef type)
366 {
367 if (LLVMGetTypeKind(type) == LLVMVectorTypeKind)
368 type = LLVMGetElementType(type);
369
370 if (LLVMGetTypeKind(type) == LLVMIntegerTypeKind)
371 return LLVMGetIntTypeWidth(type);
372
373 if (type == ctx->f16)
374 return 16;
375 if (type == ctx->f32)
376 return 32;
377 if (type == ctx->f64)
378 return 64;
379
380 unreachable("Unhandled type kind in get_elem_bits");
381 }
382
383 static LLVMValueRef unpack_param(struct ac_llvm_context *ctx,
384 LLVMValueRef param, unsigned rshift,
385 unsigned bitwidth)
386 {
387 LLVMValueRef value = param;
388 if (rshift)
389 value = LLVMBuildLShr(ctx->builder, value,
390 LLVMConstInt(ctx->i32, rshift, false), "");
391
392 if (rshift + bitwidth < 32) {
393 unsigned mask = (1 << bitwidth) - 1;
394 value = LLVMBuildAnd(ctx->builder, value,
395 LLVMConstInt(ctx->i32, mask, false), "");
396 }
397 return value;
398 }
399
400 static LLVMValueRef get_rel_patch_id(struct nir_to_llvm_context *ctx)
401 {
402 switch (ctx->stage) {
403 case MESA_SHADER_TESS_CTRL:
404 return unpack_param(&ctx->ac, ctx->abi.tcs_rel_ids, 0, 8);
405 case MESA_SHADER_TESS_EVAL:
406 return ctx->tes_rel_patch_id;
407 break;
408 default:
409 unreachable("Illegal stage");
410 }
411 }
412
413 /* Tessellation shaders pass outputs to the next shader using LDS.
414 *
415 * LS outputs = TCS inputs
416 * TCS outputs = TES inputs
417 *
418 * The LDS layout is:
419 * - TCS inputs for patch 0
420 * - TCS inputs for patch 1
421 * - TCS inputs for patch 2 = get_tcs_in_current_patch_offset (if RelPatchID==2)
422 * - ...
423 * - TCS outputs for patch 0 = get_tcs_out_patch0_offset
424 * - Per-patch TCS outputs for patch 0 = get_tcs_out_patch0_patch_data_offset
425 * - TCS outputs for patch 1
426 * - Per-patch TCS outputs for patch 1
427 * - TCS outputs for patch 2 = get_tcs_out_current_patch_offset (if RelPatchID==2)
428 * - Per-patch TCS outputs for patch 2 = get_tcs_out_current_patch_data_offset (if RelPatchID==2)
429 * - ...
430 *
431 * All three shaders VS(LS), TCS, TES share the same LDS space.
432 */
433 static LLVMValueRef
434 get_tcs_in_patch_stride(struct nir_to_llvm_context *ctx)
435 {
436 if (ctx->stage == MESA_SHADER_VERTEX)
437 return unpack_param(&ctx->ac, ctx->ls_out_layout, 0, 13);
438 else if (ctx->stage == MESA_SHADER_TESS_CTRL)
439 return unpack_param(&ctx->ac, ctx->tcs_in_layout, 0, 13);
440 else {
441 assert(0);
442 return NULL;
443 }
444 }
445
446 static LLVMValueRef
447 get_tcs_out_patch_stride(struct nir_to_llvm_context *ctx)
448 {
449 return unpack_param(&ctx->ac, ctx->tcs_out_layout, 0, 13);
450 }
451
452 static LLVMValueRef
453 get_tcs_out_patch0_offset(struct nir_to_llvm_context *ctx)
454 {
455 return LLVMBuildMul(ctx->builder,
456 unpack_param(&ctx->ac, ctx->tcs_out_offsets, 0, 16),
457 LLVMConstInt(ctx->ac.i32, 4, false), "");
458 }
459
460 static LLVMValueRef
461 get_tcs_out_patch0_patch_data_offset(struct nir_to_llvm_context *ctx)
462 {
463 return LLVMBuildMul(ctx->builder,
464 unpack_param(&ctx->ac, ctx->tcs_out_offsets, 16, 16),
465 LLVMConstInt(ctx->ac.i32, 4, false), "");
466 }
467
468 static LLVMValueRef
469 get_tcs_in_current_patch_offset(struct nir_to_llvm_context *ctx)
470 {
471 LLVMValueRef patch_stride = get_tcs_in_patch_stride(ctx);
472 LLVMValueRef rel_patch_id = get_rel_patch_id(ctx);
473
474 return LLVMBuildMul(ctx->builder, patch_stride, rel_patch_id, "");
475 }
476
477 static LLVMValueRef
478 get_tcs_out_current_patch_offset(struct nir_to_llvm_context *ctx)
479 {
480 LLVMValueRef patch0_offset = get_tcs_out_patch0_offset(ctx);
481 LLVMValueRef patch_stride = get_tcs_out_patch_stride(ctx);
482 LLVMValueRef rel_patch_id = get_rel_patch_id(ctx);
483
484 return LLVMBuildAdd(ctx->builder, patch0_offset,
485 LLVMBuildMul(ctx->builder, patch_stride,
486 rel_patch_id, ""),
487 "");
488 }
489
490 static LLVMValueRef
491 get_tcs_out_current_patch_data_offset(struct nir_to_llvm_context *ctx)
492 {
493 LLVMValueRef patch0_patch_data_offset =
494 get_tcs_out_patch0_patch_data_offset(ctx);
495 LLVMValueRef patch_stride = get_tcs_out_patch_stride(ctx);
496 LLVMValueRef rel_patch_id = get_rel_patch_id(ctx);
497
498 return LLVMBuildAdd(ctx->builder, patch0_patch_data_offset,
499 LLVMBuildMul(ctx->builder, patch_stride,
500 rel_patch_id, ""),
501 "");
502 }
503
504 static void
505 set_loc(struct ac_userdata_info *ud_info, uint8_t *sgpr_idx, uint8_t num_sgprs,
506 uint32_t indirect_offset)
507 {
508 ud_info->sgpr_idx = *sgpr_idx;
509 ud_info->num_sgprs = num_sgprs;
510 ud_info->indirect = indirect_offset > 0;
511 ud_info->indirect_offset = indirect_offset;
512 *sgpr_idx += num_sgprs;
513 }
514
515 static void
516 set_loc_shader(struct nir_to_llvm_context *ctx, int idx, uint8_t *sgpr_idx,
517 uint8_t num_sgprs)
518 {
519 struct ac_userdata_info *ud_info =
520 &ctx->shader_info->user_sgprs_locs.shader_data[idx];
521 assert(ud_info);
522
523 set_loc(ud_info, sgpr_idx, num_sgprs, 0);
524 }
525
526 static void
527 set_loc_desc(struct nir_to_llvm_context *ctx, int idx, uint8_t *sgpr_idx,
528 uint32_t indirect_offset)
529 {
530 struct ac_userdata_info *ud_info =
531 &ctx->shader_info->user_sgprs_locs.descriptor_sets[idx];
532 assert(ud_info);
533
534 set_loc(ud_info, sgpr_idx, 2, indirect_offset);
535 }
536
537 struct user_sgpr_info {
538 bool need_ring_offsets;
539 uint8_t sgpr_count;
540 bool indirect_all_descriptor_sets;
541 };
542
543 static void allocate_user_sgprs(struct nir_to_llvm_context *ctx,
544 struct user_sgpr_info *user_sgpr_info)
545 {
546 memset(user_sgpr_info, 0, sizeof(struct user_sgpr_info));
547
548 /* until we sort out scratch/global buffers always assign ring offsets for gs/vs/es */
549 if (ctx->stage == MESA_SHADER_GEOMETRY ||
550 ctx->stage == MESA_SHADER_VERTEX ||
551 ctx->stage == MESA_SHADER_TESS_CTRL ||
552 ctx->stage == MESA_SHADER_TESS_EVAL ||
553 ctx->is_gs_copy_shader)
554 user_sgpr_info->need_ring_offsets = true;
555
556 if (ctx->stage == MESA_SHADER_FRAGMENT &&
557 ctx->shader_info->info.ps.needs_sample_positions)
558 user_sgpr_info->need_ring_offsets = true;
559
560 /* 2 user sgprs will nearly always be allocated for scratch/rings */
561 if (ctx->options->supports_spill || user_sgpr_info->need_ring_offsets) {
562 user_sgpr_info->sgpr_count += 2;
563 }
564
565 switch (ctx->stage) {
566 case MESA_SHADER_COMPUTE:
567 if (ctx->shader_info->info.cs.uses_grid_size)
568 user_sgpr_info->sgpr_count += 3;
569 break;
570 case MESA_SHADER_FRAGMENT:
571 user_sgpr_info->sgpr_count += ctx->shader_info->info.ps.needs_sample_positions;
572 break;
573 case MESA_SHADER_VERTEX:
574 if (!ctx->is_gs_copy_shader) {
575 user_sgpr_info->sgpr_count += ctx->shader_info->info.vs.has_vertex_buffers ? 2 : 0;
576 if (ctx->shader_info->info.vs.needs_draw_id) {
577 user_sgpr_info->sgpr_count += 3;
578 } else {
579 user_sgpr_info->sgpr_count += 2;
580 }
581 }
582 if (ctx->options->key.vs.as_ls)
583 user_sgpr_info->sgpr_count++;
584 break;
585 case MESA_SHADER_TESS_CTRL:
586 user_sgpr_info->sgpr_count += 4;
587 break;
588 case MESA_SHADER_TESS_EVAL:
589 user_sgpr_info->sgpr_count += 1;
590 break;
591 case MESA_SHADER_GEOMETRY:
592 user_sgpr_info->sgpr_count += 2;
593 break;
594 default:
595 break;
596 }
597
598 if (ctx->shader_info->info.needs_push_constants)
599 user_sgpr_info->sgpr_count += 2;
600
601 uint32_t remaining_sgprs = 16 - user_sgpr_info->sgpr_count;
602 if (remaining_sgprs / 2 < util_bitcount(ctx->shader_info->info.desc_set_used_mask)) {
603 user_sgpr_info->sgpr_count += 2;
604 user_sgpr_info->indirect_all_descriptor_sets = true;
605 } else {
606 user_sgpr_info->sgpr_count += util_bitcount(ctx->shader_info->info.desc_set_used_mask) * 2;
607 }
608 }
609
610 static void
611 declare_global_input_sgprs(struct nir_to_llvm_context *ctx,
612 gl_shader_stage stage,
613 bool has_previous_stage,
614 gl_shader_stage previous_stage,
615 const struct user_sgpr_info *user_sgpr_info,
616 struct arg_info *args,
617 LLVMValueRef *desc_sets)
618 {
619 LLVMTypeRef type = const_array(ctx->ac.i8, 1024 * 1024);
620 unsigned num_sets = ctx->options->layout ?
621 ctx->options->layout->num_sets : 0;
622 unsigned stage_mask = 1 << stage;
623
624 if (has_previous_stage)
625 stage_mask |= 1 << previous_stage;
626
627 /* 1 for each descriptor set */
628 if (!user_sgpr_info->indirect_all_descriptor_sets) {
629 for (unsigned i = 0; i < num_sets; ++i) {
630 if (ctx->options->layout->set[i].layout->shader_stages & stage_mask) {
631 add_array_arg(args, type,
632 &ctx->descriptor_sets[i]);
633 }
634 }
635 } else {
636 add_array_arg(args, const_array(type, 32), desc_sets);
637 }
638
639 if (ctx->shader_info->info.needs_push_constants) {
640 /* 1 for push constants and dynamic descriptors */
641 add_array_arg(args, type, &ctx->push_constants);
642 }
643 }
644
645 static void
646 declare_vs_specific_input_sgprs(struct nir_to_llvm_context *ctx,
647 gl_shader_stage stage,
648 bool has_previous_stage,
649 gl_shader_stage previous_stage,
650 struct arg_info *args)
651 {
652 if (!ctx->is_gs_copy_shader &&
653 (stage == MESA_SHADER_VERTEX ||
654 (has_previous_stage && previous_stage == MESA_SHADER_VERTEX))) {
655 if (ctx->shader_info->info.vs.has_vertex_buffers) {
656 add_arg(args, ARG_SGPR, const_array(ctx->ac.v4i32, 16),
657 &ctx->vertex_buffers);
658 }
659 add_arg(args, ARG_SGPR, ctx->ac.i32, &ctx->abi.base_vertex);
660 add_arg(args, ARG_SGPR, ctx->ac.i32, &ctx->abi.start_instance);
661 if (ctx->shader_info->info.vs.needs_draw_id) {
662 add_arg(args, ARG_SGPR, ctx->ac.i32, &ctx->abi.draw_id);
663 }
664 }
665 }
666
667 static void
668 declare_vs_input_vgprs(struct nir_to_llvm_context *ctx, struct arg_info *args)
669 {
670 add_arg(args, ARG_VGPR, ctx->ac.i32, &ctx->abi.vertex_id);
671 if (!ctx->is_gs_copy_shader) {
672 add_arg(args, ARG_VGPR, ctx->ac.i32, &ctx->rel_auto_id);
673 add_arg(args, ARG_VGPR, ctx->ac.i32, &ctx->vs_prim_id);
674 add_arg(args, ARG_VGPR, ctx->ac.i32, &ctx->abi.instance_id);
675 }
676 }
677
678 static void
679 declare_tes_input_vgprs(struct nir_to_llvm_context *ctx, struct arg_info *args)
680 {
681 add_arg(args, ARG_VGPR, ctx->ac.f32, &ctx->tes_u);
682 add_arg(args, ARG_VGPR, ctx->ac.f32, &ctx->tes_v);
683 add_arg(args, ARG_VGPR, ctx->ac.i32, &ctx->tes_rel_patch_id);
684 add_arg(args, ARG_VGPR, ctx->ac.i32, &ctx->abi.tes_patch_id);
685 }
686
687 static void
688 set_global_input_locs(struct nir_to_llvm_context *ctx, gl_shader_stage stage,
689 bool has_previous_stage, gl_shader_stage previous_stage,
690 const struct user_sgpr_info *user_sgpr_info,
691 LLVMValueRef desc_sets, uint8_t *user_sgpr_idx)
692 {
693 unsigned num_sets = ctx->options->layout ?
694 ctx->options->layout->num_sets : 0;
695 unsigned stage_mask = 1 << stage;
696
697 if (has_previous_stage)
698 stage_mask |= 1 << previous_stage;
699
700 if (!user_sgpr_info->indirect_all_descriptor_sets) {
701 for (unsigned i = 0; i < num_sets; ++i) {
702 if (ctx->options->layout->set[i].layout->shader_stages & stage_mask) {
703 set_loc_desc(ctx, i, user_sgpr_idx, 0);
704 } else
705 ctx->descriptor_sets[i] = NULL;
706 }
707 } else {
708 set_loc_shader(ctx, AC_UD_INDIRECT_DESCRIPTOR_SETS,
709 user_sgpr_idx, 2);
710
711 for (unsigned i = 0; i < num_sets; ++i) {
712 if (ctx->options->layout->set[i].layout->shader_stages & stage_mask) {
713 set_loc_desc(ctx, i, user_sgpr_idx, i * 8);
714 ctx->descriptor_sets[i] =
715 ac_build_load_to_sgpr(&ctx->ac,
716 desc_sets,
717 LLVMConstInt(ctx->ac.i32, i, false));
718
719 } else
720 ctx->descriptor_sets[i] = NULL;
721 }
722 ctx->shader_info->need_indirect_descriptor_sets = true;
723 }
724
725 if (ctx->shader_info->info.needs_push_constants) {
726 set_loc_shader(ctx, AC_UD_PUSH_CONSTANTS, user_sgpr_idx, 2);
727 }
728 }
729
730 static void
731 set_vs_specific_input_locs(struct nir_to_llvm_context *ctx,
732 gl_shader_stage stage, bool has_previous_stage,
733 gl_shader_stage previous_stage,
734 uint8_t *user_sgpr_idx)
735 {
736 if (!ctx->is_gs_copy_shader &&
737 (stage == MESA_SHADER_VERTEX ||
738 (has_previous_stage && previous_stage == MESA_SHADER_VERTEX))) {
739 if (ctx->shader_info->info.vs.has_vertex_buffers) {
740 set_loc_shader(ctx, AC_UD_VS_VERTEX_BUFFERS,
741 user_sgpr_idx, 2);
742 }
743
744 unsigned vs_num = 2;
745 if (ctx->shader_info->info.vs.needs_draw_id)
746 vs_num++;
747
748 set_loc_shader(ctx, AC_UD_VS_BASE_VERTEX_START_INSTANCE,
749 user_sgpr_idx, vs_num);
750 }
751 }
752
753 static void create_function(struct nir_to_llvm_context *ctx,
754 gl_shader_stage stage,
755 bool has_previous_stage,
756 gl_shader_stage previous_stage)
757 {
758 uint8_t user_sgpr_idx;
759 struct user_sgpr_info user_sgpr_info;
760 struct arg_info args = {};
761 LLVMValueRef desc_sets;
762
763 allocate_user_sgprs(ctx, &user_sgpr_info);
764
765 if (user_sgpr_info.need_ring_offsets && !ctx->options->supports_spill) {
766 add_arg(&args, ARG_SGPR, const_array(ctx->ac.v4i32, 16),
767 &ctx->ring_offsets);
768 }
769
770 switch (stage) {
771 case MESA_SHADER_COMPUTE:
772 declare_global_input_sgprs(ctx, stage, has_previous_stage,
773 previous_stage, &user_sgpr_info,
774 &args, &desc_sets);
775
776 if (ctx->shader_info->info.cs.uses_grid_size) {
777 add_arg(&args, ARG_SGPR, ctx->ac.v3i32,
778 &ctx->num_work_groups);
779 }
780
781 for (int i = 0; i < 3; i++) {
782 ctx->workgroup_ids[i] = NULL;
783 if (ctx->shader_info->info.cs.uses_block_id[i]) {
784 add_arg(&args, ARG_SGPR, ctx->ac.i32,
785 &ctx->workgroup_ids[i]);
786 }
787 }
788
789 if (ctx->shader_info->info.cs.uses_local_invocation_idx)
790 add_arg(&args, ARG_SGPR, ctx->ac.i32, &ctx->tg_size);
791 add_arg(&args, ARG_VGPR, ctx->ac.v3i32,
792 &ctx->local_invocation_ids);
793 break;
794 case MESA_SHADER_VERTEX:
795 declare_global_input_sgprs(ctx, stage, has_previous_stage,
796 previous_stage, &user_sgpr_info,
797 &args, &desc_sets);
798 declare_vs_specific_input_sgprs(ctx, stage, has_previous_stage,
799 previous_stage, &args);
800
801 if (ctx->shader_info->info.needs_multiview_view_index || (!ctx->options->key.vs.as_es && !ctx->options->key.vs.as_ls && ctx->options->key.has_multiview_view_index))
802 add_arg(&args, ARG_SGPR, ctx->ac.i32, &ctx->view_index);
803 if (ctx->options->key.vs.as_es)
804 add_arg(&args, ARG_SGPR, ctx->ac.i32,
805 &ctx->es2gs_offset);
806 else if (ctx->options->key.vs.as_ls)
807 add_arg(&args, ARG_SGPR, ctx->ac.i32,
808 &ctx->ls_out_layout);
809
810 declare_vs_input_vgprs(ctx, &args);
811 break;
812 case MESA_SHADER_TESS_CTRL:
813 if (has_previous_stage) {
814 // First 6 system regs
815 add_arg(&args, ARG_SGPR, ctx->ac.i32, &ctx->oc_lds);
816 add_arg(&args, ARG_SGPR, ctx->ac.i32,
817 &ctx->merged_wave_info);
818 add_arg(&args, ARG_SGPR, ctx->ac.i32,
819 &ctx->tess_factor_offset);
820
821 add_arg(&args, ARG_SGPR, ctx->ac.i32, NULL); // scratch offset
822 add_arg(&args, ARG_SGPR, ctx->ac.i32, NULL); // unknown
823 add_arg(&args, ARG_SGPR, ctx->ac.i32, NULL); // unknown
824
825 declare_global_input_sgprs(ctx, stage,
826 has_previous_stage,
827 previous_stage,
828 &user_sgpr_info, &args,
829 &desc_sets);
830 declare_vs_specific_input_sgprs(ctx, stage,
831 has_previous_stage,
832 previous_stage, &args);
833
834 add_arg(&args, ARG_SGPR, ctx->ac.i32,
835 &ctx->ls_out_layout);
836
837 add_arg(&args, ARG_SGPR, ctx->ac.i32,
838 &ctx->tcs_offchip_layout);
839 add_arg(&args, ARG_SGPR, ctx->ac.i32,
840 &ctx->tcs_out_offsets);
841 add_arg(&args, ARG_SGPR, ctx->ac.i32,
842 &ctx->tcs_out_layout);
843 add_arg(&args, ARG_SGPR, ctx->ac.i32,
844 &ctx->tcs_in_layout);
845 if (ctx->shader_info->info.needs_multiview_view_index)
846 add_arg(&args, ARG_SGPR, ctx->ac.i32,
847 &ctx->view_index);
848
849 add_arg(&args, ARG_VGPR, ctx->ac.i32,
850 &ctx->abi.tcs_patch_id);
851 add_arg(&args, ARG_VGPR, ctx->ac.i32,
852 &ctx->abi.tcs_rel_ids);
853
854 declare_vs_input_vgprs(ctx, &args);
855 } else {
856 declare_global_input_sgprs(ctx, stage,
857 has_previous_stage,
858 previous_stage,
859 &user_sgpr_info, &args,
860 &desc_sets);
861
862 add_arg(&args, ARG_SGPR, ctx->ac.i32,
863 &ctx->tcs_offchip_layout);
864 add_arg(&args, ARG_SGPR, ctx->ac.i32,
865 &ctx->tcs_out_offsets);
866 add_arg(&args, ARG_SGPR, ctx->ac.i32,
867 &ctx->tcs_out_layout);
868 add_arg(&args, ARG_SGPR, ctx->ac.i32,
869 &ctx->tcs_in_layout);
870 if (ctx->shader_info->info.needs_multiview_view_index)
871 add_arg(&args, ARG_SGPR, ctx->ac.i32,
872 &ctx->view_index);
873
874 add_arg(&args, ARG_SGPR, ctx->ac.i32, &ctx->oc_lds);
875 add_arg(&args, ARG_SGPR, ctx->ac.i32,
876 &ctx->tess_factor_offset);
877 add_arg(&args, ARG_VGPR, ctx->ac.i32,
878 &ctx->abi.tcs_patch_id);
879 add_arg(&args, ARG_VGPR, ctx->ac.i32,
880 &ctx->abi.tcs_rel_ids);
881 }
882 break;
883 case MESA_SHADER_TESS_EVAL:
884 declare_global_input_sgprs(ctx, stage, has_previous_stage,
885 previous_stage, &user_sgpr_info,
886 &args, &desc_sets);
887
888 add_arg(&args, ARG_SGPR, ctx->ac.i32, &ctx->tcs_offchip_layout);
889 if (ctx->shader_info->info.needs_multiview_view_index || (!ctx->options->key.tes.as_es && ctx->options->key.has_multiview_view_index))
890 add_arg(&args, ARG_SGPR, ctx->ac.i32, &ctx->view_index);
891
892 if (ctx->options->key.tes.as_es) {
893 add_arg(&args, ARG_SGPR, ctx->ac.i32, &ctx->oc_lds);
894 add_arg(&args, ARG_SGPR, ctx->ac.i32, NULL);
895 add_arg(&args, ARG_SGPR, ctx->ac.i32,
896 &ctx->es2gs_offset);
897 } else {
898 add_arg(&args, ARG_SGPR, ctx->ac.i32, NULL);
899 add_arg(&args, ARG_SGPR, ctx->ac.i32, &ctx->oc_lds);
900 }
901 declare_tes_input_vgprs(ctx, &args);
902 break;
903 case MESA_SHADER_GEOMETRY:
904 if (has_previous_stage) {
905 // First 6 system regs
906 add_arg(&args, ARG_SGPR, ctx->ac.i32,
907 &ctx->gs2vs_offset);
908 add_arg(&args, ARG_SGPR, ctx->ac.i32,
909 &ctx->merged_wave_info);
910 add_arg(&args, ARG_SGPR, ctx->ac.i32, &ctx->oc_lds);
911
912 add_arg(&args, ARG_SGPR, ctx->ac.i32, NULL); // scratch offset
913 add_arg(&args, ARG_SGPR, ctx->ac.i32, NULL); // unknown
914 add_arg(&args, ARG_SGPR, ctx->ac.i32, NULL); // unknown
915
916 declare_global_input_sgprs(ctx, stage,
917 has_previous_stage,
918 previous_stage,
919 &user_sgpr_info, &args,
920 &desc_sets);
921
922 if (previous_stage == MESA_SHADER_TESS_EVAL) {
923 add_arg(&args, ARG_SGPR, ctx->ac.i32,
924 &ctx->tcs_offchip_layout);
925 } else {
926 declare_vs_specific_input_sgprs(ctx, stage,
927 has_previous_stage,
928 previous_stage,
929 &args);
930 }
931
932 add_arg(&args, ARG_SGPR, ctx->ac.i32,
933 &ctx->gsvs_ring_stride);
934 add_arg(&args, ARG_SGPR, ctx->ac.i32,
935 &ctx->gsvs_num_entries);
936 if (ctx->shader_info->info.needs_multiview_view_index)
937 add_arg(&args, ARG_SGPR, ctx->ac.i32,
938 &ctx->view_index);
939
940 add_arg(&args, ARG_VGPR, ctx->ac.i32,
941 &ctx->gs_vtx_offset[0]);
942 add_arg(&args, ARG_VGPR, ctx->ac.i32,
943 &ctx->gs_vtx_offset[2]);
944 add_arg(&args, ARG_VGPR, ctx->ac.i32,
945 &ctx->abi.gs_prim_id);
946 add_arg(&args, ARG_VGPR, ctx->ac.i32,
947 &ctx->abi.gs_invocation_id);
948 add_arg(&args, ARG_VGPR, ctx->ac.i32,
949 &ctx->gs_vtx_offset[4]);
950
951 if (previous_stage == MESA_SHADER_VERTEX) {
952 declare_vs_input_vgprs(ctx, &args);
953 } else {
954 declare_tes_input_vgprs(ctx, &args);
955 }
956 } else {
957 declare_global_input_sgprs(ctx, stage,
958 has_previous_stage,
959 previous_stage,
960 &user_sgpr_info, &args,
961 &desc_sets);
962
963 add_arg(&args, ARG_SGPR, ctx->ac.i32,
964 &ctx->gsvs_ring_stride);
965 add_arg(&args, ARG_SGPR, ctx->ac.i32,
966 &ctx->gsvs_num_entries);
967 if (ctx->shader_info->info.needs_multiview_view_index)
968 add_arg(&args, ARG_SGPR, ctx->ac.i32,
969 &ctx->view_index);
970
971 add_arg(&args, ARG_SGPR, ctx->ac.i32, &ctx->gs2vs_offset);
972 add_arg(&args, ARG_SGPR, ctx->ac.i32, &ctx->gs_wave_id);
973 add_arg(&args, ARG_VGPR, ctx->ac.i32,
974 &ctx->gs_vtx_offset[0]);
975 add_arg(&args, ARG_VGPR, ctx->ac.i32,
976 &ctx->gs_vtx_offset[1]);
977 add_arg(&args, ARG_VGPR, ctx->ac.i32,
978 &ctx->abi.gs_prim_id);
979 add_arg(&args, ARG_VGPR, ctx->ac.i32,
980 &ctx->gs_vtx_offset[2]);
981 add_arg(&args, ARG_VGPR, ctx->ac.i32,
982 &ctx->gs_vtx_offset[3]);
983 add_arg(&args, ARG_VGPR, ctx->ac.i32,
984 &ctx->gs_vtx_offset[4]);
985 add_arg(&args, ARG_VGPR, ctx->ac.i32,
986 &ctx->gs_vtx_offset[5]);
987 add_arg(&args, ARG_VGPR, ctx->ac.i32,
988 &ctx->abi.gs_invocation_id);
989 }
990 break;
991 case MESA_SHADER_FRAGMENT:
992 declare_global_input_sgprs(ctx, stage, has_previous_stage,
993 previous_stage, &user_sgpr_info,
994 &args, &desc_sets);
995
996 if (ctx->shader_info->info.ps.needs_sample_positions)
997 add_arg(&args, ARG_SGPR, ctx->ac.i32,
998 &ctx->sample_pos_offset);
999
1000 add_arg(&args, ARG_SGPR, ctx->ac.i32, &ctx->prim_mask);
1001 add_arg(&args, ARG_VGPR, ctx->ac.v2i32, &ctx->persp_sample);
1002 add_arg(&args, ARG_VGPR, ctx->ac.v2i32, &ctx->persp_center);
1003 add_arg(&args, ARG_VGPR, ctx->ac.v2i32, &ctx->persp_centroid);
1004 add_arg(&args, ARG_VGPR, ctx->ac.v3i32, NULL); /* persp pull model */
1005 add_arg(&args, ARG_VGPR, ctx->ac.v2i32, &ctx->linear_sample);
1006 add_arg(&args, ARG_VGPR, ctx->ac.v2i32, &ctx->linear_center);
1007 add_arg(&args, ARG_VGPR, ctx->ac.v2i32, &ctx->linear_centroid);
1008 add_arg(&args, ARG_VGPR, ctx->ac.f32, NULL); /* line stipple tex */
1009 add_arg(&args, ARG_VGPR, ctx->ac.f32, &ctx->abi.frag_pos[0]);
1010 add_arg(&args, ARG_VGPR, ctx->ac.f32, &ctx->abi.frag_pos[1]);
1011 add_arg(&args, ARG_VGPR, ctx->ac.f32, &ctx->abi.frag_pos[2]);
1012 add_arg(&args, ARG_VGPR, ctx->ac.f32, &ctx->abi.frag_pos[3]);
1013 add_arg(&args, ARG_VGPR, ctx->ac.i32, &ctx->abi.front_face);
1014 add_arg(&args, ARG_VGPR, ctx->ac.i32, &ctx->abi.ancillary);
1015 add_arg(&args, ARG_VGPR, ctx->ac.i32, &ctx->abi.sample_coverage);
1016 add_arg(&args, ARG_VGPR, ctx->ac.i32, NULL); /* fixed pt */
1017 break;
1018 default:
1019 unreachable("Shader stage not implemented");
1020 }
1021
1022 ctx->main_function = create_llvm_function(
1023 ctx->context, ctx->module, ctx->builder, NULL, 0, &args,
1024 ctx->max_workgroup_size,
1025 ctx->options->unsafe_math);
1026 set_llvm_calling_convention(ctx->main_function, stage);
1027
1028
1029 ctx->shader_info->num_input_vgprs = 0;
1030 ctx->shader_info->num_input_sgprs = ctx->options->supports_spill ? 2 : 0;
1031
1032 ctx->shader_info->num_input_sgprs += args.num_sgprs_used;
1033
1034 if (ctx->stage != MESA_SHADER_FRAGMENT)
1035 ctx->shader_info->num_input_vgprs = args.num_vgprs_used;
1036
1037 assign_arguments(ctx->main_function, &args);
1038
1039 user_sgpr_idx = 0;
1040
1041 if (ctx->options->supports_spill || user_sgpr_info.need_ring_offsets) {
1042 set_loc_shader(ctx, AC_UD_SCRATCH_RING_OFFSETS,
1043 &user_sgpr_idx, 2);
1044 if (ctx->options->supports_spill) {
1045 ctx->ring_offsets = ac_build_intrinsic(&ctx->ac, "llvm.amdgcn.implicit.buffer.ptr",
1046 LLVMPointerType(ctx->ac.i8, CONST_ADDR_SPACE),
1047 NULL, 0, AC_FUNC_ATTR_READNONE);
1048 ctx->ring_offsets = LLVMBuildBitCast(ctx->builder, ctx->ring_offsets,
1049 const_array(ctx->ac.v4i32, 16), "");
1050 }
1051 }
1052
1053 /* For merged shaders the user SGPRs start at 8, with 8 system SGPRs in front (including
1054 * the rw_buffers at s0/s1. With user SGPR0 = s8, lets restart the count from 0 */
1055 if (has_previous_stage)
1056 user_sgpr_idx = 0;
1057
1058 set_global_input_locs(ctx, stage, has_previous_stage, previous_stage,
1059 &user_sgpr_info, desc_sets, &user_sgpr_idx);
1060
1061 switch (stage) {
1062 case MESA_SHADER_COMPUTE:
1063 if (ctx->shader_info->info.cs.uses_grid_size) {
1064 set_loc_shader(ctx, AC_UD_CS_GRID_SIZE,
1065 &user_sgpr_idx, 3);
1066 }
1067 break;
1068 case MESA_SHADER_VERTEX:
1069 set_vs_specific_input_locs(ctx, stage, has_previous_stage,
1070 previous_stage, &user_sgpr_idx);
1071 if (ctx->view_index)
1072 set_loc_shader(ctx, AC_UD_VIEW_INDEX, &user_sgpr_idx, 1);
1073 if (ctx->options->key.vs.as_ls) {
1074 set_loc_shader(ctx, AC_UD_VS_LS_TCS_IN_LAYOUT,
1075 &user_sgpr_idx, 1);
1076 }
1077 if (ctx->options->key.vs.as_ls)
1078 ac_declare_lds_as_pointer(&ctx->ac);
1079 break;
1080 case MESA_SHADER_TESS_CTRL:
1081 set_vs_specific_input_locs(ctx, stage, has_previous_stage,
1082 previous_stage, &user_sgpr_idx);
1083 if (has_previous_stage)
1084 set_loc_shader(ctx, AC_UD_VS_LS_TCS_IN_LAYOUT,
1085 &user_sgpr_idx, 1);
1086 set_loc_shader(ctx, AC_UD_TCS_OFFCHIP_LAYOUT, &user_sgpr_idx, 4);
1087 if (ctx->view_index)
1088 set_loc_shader(ctx, AC_UD_VIEW_INDEX, &user_sgpr_idx, 1);
1089 ac_declare_lds_as_pointer(&ctx->ac);
1090 break;
1091 case MESA_SHADER_TESS_EVAL:
1092 set_loc_shader(ctx, AC_UD_TES_OFFCHIP_LAYOUT, &user_sgpr_idx, 1);
1093 if (ctx->view_index)
1094 set_loc_shader(ctx, AC_UD_VIEW_INDEX, &user_sgpr_idx, 1);
1095 break;
1096 case MESA_SHADER_GEOMETRY:
1097 if (has_previous_stage) {
1098 if (previous_stage == MESA_SHADER_VERTEX)
1099 set_vs_specific_input_locs(ctx, stage,
1100 has_previous_stage,
1101 previous_stage,
1102 &user_sgpr_idx);
1103 else
1104 set_loc_shader(ctx, AC_UD_TES_OFFCHIP_LAYOUT,
1105 &user_sgpr_idx, 1);
1106 }
1107 set_loc_shader(ctx, AC_UD_GS_VS_RING_STRIDE_ENTRIES,
1108 &user_sgpr_idx, 2);
1109 if (ctx->view_index)
1110 set_loc_shader(ctx, AC_UD_VIEW_INDEX, &user_sgpr_idx, 1);
1111 if (has_previous_stage)
1112 ac_declare_lds_as_pointer(&ctx->ac);
1113 break;
1114 case MESA_SHADER_FRAGMENT:
1115 if (ctx->shader_info->info.ps.needs_sample_positions) {
1116 set_loc_shader(ctx, AC_UD_PS_SAMPLE_POS_OFFSET,
1117 &user_sgpr_idx, 1);
1118 }
1119 break;
1120 default:
1121 unreachable("Shader stage not implemented");
1122 }
1123
1124 ctx->shader_info->num_user_sgprs = user_sgpr_idx;
1125 }
1126
1127 static LLVMValueRef trim_vector(struct ac_llvm_context *ctx,
1128 LLVMValueRef value, unsigned count)
1129 {
1130 unsigned num_components = ac_get_llvm_num_components(value);
1131 if (count == num_components)
1132 return value;
1133
1134 LLVMValueRef masks[] = {
1135 LLVMConstInt(ctx->i32, 0, false), LLVMConstInt(ctx->i32, 1, false),
1136 LLVMConstInt(ctx->i32, 2, false), LLVMConstInt(ctx->i32, 3, false)};
1137
1138 if (count == 1)
1139 return LLVMBuildExtractElement(ctx->builder, value, masks[0],
1140 "");
1141
1142 LLVMValueRef swizzle = LLVMConstVector(masks, count);
1143 return LLVMBuildShuffleVector(ctx->builder, value, value, swizzle, "");
1144 }
1145
1146 static void
1147 build_store_values_extended(struct ac_llvm_context *ac,
1148 LLVMValueRef *values,
1149 unsigned value_count,
1150 unsigned value_stride,
1151 LLVMValueRef vec)
1152 {
1153 LLVMBuilderRef builder = ac->builder;
1154 unsigned i;
1155
1156 for (i = 0; i < value_count; i++) {
1157 LLVMValueRef ptr = values[i * value_stride];
1158 LLVMValueRef index = LLVMConstInt(ac->i32, i, false);
1159 LLVMValueRef value = LLVMBuildExtractElement(builder, vec, index, "");
1160 LLVMBuildStore(builder, value, ptr);
1161 }
1162 }
1163
1164 static LLVMTypeRef get_def_type(struct ac_nir_context *ctx,
1165 const nir_ssa_def *def)
1166 {
1167 LLVMTypeRef type = LLVMIntTypeInContext(ctx->ac.context, def->bit_size);
1168 if (def->num_components > 1) {
1169 type = LLVMVectorType(type, def->num_components);
1170 }
1171 return type;
1172 }
1173
1174 static LLVMValueRef get_src(struct ac_nir_context *nir, nir_src src)
1175 {
1176 assert(src.is_ssa);
1177 struct hash_entry *entry = _mesa_hash_table_search(nir->defs, src.ssa);
1178 return (LLVMValueRef)entry->data;
1179 }
1180
1181
1182 static LLVMBasicBlockRef get_block(struct ac_nir_context *nir,
1183 const struct nir_block *b)
1184 {
1185 struct hash_entry *entry = _mesa_hash_table_search(nir->defs, b);
1186 return (LLVMBasicBlockRef)entry->data;
1187 }
1188
1189 static LLVMValueRef get_alu_src(struct ac_nir_context *ctx,
1190 nir_alu_src src,
1191 unsigned num_components)
1192 {
1193 LLVMValueRef value = get_src(ctx, src.src);
1194 bool need_swizzle = false;
1195
1196 assert(value);
1197 LLVMTypeRef type = LLVMTypeOf(value);
1198 unsigned src_components = LLVMGetTypeKind(type) == LLVMVectorTypeKind
1199 ? LLVMGetVectorSize(type)
1200 : 1;
1201
1202 for (unsigned i = 0; i < num_components; ++i) {
1203 assert(src.swizzle[i] < src_components);
1204 if (src.swizzle[i] != i)
1205 need_swizzle = true;
1206 }
1207
1208 if (need_swizzle || num_components != src_components) {
1209 LLVMValueRef masks[] = {
1210 LLVMConstInt(ctx->ac.i32, src.swizzle[0], false),
1211 LLVMConstInt(ctx->ac.i32, src.swizzle[1], false),
1212 LLVMConstInt(ctx->ac.i32, src.swizzle[2], false),
1213 LLVMConstInt(ctx->ac.i32, src.swizzle[3], false)};
1214
1215 if (src_components > 1 && num_components == 1) {
1216 value = LLVMBuildExtractElement(ctx->ac.builder, value,
1217 masks[0], "");
1218 } else if (src_components == 1 && num_components > 1) {
1219 LLVMValueRef values[] = {value, value, value, value};
1220 value = ac_build_gather_values(&ctx->ac, values, num_components);
1221 } else {
1222 LLVMValueRef swizzle = LLVMConstVector(masks, num_components);
1223 value = LLVMBuildShuffleVector(ctx->ac.builder, value, value,
1224 swizzle, "");
1225 }
1226 }
1227 assert(!src.negate);
1228 assert(!src.abs);
1229 return value;
1230 }
1231
1232 static LLVMValueRef emit_int_cmp(struct ac_llvm_context *ctx,
1233 LLVMIntPredicate pred, LLVMValueRef src0,
1234 LLVMValueRef src1)
1235 {
1236 LLVMValueRef result = LLVMBuildICmp(ctx->builder, pred, src0, src1, "");
1237 return LLVMBuildSelect(ctx->builder, result,
1238 LLVMConstInt(ctx->i32, 0xFFFFFFFF, false),
1239 ctx->i32_0, "");
1240 }
1241
1242 static LLVMValueRef emit_float_cmp(struct ac_llvm_context *ctx,
1243 LLVMRealPredicate pred, LLVMValueRef src0,
1244 LLVMValueRef src1)
1245 {
1246 LLVMValueRef result;
1247 src0 = ac_to_float(ctx, src0);
1248 src1 = ac_to_float(ctx, src1);
1249 result = LLVMBuildFCmp(ctx->builder, pred, src0, src1, "");
1250 return LLVMBuildSelect(ctx->builder, result,
1251 LLVMConstInt(ctx->i32, 0xFFFFFFFF, false),
1252 ctx->i32_0, "");
1253 }
1254
1255 static LLVMValueRef emit_intrin_1f_param(struct ac_llvm_context *ctx,
1256 const char *intrin,
1257 LLVMTypeRef result_type,
1258 LLVMValueRef src0)
1259 {
1260 char name[64];
1261 LLVMValueRef params[] = {
1262 ac_to_float(ctx, src0),
1263 };
1264
1265 MAYBE_UNUSED const int length = snprintf(name, sizeof(name), "%s.f%d", intrin,
1266 get_elem_bits(ctx, result_type));
1267 assert(length < sizeof(name));
1268 return ac_build_intrinsic(ctx, name, result_type, params, 1, AC_FUNC_ATTR_READNONE);
1269 }
1270
1271 static LLVMValueRef emit_intrin_2f_param(struct ac_llvm_context *ctx,
1272 const char *intrin,
1273 LLVMTypeRef result_type,
1274 LLVMValueRef src0, LLVMValueRef src1)
1275 {
1276 char name[64];
1277 LLVMValueRef params[] = {
1278 ac_to_float(ctx, src0),
1279 ac_to_float(ctx, src1),
1280 };
1281
1282 MAYBE_UNUSED const int length = snprintf(name, sizeof(name), "%s.f%d", intrin,
1283 get_elem_bits(ctx, result_type));
1284 assert(length < sizeof(name));
1285 return ac_build_intrinsic(ctx, name, result_type, params, 2, AC_FUNC_ATTR_READNONE);
1286 }
1287
1288 static LLVMValueRef emit_intrin_3f_param(struct ac_llvm_context *ctx,
1289 const char *intrin,
1290 LLVMTypeRef result_type,
1291 LLVMValueRef src0, LLVMValueRef src1, LLVMValueRef src2)
1292 {
1293 char name[64];
1294 LLVMValueRef params[] = {
1295 ac_to_float(ctx, src0),
1296 ac_to_float(ctx, src1),
1297 ac_to_float(ctx, src2),
1298 };
1299
1300 MAYBE_UNUSED const int length = snprintf(name, sizeof(name), "%s.f%d", intrin,
1301 get_elem_bits(ctx, result_type));
1302 assert(length < sizeof(name));
1303 return ac_build_intrinsic(ctx, name, result_type, params, 3, AC_FUNC_ATTR_READNONE);
1304 }
1305
1306 static LLVMValueRef emit_bcsel(struct ac_llvm_context *ctx,
1307 LLVMValueRef src0, LLVMValueRef src1, LLVMValueRef src2)
1308 {
1309 LLVMValueRef v = LLVMBuildICmp(ctx->builder, LLVMIntNE, src0,
1310 ctx->i32_0, "");
1311 return LLVMBuildSelect(ctx->builder, v, src1, src2, "");
1312 }
1313
1314 static LLVMValueRef emit_minmax_int(struct ac_llvm_context *ctx,
1315 LLVMIntPredicate pred,
1316 LLVMValueRef src0, LLVMValueRef src1)
1317 {
1318 return LLVMBuildSelect(ctx->builder,
1319 LLVMBuildICmp(ctx->builder, pred, src0, src1, ""),
1320 src0,
1321 src1, "");
1322
1323 }
1324 static LLVMValueRef emit_iabs(struct ac_llvm_context *ctx,
1325 LLVMValueRef src0)
1326 {
1327 return emit_minmax_int(ctx, LLVMIntSGT, src0,
1328 LLVMBuildNeg(ctx->builder, src0, ""));
1329 }
1330
1331 static LLVMValueRef emit_fsign(struct ac_llvm_context *ctx,
1332 LLVMValueRef src0)
1333 {
1334 LLVMValueRef cmp, val;
1335
1336 cmp = LLVMBuildFCmp(ctx->builder, LLVMRealOGT, src0, ctx->f32_0, "");
1337 val = LLVMBuildSelect(ctx->builder, cmp, ctx->f32_1, src0, "");
1338 cmp = LLVMBuildFCmp(ctx->builder, LLVMRealOGE, val, ctx->f32_0, "");
1339 val = LLVMBuildSelect(ctx->builder, cmp, val, LLVMConstReal(ctx->f32, -1.0), "");
1340 return val;
1341 }
1342
1343 static LLVMValueRef emit_isign(struct ac_llvm_context *ctx,
1344 LLVMValueRef src0)
1345 {
1346 LLVMValueRef cmp, val;
1347
1348 cmp = LLVMBuildICmp(ctx->builder, LLVMIntSGT, src0, ctx->i32_0, "");
1349 val = LLVMBuildSelect(ctx->builder, cmp, ctx->i32_1, src0, "");
1350 cmp = LLVMBuildICmp(ctx->builder, LLVMIntSGE, val, ctx->i32_0, "");
1351 val = LLVMBuildSelect(ctx->builder, cmp, val, LLVMConstInt(ctx->i32, -1, true), "");
1352 return val;
1353 }
1354
1355 static LLVMValueRef emit_ffract(struct ac_llvm_context *ctx,
1356 LLVMValueRef src0)
1357 {
1358 const char *intr = "llvm.floor.f32";
1359 LLVMValueRef fsrc0 = ac_to_float(ctx, src0);
1360 LLVMValueRef params[] = {
1361 fsrc0,
1362 };
1363 LLVMValueRef floor = ac_build_intrinsic(ctx, intr,
1364 ctx->f32, params, 1,
1365 AC_FUNC_ATTR_READNONE);
1366 return LLVMBuildFSub(ctx->builder, fsrc0, floor, "");
1367 }
1368
1369 static LLVMValueRef emit_uint_carry(struct ac_llvm_context *ctx,
1370 const char *intrin,
1371 LLVMValueRef src0, LLVMValueRef src1)
1372 {
1373 LLVMTypeRef ret_type;
1374 LLVMTypeRef types[] = { ctx->i32, ctx->i1 };
1375 LLVMValueRef res;
1376 LLVMValueRef params[] = { src0, src1 };
1377 ret_type = LLVMStructTypeInContext(ctx->context, types,
1378 2, true);
1379
1380 res = ac_build_intrinsic(ctx, intrin, ret_type,
1381 params, 2, AC_FUNC_ATTR_READNONE);
1382
1383 res = LLVMBuildExtractValue(ctx->builder, res, 1, "");
1384 res = LLVMBuildZExt(ctx->builder, res, ctx->i32, "");
1385 return res;
1386 }
1387
1388 static LLVMValueRef emit_b2f(struct ac_llvm_context *ctx,
1389 LLVMValueRef src0)
1390 {
1391 return LLVMBuildAnd(ctx->builder, src0, LLVMBuildBitCast(ctx->builder, LLVMConstReal(ctx->f32, 1.0), ctx->i32, ""), "");
1392 }
1393
1394 static LLVMValueRef emit_f2b(struct ac_llvm_context *ctx,
1395 LLVMValueRef src0)
1396 {
1397 src0 = ac_to_float(ctx, src0);
1398 return LLVMBuildSExt(ctx->builder,
1399 LLVMBuildFCmp(ctx->builder, LLVMRealUNE, src0, ctx->f32_0, ""),
1400 ctx->i32, "");
1401 }
1402
1403 static LLVMValueRef emit_b2i(struct ac_llvm_context *ctx,
1404 LLVMValueRef src0)
1405 {
1406 return LLVMBuildAnd(ctx->builder, src0, ctx->i32_1, "");
1407 }
1408
1409 static LLVMValueRef emit_i2b(struct ac_llvm_context *ctx,
1410 LLVMValueRef src0)
1411 {
1412 return LLVMBuildSExt(ctx->builder,
1413 LLVMBuildICmp(ctx->builder, LLVMIntNE, src0, ctx->i32_0, ""),
1414 ctx->i32, "");
1415 }
1416
1417 static LLVMValueRef emit_f2f16(struct nir_to_llvm_context *ctx,
1418 LLVMValueRef src0)
1419 {
1420 LLVMValueRef result;
1421 LLVMValueRef cond = NULL;
1422
1423 src0 = ac_to_float(&ctx->ac, src0);
1424 result = LLVMBuildFPTrunc(ctx->builder, src0, ctx->ac.f16, "");
1425
1426 if (ctx->options->chip_class >= VI) {
1427 LLVMValueRef args[2];
1428 /* Check if the result is a denormal - and flush to 0 if so. */
1429 args[0] = result;
1430 args[1] = LLVMConstInt(ctx->ac.i32, N_SUBNORMAL | P_SUBNORMAL, false);
1431 cond = ac_build_intrinsic(&ctx->ac, "llvm.amdgcn.class.f16", ctx->ac.i1, args, 2, AC_FUNC_ATTR_READNONE);
1432 }
1433
1434 /* need to convert back up to f32 */
1435 result = LLVMBuildFPExt(ctx->builder, result, ctx->ac.f32, "");
1436
1437 if (ctx->options->chip_class >= VI)
1438 result = LLVMBuildSelect(ctx->builder, cond, ctx->ac.f32_0, result, "");
1439 else {
1440 /* for SI/CIK */
1441 /* 0x38800000 is smallest half float value (2^-14) in 32-bit float,
1442 * so compare the result and flush to 0 if it's smaller.
1443 */
1444 LLVMValueRef temp, cond2;
1445 temp = emit_intrin_1f_param(&ctx->ac, "llvm.fabs",
1446 ctx->ac.f32, result);
1447 cond = LLVMBuildFCmp(ctx->builder, LLVMRealUGT,
1448 LLVMBuildBitCast(ctx->builder, LLVMConstInt(ctx->ac.i32, 0x38800000, false), ctx->ac.f32, ""),
1449 temp, "");
1450 cond2 = LLVMBuildFCmp(ctx->builder, LLVMRealUNE,
1451 temp, ctx->ac.f32_0, "");
1452 cond = LLVMBuildAnd(ctx->builder, cond, cond2, "");
1453 result = LLVMBuildSelect(ctx->builder, cond, ctx->ac.f32_0, result, "");
1454 }
1455 return result;
1456 }
1457
1458 static LLVMValueRef emit_umul_high(struct ac_llvm_context *ctx,
1459 LLVMValueRef src0, LLVMValueRef src1)
1460 {
1461 LLVMValueRef dst64, result;
1462 src0 = LLVMBuildZExt(ctx->builder, src0, ctx->i64, "");
1463 src1 = LLVMBuildZExt(ctx->builder, src1, ctx->i64, "");
1464
1465 dst64 = LLVMBuildMul(ctx->builder, src0, src1, "");
1466 dst64 = LLVMBuildLShr(ctx->builder, dst64, LLVMConstInt(ctx->i64, 32, false), "");
1467 result = LLVMBuildTrunc(ctx->builder, dst64, ctx->i32, "");
1468 return result;
1469 }
1470
1471 static LLVMValueRef emit_imul_high(struct ac_llvm_context *ctx,
1472 LLVMValueRef src0, LLVMValueRef src1)
1473 {
1474 LLVMValueRef dst64, result;
1475 src0 = LLVMBuildSExt(ctx->builder, src0, ctx->i64, "");
1476 src1 = LLVMBuildSExt(ctx->builder, src1, ctx->i64, "");
1477
1478 dst64 = LLVMBuildMul(ctx->builder, src0, src1, "");
1479 dst64 = LLVMBuildAShr(ctx->builder, dst64, LLVMConstInt(ctx->i64, 32, false), "");
1480 result = LLVMBuildTrunc(ctx->builder, dst64, ctx->i32, "");
1481 return result;
1482 }
1483
1484 static LLVMValueRef emit_bitfield_extract(struct ac_llvm_context *ctx,
1485 bool is_signed,
1486 const LLVMValueRef srcs[3])
1487 {
1488 LLVMValueRef result;
1489 LLVMValueRef icond = LLVMBuildICmp(ctx->builder, LLVMIntEQ, srcs[2], LLVMConstInt(ctx->i32, 32, false), "");
1490
1491 result = ac_build_bfe(ctx, srcs[0], srcs[1], srcs[2], is_signed);
1492 result = LLVMBuildSelect(ctx->builder, icond, srcs[0], result, "");
1493 return result;
1494 }
1495
1496 static LLVMValueRef emit_bitfield_insert(struct ac_llvm_context *ctx,
1497 LLVMValueRef src0, LLVMValueRef src1,
1498 LLVMValueRef src2, LLVMValueRef src3)
1499 {
1500 LLVMValueRef bfi_args[3], result;
1501
1502 bfi_args[0] = LLVMBuildShl(ctx->builder,
1503 LLVMBuildSub(ctx->builder,
1504 LLVMBuildShl(ctx->builder,
1505 ctx->i32_1,
1506 src3, ""),
1507 ctx->i32_1, ""),
1508 src2, "");
1509 bfi_args[1] = LLVMBuildShl(ctx->builder, src1, src2, "");
1510 bfi_args[2] = src0;
1511
1512 LLVMValueRef icond = LLVMBuildICmp(ctx->builder, LLVMIntEQ, src3, LLVMConstInt(ctx->i32, 32, false), "");
1513
1514 /* Calculate:
1515 * (arg0 & arg1) | (~arg0 & arg2) = arg2 ^ (arg0 & (arg1 ^ arg2)
1516 * Use the right-hand side, which the LLVM backend can convert to V_BFI.
1517 */
1518 result = LLVMBuildXor(ctx->builder, bfi_args[2],
1519 LLVMBuildAnd(ctx->builder, bfi_args[0],
1520 LLVMBuildXor(ctx->builder, bfi_args[1], bfi_args[2], ""), ""), "");
1521
1522 result = LLVMBuildSelect(ctx->builder, icond, src1, result, "");
1523 return result;
1524 }
1525
1526 static LLVMValueRef emit_pack_half_2x16(struct ac_llvm_context *ctx,
1527 LLVMValueRef src0)
1528 {
1529 LLVMValueRef comp[2];
1530
1531 src0 = ac_to_float(ctx, src0);
1532 comp[0] = LLVMBuildExtractElement(ctx->builder, src0, ctx->i32_0, "");
1533 comp[1] = LLVMBuildExtractElement(ctx->builder, src0, ctx->i32_1, "");
1534
1535 return ac_build_cvt_pkrtz_f16(ctx, comp);
1536 }
1537
1538 static LLVMValueRef emit_unpack_half_2x16(struct ac_llvm_context *ctx,
1539 LLVMValueRef src0)
1540 {
1541 LLVMValueRef const16 = LLVMConstInt(ctx->i32, 16, false);
1542 LLVMValueRef temps[2], result, val;
1543 int i;
1544
1545 for (i = 0; i < 2; i++) {
1546 val = i == 1 ? LLVMBuildLShr(ctx->builder, src0, const16, "") : src0;
1547 val = LLVMBuildTrunc(ctx->builder, val, ctx->i16, "");
1548 val = LLVMBuildBitCast(ctx->builder, val, ctx->f16, "");
1549 temps[i] = LLVMBuildFPExt(ctx->builder, val, ctx->f32, "");
1550 }
1551
1552 result = LLVMBuildInsertElement(ctx->builder, LLVMGetUndef(ctx->v2f32), temps[0],
1553 ctx->i32_0, "");
1554 result = LLVMBuildInsertElement(ctx->builder, result, temps[1],
1555 ctx->i32_1, "");
1556 return result;
1557 }
1558
1559 static LLVMValueRef emit_ddxy(struct ac_nir_context *ctx,
1560 nir_op op,
1561 LLVMValueRef src0)
1562 {
1563 unsigned mask;
1564 int idx;
1565 LLVMValueRef result;
1566
1567 if (op == nir_op_fddx_fine || op == nir_op_fddx)
1568 mask = AC_TID_MASK_LEFT;
1569 else if (op == nir_op_fddy_fine || op == nir_op_fddy)
1570 mask = AC_TID_MASK_TOP;
1571 else
1572 mask = AC_TID_MASK_TOP_LEFT;
1573
1574 /* for DDX we want to next X pixel, DDY next Y pixel. */
1575 if (op == nir_op_fddx_fine ||
1576 op == nir_op_fddx_coarse ||
1577 op == nir_op_fddx)
1578 idx = 1;
1579 else
1580 idx = 2;
1581
1582 result = ac_build_ddxy(&ctx->ac, mask, idx, src0);
1583 return result;
1584 }
1585
1586 /*
1587 * this takes an I,J coordinate pair,
1588 * and works out the X and Y derivatives.
1589 * it returns DDX(I), DDX(J), DDY(I), DDY(J).
1590 */
1591 static LLVMValueRef emit_ddxy_interp(
1592 struct ac_nir_context *ctx,
1593 LLVMValueRef interp_ij)
1594 {
1595 LLVMValueRef result[4], a;
1596 unsigned i;
1597
1598 for (i = 0; i < 2; i++) {
1599 a = LLVMBuildExtractElement(ctx->ac.builder, interp_ij,
1600 LLVMConstInt(ctx->ac.i32, i, false), "");
1601 result[i] = emit_ddxy(ctx, nir_op_fddx, a);
1602 result[2+i] = emit_ddxy(ctx, nir_op_fddy, a);
1603 }
1604 return ac_build_gather_values(&ctx->ac, result, 4);
1605 }
1606
1607 static void visit_alu(struct ac_nir_context *ctx, const nir_alu_instr *instr)
1608 {
1609 LLVMValueRef src[4], result = NULL;
1610 unsigned num_components = instr->dest.dest.ssa.num_components;
1611 unsigned src_components;
1612 LLVMTypeRef def_type = get_def_type(ctx, &instr->dest.dest.ssa);
1613
1614 assert(nir_op_infos[instr->op].num_inputs <= ARRAY_SIZE(src));
1615 switch (instr->op) {
1616 case nir_op_vec2:
1617 case nir_op_vec3:
1618 case nir_op_vec4:
1619 src_components = 1;
1620 break;
1621 case nir_op_pack_half_2x16:
1622 src_components = 2;
1623 break;
1624 case nir_op_unpack_half_2x16:
1625 src_components = 1;
1626 break;
1627 default:
1628 src_components = num_components;
1629 break;
1630 }
1631 for (unsigned i = 0; i < nir_op_infos[instr->op].num_inputs; i++)
1632 src[i] = get_alu_src(ctx, instr->src[i], src_components);
1633
1634 switch (instr->op) {
1635 case nir_op_fmov:
1636 case nir_op_imov:
1637 result = src[0];
1638 break;
1639 case nir_op_fneg:
1640 src[0] = ac_to_float(&ctx->ac, src[0]);
1641 result = LLVMBuildFNeg(ctx->ac.builder, src[0], "");
1642 break;
1643 case nir_op_ineg:
1644 result = LLVMBuildNeg(ctx->ac.builder, src[0], "");
1645 break;
1646 case nir_op_inot:
1647 result = LLVMBuildNot(ctx->ac.builder, src[0], "");
1648 break;
1649 case nir_op_iadd:
1650 result = LLVMBuildAdd(ctx->ac.builder, src[0], src[1], "");
1651 break;
1652 case nir_op_fadd:
1653 src[0] = ac_to_float(&ctx->ac, src[0]);
1654 src[1] = ac_to_float(&ctx->ac, src[1]);
1655 result = LLVMBuildFAdd(ctx->ac.builder, src[0], src[1], "");
1656 break;
1657 case nir_op_fsub:
1658 src[0] = ac_to_float(&ctx->ac, src[0]);
1659 src[1] = ac_to_float(&ctx->ac, src[1]);
1660 result = LLVMBuildFSub(ctx->ac.builder, src[0], src[1], "");
1661 break;
1662 case nir_op_isub:
1663 result = LLVMBuildSub(ctx->ac.builder, src[0], src[1], "");
1664 break;
1665 case nir_op_imul:
1666 result = LLVMBuildMul(ctx->ac.builder, src[0], src[1], "");
1667 break;
1668 case nir_op_imod:
1669 result = LLVMBuildSRem(ctx->ac.builder, src[0], src[1], "");
1670 break;
1671 case nir_op_umod:
1672 result = LLVMBuildURem(ctx->ac.builder, src[0], src[1], "");
1673 break;
1674 case nir_op_fmod:
1675 src[0] = ac_to_float(&ctx->ac, src[0]);
1676 src[1] = ac_to_float(&ctx->ac, src[1]);
1677 result = ac_build_fdiv(&ctx->ac, src[0], src[1]);
1678 result = emit_intrin_1f_param(&ctx->ac, "llvm.floor",
1679 ac_to_float_type(&ctx->ac, def_type), result);
1680 result = LLVMBuildFMul(ctx->ac.builder, src[1] , result, "");
1681 result = LLVMBuildFSub(ctx->ac.builder, src[0], result, "");
1682 break;
1683 case nir_op_frem:
1684 src[0] = ac_to_float(&ctx->ac, src[0]);
1685 src[1] = ac_to_float(&ctx->ac, src[1]);
1686 result = LLVMBuildFRem(ctx->ac.builder, src[0], src[1], "");
1687 break;
1688 case nir_op_irem:
1689 result = LLVMBuildSRem(ctx->ac.builder, src[0], src[1], "");
1690 break;
1691 case nir_op_idiv:
1692 result = LLVMBuildSDiv(ctx->ac.builder, src[0], src[1], "");
1693 break;
1694 case nir_op_udiv:
1695 result = LLVMBuildUDiv(ctx->ac.builder, src[0], src[1], "");
1696 break;
1697 case nir_op_fmul:
1698 src[0] = ac_to_float(&ctx->ac, src[0]);
1699 src[1] = ac_to_float(&ctx->ac, src[1]);
1700 result = LLVMBuildFMul(ctx->ac.builder, src[0], src[1], "");
1701 break;
1702 case nir_op_fdiv:
1703 src[0] = ac_to_float(&ctx->ac, src[0]);
1704 src[1] = ac_to_float(&ctx->ac, src[1]);
1705 result = ac_build_fdiv(&ctx->ac, src[0], src[1]);
1706 break;
1707 case nir_op_frcp:
1708 src[0] = ac_to_float(&ctx->ac, src[0]);
1709 result = ac_build_fdiv(&ctx->ac, ctx->ac.f32_1, src[0]);
1710 break;
1711 case nir_op_iand:
1712 result = LLVMBuildAnd(ctx->ac.builder, src[0], src[1], "");
1713 break;
1714 case nir_op_ior:
1715 result = LLVMBuildOr(ctx->ac.builder, src[0], src[1], "");
1716 break;
1717 case nir_op_ixor:
1718 result = LLVMBuildXor(ctx->ac.builder, src[0], src[1], "");
1719 break;
1720 case nir_op_ishl:
1721 result = LLVMBuildShl(ctx->ac.builder, src[0],
1722 LLVMBuildZExt(ctx->ac.builder, src[1],
1723 LLVMTypeOf(src[0]), ""),
1724 "");
1725 break;
1726 case nir_op_ishr:
1727 result = LLVMBuildAShr(ctx->ac.builder, src[0],
1728 LLVMBuildZExt(ctx->ac.builder, src[1],
1729 LLVMTypeOf(src[0]), ""),
1730 "");
1731 break;
1732 case nir_op_ushr:
1733 result = LLVMBuildLShr(ctx->ac.builder, src[0],
1734 LLVMBuildZExt(ctx->ac.builder, src[1],
1735 LLVMTypeOf(src[0]), ""),
1736 "");
1737 break;
1738 case nir_op_ilt:
1739 result = emit_int_cmp(&ctx->ac, LLVMIntSLT, src[0], src[1]);
1740 break;
1741 case nir_op_ine:
1742 result = emit_int_cmp(&ctx->ac, LLVMIntNE, src[0], src[1]);
1743 break;
1744 case nir_op_ieq:
1745 result = emit_int_cmp(&ctx->ac, LLVMIntEQ, src[0], src[1]);
1746 break;
1747 case nir_op_ige:
1748 result = emit_int_cmp(&ctx->ac, LLVMIntSGE, src[0], src[1]);
1749 break;
1750 case nir_op_ult:
1751 result = emit_int_cmp(&ctx->ac, LLVMIntULT, src[0], src[1]);
1752 break;
1753 case nir_op_uge:
1754 result = emit_int_cmp(&ctx->ac, LLVMIntUGE, src[0], src[1]);
1755 break;
1756 case nir_op_feq:
1757 result = emit_float_cmp(&ctx->ac, LLVMRealUEQ, src[0], src[1]);
1758 break;
1759 case nir_op_fne:
1760 result = emit_float_cmp(&ctx->ac, LLVMRealUNE, src[0], src[1]);
1761 break;
1762 case nir_op_flt:
1763 result = emit_float_cmp(&ctx->ac, LLVMRealULT, src[0], src[1]);
1764 break;
1765 case nir_op_fge:
1766 result = emit_float_cmp(&ctx->ac, LLVMRealUGE, src[0], src[1]);
1767 break;
1768 case nir_op_fabs:
1769 result = emit_intrin_1f_param(&ctx->ac, "llvm.fabs",
1770 ac_to_float_type(&ctx->ac, def_type), src[0]);
1771 break;
1772 case nir_op_iabs:
1773 result = emit_iabs(&ctx->ac, src[0]);
1774 break;
1775 case nir_op_imax:
1776 result = emit_minmax_int(&ctx->ac, LLVMIntSGT, src[0], src[1]);
1777 break;
1778 case nir_op_imin:
1779 result = emit_minmax_int(&ctx->ac, LLVMIntSLT, src[0], src[1]);
1780 break;
1781 case nir_op_umax:
1782 result = emit_minmax_int(&ctx->ac, LLVMIntUGT, src[0], src[1]);
1783 break;
1784 case nir_op_umin:
1785 result = emit_minmax_int(&ctx->ac, LLVMIntULT, src[0], src[1]);
1786 break;
1787 case nir_op_isign:
1788 result = emit_isign(&ctx->ac, src[0]);
1789 break;
1790 case nir_op_fsign:
1791 src[0] = ac_to_float(&ctx->ac, src[0]);
1792 result = emit_fsign(&ctx->ac, src[0]);
1793 break;
1794 case nir_op_ffloor:
1795 result = emit_intrin_1f_param(&ctx->ac, "llvm.floor",
1796 ac_to_float_type(&ctx->ac, def_type), src[0]);
1797 break;
1798 case nir_op_ftrunc:
1799 result = emit_intrin_1f_param(&ctx->ac, "llvm.trunc",
1800 ac_to_float_type(&ctx->ac, def_type), src[0]);
1801 break;
1802 case nir_op_fceil:
1803 result = emit_intrin_1f_param(&ctx->ac, "llvm.ceil",
1804 ac_to_float_type(&ctx->ac, def_type), src[0]);
1805 break;
1806 case nir_op_fround_even:
1807 result = emit_intrin_1f_param(&ctx->ac, "llvm.rint",
1808 ac_to_float_type(&ctx->ac, def_type),src[0]);
1809 break;
1810 case nir_op_ffract:
1811 result = emit_ffract(&ctx->ac, src[0]);
1812 break;
1813 case nir_op_fsin:
1814 result = emit_intrin_1f_param(&ctx->ac, "llvm.sin",
1815 ac_to_float_type(&ctx->ac, def_type), src[0]);
1816 break;
1817 case nir_op_fcos:
1818 result = emit_intrin_1f_param(&ctx->ac, "llvm.cos",
1819 ac_to_float_type(&ctx->ac, def_type), src[0]);
1820 break;
1821 case nir_op_fsqrt:
1822 result = emit_intrin_1f_param(&ctx->ac, "llvm.sqrt",
1823 ac_to_float_type(&ctx->ac, def_type), src[0]);
1824 break;
1825 case nir_op_fexp2:
1826 result = emit_intrin_1f_param(&ctx->ac, "llvm.exp2",
1827 ac_to_float_type(&ctx->ac, def_type), src[0]);
1828 break;
1829 case nir_op_flog2:
1830 result = emit_intrin_1f_param(&ctx->ac, "llvm.log2",
1831 ac_to_float_type(&ctx->ac, def_type), src[0]);
1832 break;
1833 case nir_op_frsq:
1834 result = emit_intrin_1f_param(&ctx->ac, "llvm.sqrt",
1835 ac_to_float_type(&ctx->ac, def_type), src[0]);
1836 result = ac_build_fdiv(&ctx->ac, ctx->ac.f32_1, result);
1837 break;
1838 case nir_op_fpow:
1839 result = emit_intrin_2f_param(&ctx->ac, "llvm.pow",
1840 ac_to_float_type(&ctx->ac, def_type), src[0], src[1]);
1841 break;
1842 case nir_op_fmax:
1843 result = emit_intrin_2f_param(&ctx->ac, "llvm.maxnum",
1844 ac_to_float_type(&ctx->ac, def_type), src[0], src[1]);
1845 if (instr->dest.dest.ssa.bit_size == 32)
1846 result = emit_intrin_1f_param(&ctx->ac, "llvm.canonicalize",
1847 ac_to_float_type(&ctx->ac, def_type),
1848 result);
1849 break;
1850 case nir_op_fmin:
1851 result = emit_intrin_2f_param(&ctx->ac, "llvm.minnum",
1852 ac_to_float_type(&ctx->ac, def_type), src[0], src[1]);
1853 if (instr->dest.dest.ssa.bit_size == 32)
1854 result = emit_intrin_1f_param(&ctx->ac, "llvm.canonicalize",
1855 ac_to_float_type(&ctx->ac, def_type),
1856 result);
1857 break;
1858 case nir_op_ffma:
1859 result = emit_intrin_3f_param(&ctx->ac, "llvm.fmuladd",
1860 ac_to_float_type(&ctx->ac, def_type), src[0], src[1], src[2]);
1861 break;
1862 case nir_op_ibitfield_extract:
1863 result = emit_bitfield_extract(&ctx->ac, true, src);
1864 break;
1865 case nir_op_ubitfield_extract:
1866 result = emit_bitfield_extract(&ctx->ac, false, src);
1867 break;
1868 case nir_op_bitfield_insert:
1869 result = emit_bitfield_insert(&ctx->ac, src[0], src[1], src[2], src[3]);
1870 break;
1871 case nir_op_bitfield_reverse:
1872 result = ac_build_intrinsic(&ctx->ac, "llvm.bitreverse.i32", ctx->ac.i32, src, 1, AC_FUNC_ATTR_READNONE);
1873 break;
1874 case nir_op_bit_count:
1875 result = ac_build_intrinsic(&ctx->ac, "llvm.ctpop.i32", ctx->ac.i32, src, 1, AC_FUNC_ATTR_READNONE);
1876 break;
1877 case nir_op_vec2:
1878 case nir_op_vec3:
1879 case nir_op_vec4:
1880 for (unsigned i = 0; i < nir_op_infos[instr->op].num_inputs; i++)
1881 src[i] = ac_to_integer(&ctx->ac, src[i]);
1882 result = ac_build_gather_values(&ctx->ac, src, num_components);
1883 break;
1884 case nir_op_f2i32:
1885 case nir_op_f2i64:
1886 src[0] = ac_to_float(&ctx->ac, src[0]);
1887 result = LLVMBuildFPToSI(ctx->ac.builder, src[0], def_type, "");
1888 break;
1889 case nir_op_f2u32:
1890 case nir_op_f2u64:
1891 src[0] = ac_to_float(&ctx->ac, src[0]);
1892 result = LLVMBuildFPToUI(ctx->ac.builder, src[0], def_type, "");
1893 break;
1894 case nir_op_i2f32:
1895 case nir_op_i2f64:
1896 src[0] = ac_to_integer(&ctx->ac, src[0]);
1897 result = LLVMBuildSIToFP(ctx->ac.builder, src[0], ac_to_float_type(&ctx->ac, def_type), "");
1898 break;
1899 case nir_op_u2f32:
1900 case nir_op_u2f64:
1901 src[0] = ac_to_integer(&ctx->ac, src[0]);
1902 result = LLVMBuildUIToFP(ctx->ac.builder, src[0], ac_to_float_type(&ctx->ac, def_type), "");
1903 break;
1904 case nir_op_f2f64:
1905 src[0] = ac_to_float(&ctx->ac, src[0]);
1906 result = LLVMBuildFPExt(ctx->ac.builder, src[0], ac_to_float_type(&ctx->ac, def_type), "");
1907 break;
1908 case nir_op_f2f32:
1909 result = LLVMBuildFPTrunc(ctx->ac.builder, src[0], ac_to_float_type(&ctx->ac, def_type), "");
1910 break;
1911 case nir_op_u2u32:
1912 case nir_op_u2u64:
1913 src[0] = ac_to_integer(&ctx->ac, src[0]);
1914 if (get_elem_bits(&ctx->ac, LLVMTypeOf(src[0])) < get_elem_bits(&ctx->ac, def_type))
1915 result = LLVMBuildZExt(ctx->ac.builder, src[0], def_type, "");
1916 else
1917 result = LLVMBuildTrunc(ctx->ac.builder, src[0], def_type, "");
1918 break;
1919 case nir_op_i2i32:
1920 case nir_op_i2i64:
1921 src[0] = ac_to_integer(&ctx->ac, src[0]);
1922 if (get_elem_bits(&ctx->ac, LLVMTypeOf(src[0])) < get_elem_bits(&ctx->ac, def_type))
1923 result = LLVMBuildSExt(ctx->ac.builder, src[0], def_type, "");
1924 else
1925 result = LLVMBuildTrunc(ctx->ac.builder, src[0], def_type, "");
1926 break;
1927 case nir_op_bcsel:
1928 result = emit_bcsel(&ctx->ac, src[0], src[1], src[2]);
1929 break;
1930 case nir_op_find_lsb:
1931 src[0] = ac_to_integer(&ctx->ac, src[0]);
1932 result = ac_find_lsb(&ctx->ac, ctx->ac.i32, src[0]);
1933 break;
1934 case nir_op_ufind_msb:
1935 src[0] = ac_to_integer(&ctx->ac, src[0]);
1936 result = ac_build_umsb(&ctx->ac, src[0], ctx->ac.i32);
1937 break;
1938 case nir_op_ifind_msb:
1939 src[0] = ac_to_integer(&ctx->ac, src[0]);
1940 result = ac_build_imsb(&ctx->ac, src[0], ctx->ac.i32);
1941 break;
1942 case nir_op_uadd_carry:
1943 src[0] = ac_to_integer(&ctx->ac, src[0]);
1944 src[1] = ac_to_integer(&ctx->ac, src[1]);
1945 result = emit_uint_carry(&ctx->ac, "llvm.uadd.with.overflow.i32", src[0], src[1]);
1946 break;
1947 case nir_op_usub_borrow:
1948 src[0] = ac_to_integer(&ctx->ac, src[0]);
1949 src[1] = ac_to_integer(&ctx->ac, src[1]);
1950 result = emit_uint_carry(&ctx->ac, "llvm.usub.with.overflow.i32", src[0], src[1]);
1951 break;
1952 case nir_op_b2f:
1953 result = emit_b2f(&ctx->ac, src[0]);
1954 break;
1955 case nir_op_f2b:
1956 result = emit_f2b(&ctx->ac, src[0]);
1957 break;
1958 case nir_op_b2i:
1959 result = emit_b2i(&ctx->ac, src[0]);
1960 break;
1961 case nir_op_i2b:
1962 src[0] = ac_to_integer(&ctx->ac, src[0]);
1963 result = emit_i2b(&ctx->ac, src[0]);
1964 break;
1965 case nir_op_fquantize2f16:
1966 result = emit_f2f16(ctx->nctx, src[0]);
1967 break;
1968 case nir_op_umul_high:
1969 src[0] = ac_to_integer(&ctx->ac, src[0]);
1970 src[1] = ac_to_integer(&ctx->ac, src[1]);
1971 result = emit_umul_high(&ctx->ac, src[0], src[1]);
1972 break;
1973 case nir_op_imul_high:
1974 src[0] = ac_to_integer(&ctx->ac, src[0]);
1975 src[1] = ac_to_integer(&ctx->ac, src[1]);
1976 result = emit_imul_high(&ctx->ac, src[0], src[1]);
1977 break;
1978 case nir_op_pack_half_2x16:
1979 result = emit_pack_half_2x16(&ctx->ac, src[0]);
1980 break;
1981 case nir_op_unpack_half_2x16:
1982 result = emit_unpack_half_2x16(&ctx->ac, src[0]);
1983 break;
1984 case nir_op_fddx:
1985 case nir_op_fddy:
1986 case nir_op_fddx_fine:
1987 case nir_op_fddy_fine:
1988 case nir_op_fddx_coarse:
1989 case nir_op_fddy_coarse:
1990 result = emit_ddxy(ctx, instr->op, src[0]);
1991 break;
1992
1993 case nir_op_unpack_64_2x32_split_x: {
1994 assert(instr->src[0].src.ssa->num_components == 1);
1995 LLVMValueRef tmp = LLVMBuildBitCast(ctx->ac.builder, src[0],
1996 ctx->ac.v2i32,
1997 "");
1998 result = LLVMBuildExtractElement(ctx->ac.builder, tmp,
1999 ctx->ac.i32_0, "");
2000 break;
2001 }
2002
2003 case nir_op_unpack_64_2x32_split_y: {
2004 assert(instr->src[0].src.ssa->num_components == 1);
2005 LLVMValueRef tmp = LLVMBuildBitCast(ctx->ac.builder, src[0],
2006 ctx->ac.v2i32,
2007 "");
2008 result = LLVMBuildExtractElement(ctx->ac.builder, tmp,
2009 ctx->ac.i32_1, "");
2010 break;
2011 }
2012
2013 case nir_op_pack_64_2x32_split: {
2014 LLVMValueRef tmp = LLVMGetUndef(ctx->ac.v2i32);
2015 tmp = LLVMBuildInsertElement(ctx->ac.builder, tmp,
2016 src[0], ctx->ac.i32_0, "");
2017 tmp = LLVMBuildInsertElement(ctx->ac.builder, tmp,
2018 src[1], ctx->ac.i32_1, "");
2019 result = LLVMBuildBitCast(ctx->ac.builder, tmp, ctx->ac.i64, "");
2020 break;
2021 }
2022
2023 default:
2024 fprintf(stderr, "Unknown NIR alu instr: ");
2025 nir_print_instr(&instr->instr, stderr);
2026 fprintf(stderr, "\n");
2027 abort();
2028 }
2029
2030 if (result) {
2031 assert(instr->dest.dest.is_ssa);
2032 result = ac_to_integer(&ctx->ac, result);
2033 _mesa_hash_table_insert(ctx->defs, &instr->dest.dest.ssa,
2034 result);
2035 }
2036 }
2037
2038 static void visit_load_const(struct ac_nir_context *ctx,
2039 const nir_load_const_instr *instr)
2040 {
2041 LLVMValueRef values[4], value = NULL;
2042 LLVMTypeRef element_type =
2043 LLVMIntTypeInContext(ctx->ac.context, instr->def.bit_size);
2044
2045 for (unsigned i = 0; i < instr->def.num_components; ++i) {
2046 switch (instr->def.bit_size) {
2047 case 32:
2048 values[i] = LLVMConstInt(element_type,
2049 instr->value.u32[i], false);
2050 break;
2051 case 64:
2052 values[i] = LLVMConstInt(element_type,
2053 instr->value.u64[i], false);
2054 break;
2055 default:
2056 fprintf(stderr,
2057 "unsupported nir load_const bit_size: %d\n",
2058 instr->def.bit_size);
2059 abort();
2060 }
2061 }
2062 if (instr->def.num_components > 1) {
2063 value = LLVMConstVector(values, instr->def.num_components);
2064 } else
2065 value = values[0];
2066
2067 _mesa_hash_table_insert(ctx->defs, &instr->def, value);
2068 }
2069
2070 static LLVMValueRef cast_ptr(struct nir_to_llvm_context *ctx, LLVMValueRef ptr,
2071 LLVMTypeRef type)
2072 {
2073 int addr_space = LLVMGetPointerAddressSpace(LLVMTypeOf(ptr));
2074 return LLVMBuildBitCast(ctx->builder, ptr,
2075 LLVMPointerType(type, addr_space), "");
2076 }
2077
2078 static LLVMValueRef
2079 get_buffer_size(struct ac_nir_context *ctx, LLVMValueRef descriptor, bool in_elements)
2080 {
2081 LLVMValueRef size =
2082 LLVMBuildExtractElement(ctx->ac.builder, descriptor,
2083 LLVMConstInt(ctx->ac.i32, 2, false), "");
2084
2085 /* VI only */
2086 if (ctx->ac.chip_class == VI && in_elements) {
2087 /* On VI, the descriptor contains the size in bytes,
2088 * but TXQ must return the size in elements.
2089 * The stride is always non-zero for resources using TXQ.
2090 */
2091 LLVMValueRef stride =
2092 LLVMBuildExtractElement(ctx->ac.builder, descriptor,
2093 ctx->ac.i32_1, "");
2094 stride = LLVMBuildLShr(ctx->ac.builder, stride,
2095 LLVMConstInt(ctx->ac.i32, 16, false), "");
2096 stride = LLVMBuildAnd(ctx->ac.builder, stride,
2097 LLVMConstInt(ctx->ac.i32, 0x3fff, false), "");
2098
2099 size = LLVMBuildUDiv(ctx->ac.builder, size, stride, "");
2100 }
2101 return size;
2102 }
2103
2104 /**
2105 * Given the i32 or vNi32 \p type, generate the textual name (e.g. for use with
2106 * intrinsic names).
2107 */
2108 static void build_int_type_name(
2109 LLVMTypeRef type,
2110 char *buf, unsigned bufsize)
2111 {
2112 assert(bufsize >= 6);
2113
2114 if (LLVMGetTypeKind(type) == LLVMVectorTypeKind)
2115 snprintf(buf, bufsize, "v%ui32",
2116 LLVMGetVectorSize(type));
2117 else
2118 strcpy(buf, "i32");
2119 }
2120
2121 static LLVMValueRef radv_lower_gather4_integer(struct ac_llvm_context *ctx,
2122 struct ac_image_args *args,
2123 const nir_tex_instr *instr)
2124 {
2125 enum glsl_base_type stype = glsl_get_sampler_result_type(instr->texture->var->type);
2126 LLVMValueRef coord = args->addr;
2127 LLVMValueRef half_texel[2];
2128 LLVMValueRef compare_cube_wa = NULL;
2129 LLVMValueRef result;
2130 int c;
2131 unsigned coord_vgpr_index = (unsigned)args->offset + (unsigned)args->compare;
2132
2133 //TODO Rect
2134 {
2135 struct ac_image_args txq_args = { 0 };
2136
2137 txq_args.da = instr->is_array || instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE;
2138 txq_args.opcode = ac_image_get_resinfo;
2139 txq_args.dmask = 0xf;
2140 txq_args.addr = ctx->i32_0;
2141 txq_args.resource = args->resource;
2142 LLVMValueRef size = ac_build_image_opcode(ctx, &txq_args);
2143
2144 for (c = 0; c < 2; c++) {
2145 half_texel[c] = LLVMBuildExtractElement(ctx->builder, size,
2146 LLVMConstInt(ctx->i32, c, false), "");
2147 half_texel[c] = LLVMBuildUIToFP(ctx->builder, half_texel[c], ctx->f32, "");
2148 half_texel[c] = ac_build_fdiv(ctx, ctx->f32_1, half_texel[c]);
2149 half_texel[c] = LLVMBuildFMul(ctx->builder, half_texel[c],
2150 LLVMConstReal(ctx->f32, -0.5), "");
2151 }
2152 }
2153
2154 LLVMValueRef orig_coords = args->addr;
2155
2156 for (c = 0; c < 2; c++) {
2157 LLVMValueRef tmp;
2158 LLVMValueRef index = LLVMConstInt(ctx->i32, coord_vgpr_index + c, 0);
2159 tmp = LLVMBuildExtractElement(ctx->builder, coord, index, "");
2160 tmp = LLVMBuildBitCast(ctx->builder, tmp, ctx->f32, "");
2161 tmp = LLVMBuildFAdd(ctx->builder, tmp, half_texel[c], "");
2162 tmp = LLVMBuildBitCast(ctx->builder, tmp, ctx->i32, "");
2163 coord = LLVMBuildInsertElement(ctx->builder, coord, tmp, index, "");
2164 }
2165
2166
2167 /*
2168 * Apparantly cube has issue with integer types that the workaround doesn't solve,
2169 * so this tests if the format is 8_8_8_8 and an integer type do an alternate
2170 * workaround by sampling using a scaled type and converting.
2171 * This is taken from amdgpu-pro shaders.
2172 */
2173 /* NOTE this produces some ugly code compared to amdgpu-pro,
2174 * LLVM ends up dumping SGPRs into VGPRs to deal with the compare/select,
2175 * and then reads them back. -pro generates two selects,
2176 * one s_cmp for the descriptor rewriting
2177 * one v_cmp for the coordinate and result changes.
2178 */
2179 if (instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE) {
2180 LLVMValueRef tmp, tmp2;
2181
2182 /* workaround 8/8/8/8 uint/sint cube gather bug */
2183 /* first detect it then change to a scaled read and f2i */
2184 tmp = LLVMBuildExtractElement(ctx->builder, args->resource, ctx->i32_1, "");
2185 tmp2 = tmp;
2186
2187 /* extract the DATA_FORMAT */
2188 tmp = ac_build_bfe(ctx, tmp, LLVMConstInt(ctx->i32, 20, false),
2189 LLVMConstInt(ctx->i32, 6, false), false);
2190
2191 /* is the DATA_FORMAT == 8_8_8_8 */
2192 compare_cube_wa = LLVMBuildICmp(ctx->builder, LLVMIntEQ, tmp, LLVMConstInt(ctx->i32, V_008F14_IMG_DATA_FORMAT_8_8_8_8, false), "");
2193
2194 if (stype == GLSL_TYPE_UINT)
2195 /* Create a NUM FORMAT - 0x2 or 0x4 - USCALED or UINT */
2196 tmp = LLVMBuildSelect(ctx->builder, compare_cube_wa, LLVMConstInt(ctx->i32, 0x8000000, false),
2197 LLVMConstInt(ctx->i32, 0x10000000, false), "");
2198 else
2199 /* Create a NUM FORMAT - 0x3 or 0x5 - SSCALED or SINT */
2200 tmp = LLVMBuildSelect(ctx->builder, compare_cube_wa, LLVMConstInt(ctx->i32, 0xc000000, false),
2201 LLVMConstInt(ctx->i32, 0x14000000, false), "");
2202
2203 /* replace the NUM FORMAT in the descriptor */
2204 tmp2 = LLVMBuildAnd(ctx->builder, tmp2, LLVMConstInt(ctx->i32, C_008F14_NUM_FORMAT_GFX6, false), "");
2205 tmp2 = LLVMBuildOr(ctx->builder, tmp2, tmp, "");
2206
2207 args->resource = LLVMBuildInsertElement(ctx->builder, args->resource, tmp2, ctx->i32_1, "");
2208
2209 /* don't modify the coordinates for this case */
2210 coord = LLVMBuildSelect(ctx->builder, compare_cube_wa, orig_coords, coord, "");
2211 }
2212 args->addr = coord;
2213 result = ac_build_image_opcode(ctx, args);
2214
2215 if (instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE) {
2216 LLVMValueRef tmp, tmp2;
2217
2218 /* if the cube workaround is in place, f2i the result. */
2219 for (c = 0; c < 4; c++) {
2220 tmp = LLVMBuildExtractElement(ctx->builder, result, LLVMConstInt(ctx->i32, c, false), "");
2221 if (stype == GLSL_TYPE_UINT)
2222 tmp2 = LLVMBuildFPToUI(ctx->builder, tmp, ctx->i32, "");
2223 else
2224 tmp2 = LLVMBuildFPToSI(ctx->builder, tmp, ctx->i32, "");
2225 tmp = LLVMBuildBitCast(ctx->builder, tmp, ctx->i32, "");
2226 tmp2 = LLVMBuildBitCast(ctx->builder, tmp2, ctx->i32, "");
2227 tmp = LLVMBuildSelect(ctx->builder, compare_cube_wa, tmp2, tmp, "");
2228 tmp = LLVMBuildBitCast(ctx->builder, tmp, ctx->f32, "");
2229 result = LLVMBuildInsertElement(ctx->builder, result, tmp, LLVMConstInt(ctx->i32, c, false), "");
2230 }
2231 }
2232 return result;
2233 }
2234
2235 static LLVMValueRef build_tex_intrinsic(struct ac_nir_context *ctx,
2236 const nir_tex_instr *instr,
2237 bool lod_is_zero,
2238 struct ac_image_args *args)
2239 {
2240 if (instr->sampler_dim == GLSL_SAMPLER_DIM_BUF) {
2241 return ac_build_buffer_load_format(&ctx->ac,
2242 args->resource,
2243 args->addr,
2244 ctx->ac.i32_0,
2245 true);
2246 }
2247
2248 args->opcode = ac_image_sample;
2249 args->compare = instr->is_shadow;
2250
2251 switch (instr->op) {
2252 case nir_texop_txf:
2253 case nir_texop_txf_ms:
2254 case nir_texop_samples_identical:
2255 args->opcode = instr->sampler_dim == GLSL_SAMPLER_DIM_MS ? ac_image_load : ac_image_load_mip;
2256 args->compare = false;
2257 args->offset = false;
2258 break;
2259 case nir_texop_txb:
2260 args->bias = true;
2261 break;
2262 case nir_texop_txl:
2263 if (lod_is_zero)
2264 args->level_zero = true;
2265 else
2266 args->lod = true;
2267 break;
2268 case nir_texop_txs:
2269 case nir_texop_query_levels:
2270 args->opcode = ac_image_get_resinfo;
2271 break;
2272 case nir_texop_tex:
2273 if (ctx->stage != MESA_SHADER_FRAGMENT)
2274 args->level_zero = true;
2275 break;
2276 case nir_texop_txd:
2277 args->deriv = true;
2278 break;
2279 case nir_texop_tg4:
2280 args->opcode = ac_image_gather4;
2281 args->level_zero = true;
2282 break;
2283 case nir_texop_lod:
2284 args->opcode = ac_image_get_lod;
2285 args->compare = false;
2286 args->offset = false;
2287 break;
2288 default:
2289 break;
2290 }
2291
2292 if (instr->op == nir_texop_tg4 && ctx->ac.chip_class <= VI) {
2293 enum glsl_base_type stype = glsl_get_sampler_result_type(instr->texture->var->type);
2294 if (stype == GLSL_TYPE_UINT || stype == GLSL_TYPE_INT) {
2295 return radv_lower_gather4_integer(&ctx->ac, args, instr);
2296 }
2297 }
2298 return ac_build_image_opcode(&ctx->ac, args);
2299 }
2300
2301 static LLVMValueRef visit_vulkan_resource_index(struct nir_to_llvm_context *ctx,
2302 nir_intrinsic_instr *instr)
2303 {
2304 LLVMValueRef index = get_src(ctx->nir, instr->src[0]);
2305 unsigned desc_set = nir_intrinsic_desc_set(instr);
2306 unsigned binding = nir_intrinsic_binding(instr);
2307 LLVMValueRef desc_ptr = ctx->descriptor_sets[desc_set];
2308 struct radv_pipeline_layout *pipeline_layout = ctx->options->layout;
2309 struct radv_descriptor_set_layout *layout = pipeline_layout->set[desc_set].layout;
2310 unsigned base_offset = layout->binding[binding].offset;
2311 LLVMValueRef offset, stride;
2312
2313 if (layout->binding[binding].type == VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER_DYNAMIC ||
2314 layout->binding[binding].type == VK_DESCRIPTOR_TYPE_STORAGE_BUFFER_DYNAMIC) {
2315 unsigned idx = pipeline_layout->set[desc_set].dynamic_offset_start +
2316 layout->binding[binding].dynamic_offset_offset;
2317 desc_ptr = ctx->push_constants;
2318 base_offset = pipeline_layout->push_constant_size + 16 * idx;
2319 stride = LLVMConstInt(ctx->ac.i32, 16, false);
2320 } else
2321 stride = LLVMConstInt(ctx->ac.i32, layout->binding[binding].size, false);
2322
2323 offset = LLVMConstInt(ctx->ac.i32, base_offset, false);
2324 index = LLVMBuildMul(ctx->builder, index, stride, "");
2325 offset = LLVMBuildAdd(ctx->builder, offset, index, "");
2326
2327 desc_ptr = ac_build_gep0(&ctx->ac, desc_ptr, offset);
2328 desc_ptr = cast_ptr(ctx, desc_ptr, ctx->ac.v4i32);
2329 LLVMSetMetadata(desc_ptr, ctx->ac.uniform_md_kind, ctx->ac.empty_md);
2330
2331 return desc_ptr;
2332 }
2333
2334 static LLVMValueRef visit_vulkan_resource_reindex(struct nir_to_llvm_context *ctx,
2335 nir_intrinsic_instr *instr)
2336 {
2337 LLVMValueRef ptr = get_src(ctx->nir, instr->src[0]);
2338 LLVMValueRef index = get_src(ctx->nir, instr->src[1]);
2339
2340 LLVMValueRef result = LLVMBuildGEP(ctx->builder, ptr, &index, 1, "");
2341 LLVMSetMetadata(result, ctx->ac.uniform_md_kind, ctx->ac.empty_md);
2342 return result;
2343 }
2344
2345 static LLVMValueRef visit_load_push_constant(struct nir_to_llvm_context *ctx,
2346 nir_intrinsic_instr *instr)
2347 {
2348 LLVMValueRef ptr, addr;
2349
2350 addr = LLVMConstInt(ctx->ac.i32, nir_intrinsic_base(instr), 0);
2351 addr = LLVMBuildAdd(ctx->builder, addr, get_src(ctx->nir, instr->src[0]), "");
2352
2353 ptr = ac_build_gep0(&ctx->ac, ctx->push_constants, addr);
2354 ptr = cast_ptr(ctx, ptr, get_def_type(ctx->nir, &instr->dest.ssa));
2355
2356 return LLVMBuildLoad(ctx->builder, ptr, "");
2357 }
2358
2359 static LLVMValueRef visit_get_buffer_size(struct ac_nir_context *ctx,
2360 const nir_intrinsic_instr *instr)
2361 {
2362 LLVMValueRef ptr = get_src(ctx, instr->src[0]);
2363
2364 return get_buffer_size(ctx, LLVMBuildLoad(ctx->ac.builder, ptr, ""), false);
2365 }
2366 static void visit_store_ssbo(struct ac_nir_context *ctx,
2367 nir_intrinsic_instr *instr)
2368 {
2369 const char *store_name;
2370 LLVMValueRef src_data = get_src(ctx, instr->src[0]);
2371 LLVMTypeRef data_type = ctx->ac.f32;
2372 int elem_size_mult = get_elem_bits(&ctx->ac, LLVMTypeOf(src_data)) / 32;
2373 int components_32bit = elem_size_mult * instr->num_components;
2374 unsigned writemask = nir_intrinsic_write_mask(instr);
2375 LLVMValueRef base_data, base_offset;
2376 LLVMValueRef params[6];
2377
2378 params[1] = ctx->abi->load_ssbo(ctx->abi,
2379 get_src(ctx, instr->src[1]), true);
2380 params[2] = ctx->ac.i32_0; /* vindex */
2381 params[4] = ctx->ac.i1false; /* glc */
2382 params[5] = ctx->ac.i1false; /* slc */
2383
2384 if (components_32bit > 1)
2385 data_type = LLVMVectorType(ctx->ac.f32, components_32bit);
2386
2387 base_data = ac_to_float(&ctx->ac, src_data);
2388 base_data = trim_vector(&ctx->ac, base_data, instr->num_components);
2389 base_data = LLVMBuildBitCast(ctx->ac.builder, base_data,
2390 data_type, "");
2391 base_offset = get_src(ctx, instr->src[2]); /* voffset */
2392 while (writemask) {
2393 int start, count;
2394 LLVMValueRef data;
2395 LLVMValueRef offset;
2396 LLVMValueRef tmp;
2397 u_bit_scan_consecutive_range(&writemask, &start, &count);
2398
2399 /* Due to an LLVM limitation, split 3-element writes
2400 * into a 2-element and a 1-element write. */
2401 if (count == 3) {
2402 writemask |= 1 << (start + 2);
2403 count = 2;
2404 }
2405
2406 start *= elem_size_mult;
2407 count *= elem_size_mult;
2408
2409 if (count > 4) {
2410 writemask |= ((1u << (count - 4)) - 1u) << (start + 4);
2411 count = 4;
2412 }
2413
2414 if (count == 4) {
2415 store_name = "llvm.amdgcn.buffer.store.v4f32";
2416 data = base_data;
2417 } else if (count == 2) {
2418 tmp = LLVMBuildExtractElement(ctx->ac.builder,
2419 base_data, LLVMConstInt(ctx->ac.i32, start, false), "");
2420 data = LLVMBuildInsertElement(ctx->ac.builder, LLVMGetUndef(ctx->ac.v2f32), tmp,
2421 ctx->ac.i32_0, "");
2422
2423 tmp = LLVMBuildExtractElement(ctx->ac.builder,
2424 base_data, LLVMConstInt(ctx->ac.i32, start + 1, false), "");
2425 data = LLVMBuildInsertElement(ctx->ac.builder, data, tmp,
2426 ctx->ac.i32_1, "");
2427 store_name = "llvm.amdgcn.buffer.store.v2f32";
2428
2429 } else {
2430 assert(count == 1);
2431 if (ac_get_llvm_num_components(base_data) > 1)
2432 data = LLVMBuildExtractElement(ctx->ac.builder, base_data,
2433 LLVMConstInt(ctx->ac.i32, start, false), "");
2434 else
2435 data = base_data;
2436 store_name = "llvm.amdgcn.buffer.store.f32";
2437 }
2438
2439 offset = base_offset;
2440 if (start != 0) {
2441 offset = LLVMBuildAdd(ctx->ac.builder, offset, LLVMConstInt(ctx->ac.i32, start * 4, false), "");
2442 }
2443 params[0] = data;
2444 params[3] = offset;
2445 ac_build_intrinsic(&ctx->ac, store_name,
2446 ctx->ac.voidt, params, 6, 0);
2447 }
2448 }
2449
2450 static LLVMValueRef visit_atomic_ssbo(struct ac_nir_context *ctx,
2451 const nir_intrinsic_instr *instr)
2452 {
2453 const char *name;
2454 LLVMValueRef params[6];
2455 int arg_count = 0;
2456
2457 if (instr->intrinsic == nir_intrinsic_ssbo_atomic_comp_swap) {
2458 params[arg_count++] = ac_llvm_extract_elem(&ctx->ac, get_src(ctx, instr->src[3]), 0);
2459 }
2460 params[arg_count++] = ac_llvm_extract_elem(&ctx->ac, get_src(ctx, instr->src[2]), 0);
2461 params[arg_count++] = ctx->abi->load_ssbo(ctx->abi,
2462 get_src(ctx, instr->src[0]),
2463 true);
2464 params[arg_count++] = ctx->ac.i32_0; /* vindex */
2465 params[arg_count++] = get_src(ctx, instr->src[1]); /* voffset */
2466 params[arg_count++] = LLVMConstInt(ctx->ac.i1, 0, false); /* slc */
2467
2468 switch (instr->intrinsic) {
2469 case nir_intrinsic_ssbo_atomic_add:
2470 name = "llvm.amdgcn.buffer.atomic.add";
2471 break;
2472 case nir_intrinsic_ssbo_atomic_imin:
2473 name = "llvm.amdgcn.buffer.atomic.smin";
2474 break;
2475 case nir_intrinsic_ssbo_atomic_umin:
2476 name = "llvm.amdgcn.buffer.atomic.umin";
2477 break;
2478 case nir_intrinsic_ssbo_atomic_imax:
2479 name = "llvm.amdgcn.buffer.atomic.smax";
2480 break;
2481 case nir_intrinsic_ssbo_atomic_umax:
2482 name = "llvm.amdgcn.buffer.atomic.umax";
2483 break;
2484 case nir_intrinsic_ssbo_atomic_and:
2485 name = "llvm.amdgcn.buffer.atomic.and";
2486 break;
2487 case nir_intrinsic_ssbo_atomic_or:
2488 name = "llvm.amdgcn.buffer.atomic.or";
2489 break;
2490 case nir_intrinsic_ssbo_atomic_xor:
2491 name = "llvm.amdgcn.buffer.atomic.xor";
2492 break;
2493 case nir_intrinsic_ssbo_atomic_exchange:
2494 name = "llvm.amdgcn.buffer.atomic.swap";
2495 break;
2496 case nir_intrinsic_ssbo_atomic_comp_swap:
2497 name = "llvm.amdgcn.buffer.atomic.cmpswap";
2498 break;
2499 default:
2500 abort();
2501 }
2502
2503 return ac_build_intrinsic(&ctx->ac, name, ctx->ac.i32, params, arg_count, 0);
2504 }
2505
2506 static LLVMValueRef visit_load_buffer(struct ac_nir_context *ctx,
2507 const nir_intrinsic_instr *instr)
2508 {
2509 LLVMValueRef results[2];
2510 int load_components;
2511 int num_components = instr->num_components;
2512 if (instr->dest.ssa.bit_size == 64)
2513 num_components *= 2;
2514
2515 for (int i = 0; i < num_components; i += load_components) {
2516 load_components = MIN2(num_components - i, 4);
2517 const char *load_name;
2518 LLVMTypeRef data_type = ctx->ac.f32;
2519 LLVMValueRef offset = LLVMConstInt(ctx->ac.i32, i * 4, false);
2520 offset = LLVMBuildAdd(ctx->ac.builder, get_src(ctx, instr->src[1]), offset, "");
2521
2522 if (load_components == 3)
2523 data_type = LLVMVectorType(ctx->ac.f32, 4);
2524 else if (load_components > 1)
2525 data_type = LLVMVectorType(ctx->ac.f32, load_components);
2526
2527 if (load_components >= 3)
2528 load_name = "llvm.amdgcn.buffer.load.v4f32";
2529 else if (load_components == 2)
2530 load_name = "llvm.amdgcn.buffer.load.v2f32";
2531 else if (load_components == 1)
2532 load_name = "llvm.amdgcn.buffer.load.f32";
2533 else
2534 unreachable("unhandled number of components");
2535
2536 LLVMValueRef params[] = {
2537 ctx->abi->load_ssbo(ctx->abi,
2538 get_src(ctx, instr->src[0]),
2539 false),
2540 ctx->ac.i32_0,
2541 offset,
2542 ctx->ac.i1false,
2543 ctx->ac.i1false,
2544 };
2545
2546 results[i] = ac_build_intrinsic(&ctx->ac, load_name, data_type, params, 5, 0);
2547
2548 }
2549
2550 assume(results[0]);
2551 LLVMValueRef ret = results[0];
2552 if (num_components > 4 || num_components == 3) {
2553 LLVMValueRef masks[] = {
2554 LLVMConstInt(ctx->ac.i32, 0, false), LLVMConstInt(ctx->ac.i32, 1, false),
2555 LLVMConstInt(ctx->ac.i32, 2, false), LLVMConstInt(ctx->ac.i32, 3, false),
2556 LLVMConstInt(ctx->ac.i32, 4, false), LLVMConstInt(ctx->ac.i32, 5, false),
2557 LLVMConstInt(ctx->ac.i32, 6, false), LLVMConstInt(ctx->ac.i32, 7, false)
2558 };
2559
2560 LLVMValueRef swizzle = LLVMConstVector(masks, num_components);
2561 ret = LLVMBuildShuffleVector(ctx->ac.builder, results[0],
2562 results[num_components > 4 ? 1 : 0], swizzle, "");
2563 }
2564
2565 return LLVMBuildBitCast(ctx->ac.builder, ret,
2566 get_def_type(ctx, &instr->dest.ssa), "");
2567 }
2568
2569 static LLVMValueRef visit_load_ubo_buffer(struct ac_nir_context *ctx,
2570 const nir_intrinsic_instr *instr)
2571 {
2572 LLVMValueRef results[8], ret;
2573 LLVMValueRef rsrc = get_src(ctx, instr->src[0]);
2574 LLVMValueRef offset = get_src(ctx, instr->src[1]);
2575 int num_components = instr->num_components;
2576
2577 if (ctx->abi->load_ubo)
2578 rsrc = ctx->abi->load_ubo(ctx->abi, rsrc);
2579
2580 if (instr->dest.ssa.bit_size == 64)
2581 num_components *= 2;
2582
2583 for (unsigned i = 0; i < num_components; ++i) {
2584 LLVMValueRef params[] = {
2585 rsrc,
2586 LLVMBuildAdd(ctx->ac.builder, LLVMConstInt(ctx->ac.i32, 4 * i, 0),
2587 offset, "")
2588 };
2589 results[i] = ac_build_intrinsic(&ctx->ac, "llvm.SI.load.const.v4i32", ctx->ac.f32,
2590 params, 2,
2591 AC_FUNC_ATTR_READNONE |
2592 AC_FUNC_ATTR_LEGACY);
2593 }
2594
2595
2596 ret = ac_build_gather_values(&ctx->ac, results, num_components);
2597 return LLVMBuildBitCast(ctx->ac.builder, ret,
2598 get_def_type(ctx, &instr->dest.ssa), "");
2599 }
2600
2601 static void
2602 get_deref_offset(struct ac_nir_context *ctx, nir_deref_var *deref,
2603 bool vs_in, unsigned *vertex_index_out,
2604 LLVMValueRef *vertex_index_ref,
2605 unsigned *const_out, LLVMValueRef *indir_out)
2606 {
2607 unsigned const_offset = 0;
2608 nir_deref *tail = &deref->deref;
2609 LLVMValueRef offset = NULL;
2610
2611 if (vertex_index_out != NULL || vertex_index_ref != NULL) {
2612 tail = tail->child;
2613 nir_deref_array *deref_array = nir_deref_as_array(tail);
2614 if (vertex_index_out)
2615 *vertex_index_out = deref_array->base_offset;
2616
2617 if (vertex_index_ref) {
2618 LLVMValueRef vtx = LLVMConstInt(ctx->ac.i32, deref_array->base_offset, false);
2619 if (deref_array->deref_array_type == nir_deref_array_type_indirect) {
2620 vtx = LLVMBuildAdd(ctx->ac.builder, vtx, get_src(ctx, deref_array->indirect), "");
2621 }
2622 *vertex_index_ref = vtx;
2623 }
2624 }
2625
2626 if (deref->var->data.compact) {
2627 assert(tail->child->deref_type == nir_deref_type_array);
2628 assert(glsl_type_is_scalar(glsl_without_array(deref->var->type)));
2629 nir_deref_array *deref_array = nir_deref_as_array(tail->child);
2630 /* We always lower indirect dereferences for "compact" array vars. */
2631 assert(deref_array->deref_array_type == nir_deref_array_type_direct);
2632
2633 const_offset = deref_array->base_offset;
2634 goto out;
2635 }
2636
2637 while (tail->child != NULL) {
2638 const struct glsl_type *parent_type = tail->type;
2639 tail = tail->child;
2640
2641 if (tail->deref_type == nir_deref_type_array) {
2642 nir_deref_array *deref_array = nir_deref_as_array(tail);
2643 LLVMValueRef index, stride, local_offset;
2644 unsigned size = glsl_count_attribute_slots(tail->type, vs_in);
2645
2646 const_offset += size * deref_array->base_offset;
2647 if (deref_array->deref_array_type == nir_deref_array_type_direct)
2648 continue;
2649
2650 assert(deref_array->deref_array_type == nir_deref_array_type_indirect);
2651 index = get_src(ctx, deref_array->indirect);
2652 stride = LLVMConstInt(ctx->ac.i32, size, 0);
2653 local_offset = LLVMBuildMul(ctx->ac.builder, stride, index, "");
2654
2655 if (offset)
2656 offset = LLVMBuildAdd(ctx->ac.builder, offset, local_offset, "");
2657 else
2658 offset = local_offset;
2659 } else if (tail->deref_type == nir_deref_type_struct) {
2660 nir_deref_struct *deref_struct = nir_deref_as_struct(tail);
2661
2662 for (unsigned i = 0; i < deref_struct->index; i++) {
2663 const struct glsl_type *ft = glsl_get_struct_field(parent_type, i);
2664 const_offset += glsl_count_attribute_slots(ft, vs_in);
2665 }
2666 } else
2667 unreachable("unsupported deref type");
2668
2669 }
2670 out:
2671 if (const_offset && offset)
2672 offset = LLVMBuildAdd(ctx->ac.builder, offset,
2673 LLVMConstInt(ctx->ac.i32, const_offset, 0),
2674 "");
2675
2676 *const_out = const_offset;
2677 *indir_out = offset;
2678 }
2679
2680
2681 /* The offchip buffer layout for TCS->TES is
2682 *
2683 * - attribute 0 of patch 0 vertex 0
2684 * - attribute 0 of patch 0 vertex 1
2685 * - attribute 0 of patch 0 vertex 2
2686 * ...
2687 * - attribute 0 of patch 1 vertex 0
2688 * - attribute 0 of patch 1 vertex 1
2689 * ...
2690 * - attribute 1 of patch 0 vertex 0
2691 * - attribute 1 of patch 0 vertex 1
2692 * ...
2693 * - per patch attribute 0 of patch 0
2694 * - per patch attribute 0 of patch 1
2695 * ...
2696 *
2697 * Note that every attribute has 4 components.
2698 */
2699 static LLVMValueRef get_tcs_tes_buffer_address(struct nir_to_llvm_context *ctx,
2700 LLVMValueRef vertex_index,
2701 LLVMValueRef param_index)
2702 {
2703 LLVMValueRef base_addr, vertices_per_patch, num_patches, total_vertices;
2704 LLVMValueRef param_stride, constant16;
2705 LLVMValueRef rel_patch_id = get_rel_patch_id(ctx);
2706
2707 vertices_per_patch = unpack_param(&ctx->ac, ctx->tcs_offchip_layout, 9, 6);
2708 num_patches = unpack_param(&ctx->ac, ctx->tcs_offchip_layout, 0, 9);
2709 total_vertices = LLVMBuildMul(ctx->builder, vertices_per_patch,
2710 num_patches, "");
2711
2712 constant16 = LLVMConstInt(ctx->ac.i32, 16, false);
2713 if (vertex_index) {
2714 base_addr = LLVMBuildMul(ctx->builder, rel_patch_id,
2715 vertices_per_patch, "");
2716
2717 base_addr = LLVMBuildAdd(ctx->builder, base_addr,
2718 vertex_index, "");
2719
2720 param_stride = total_vertices;
2721 } else {
2722 base_addr = rel_patch_id;
2723 param_stride = num_patches;
2724 }
2725
2726 base_addr = LLVMBuildAdd(ctx->builder, base_addr,
2727 LLVMBuildMul(ctx->builder, param_index,
2728 param_stride, ""), "");
2729
2730 base_addr = LLVMBuildMul(ctx->builder, base_addr, constant16, "");
2731
2732 if (!vertex_index) {
2733 LLVMValueRef patch_data_offset =
2734 unpack_param(&ctx->ac, ctx->tcs_offchip_layout, 16, 16);
2735
2736 base_addr = LLVMBuildAdd(ctx->builder, base_addr,
2737 patch_data_offset, "");
2738 }
2739 return base_addr;
2740 }
2741
2742 static LLVMValueRef get_tcs_tes_buffer_address_params(struct nir_to_llvm_context *ctx,
2743 unsigned param,
2744 unsigned const_index,
2745 bool is_compact,
2746 LLVMValueRef vertex_index,
2747 LLVMValueRef indir_index)
2748 {
2749 LLVMValueRef param_index;
2750
2751 if (indir_index)
2752 param_index = LLVMBuildAdd(ctx->builder, LLVMConstInt(ctx->ac.i32, param, false),
2753 indir_index, "");
2754 else {
2755 if (const_index && !is_compact)
2756 param += const_index;
2757 param_index = LLVMConstInt(ctx->ac.i32, param, false);
2758 }
2759 return get_tcs_tes_buffer_address(ctx, vertex_index, param_index);
2760 }
2761
2762 static void
2763 mark_tess_output(struct nir_to_llvm_context *ctx,
2764 bool is_patch, uint32_t param)
2765
2766 {
2767 if (is_patch) {
2768 ctx->tess_patch_outputs_written |= (1ull << param);
2769 } else
2770 ctx->tess_outputs_written |= (1ull << param);
2771 }
2772
2773 static LLVMValueRef
2774 get_dw_address(struct nir_to_llvm_context *ctx,
2775 LLVMValueRef dw_addr,
2776 unsigned param,
2777 unsigned const_index,
2778 bool compact_const_index,
2779 LLVMValueRef vertex_index,
2780 LLVMValueRef stride,
2781 LLVMValueRef indir_index)
2782
2783 {
2784
2785 if (vertex_index) {
2786 dw_addr = LLVMBuildAdd(ctx->builder, dw_addr,
2787 LLVMBuildMul(ctx->builder,
2788 vertex_index,
2789 stride, ""), "");
2790 }
2791
2792 if (indir_index)
2793 dw_addr = LLVMBuildAdd(ctx->builder, dw_addr,
2794 LLVMBuildMul(ctx->builder, indir_index,
2795 LLVMConstInt(ctx->ac.i32, 4, false), ""), "");
2796 else if (const_index && !compact_const_index)
2797 dw_addr = LLVMBuildAdd(ctx->builder, dw_addr,
2798 LLVMConstInt(ctx->ac.i32, const_index, false), "");
2799
2800 dw_addr = LLVMBuildAdd(ctx->builder, dw_addr,
2801 LLVMConstInt(ctx->ac.i32, param * 4, false), "");
2802
2803 if (const_index && compact_const_index)
2804 dw_addr = LLVMBuildAdd(ctx->builder, dw_addr,
2805 LLVMConstInt(ctx->ac.i32, const_index, false), "");
2806 return dw_addr;
2807 }
2808
2809 static LLVMValueRef
2810 load_tcs_input(struct ac_shader_abi *abi,
2811 LLVMValueRef vertex_index,
2812 LLVMValueRef indir_index,
2813 unsigned const_index,
2814 unsigned location,
2815 unsigned driver_location,
2816 unsigned component,
2817 unsigned num_components,
2818 bool is_patch,
2819 bool is_compact)
2820 {
2821 struct nir_to_llvm_context *ctx = nir_to_llvm_context_from_abi(abi);
2822 LLVMValueRef dw_addr, stride;
2823 LLVMValueRef value[4], result;
2824 unsigned param = shader_io_get_unique_index(location);
2825
2826 stride = unpack_param(&ctx->ac, ctx->tcs_in_layout, 13, 8);
2827 dw_addr = get_tcs_in_current_patch_offset(ctx);
2828 dw_addr = get_dw_address(ctx, dw_addr, param, const_index, is_compact, vertex_index, stride,
2829 indir_index);
2830
2831 for (unsigned i = 0; i < num_components + component; i++) {
2832 value[i] = ac_lds_load(&ctx->ac, dw_addr);
2833 dw_addr = LLVMBuildAdd(ctx->builder, dw_addr,
2834 ctx->ac.i32_1, "");
2835 }
2836 result = ac_build_varying_gather_values(&ctx->ac, value, num_components, component);
2837 return result;
2838 }
2839
2840 static LLVMValueRef
2841 load_tcs_output(struct nir_to_llvm_context *ctx,
2842 nir_intrinsic_instr *instr)
2843 {
2844 LLVMValueRef dw_addr;
2845 LLVMValueRef stride = NULL;
2846 LLVMValueRef value[4], result;
2847 LLVMValueRef vertex_index = NULL;
2848 LLVMValueRef indir_index = NULL;
2849 unsigned const_index = 0;
2850 unsigned param;
2851 const bool per_vertex = nir_is_per_vertex_io(instr->variables[0]->var, ctx->stage);
2852 const bool is_compact = instr->variables[0]->var->data.compact;
2853 param = shader_io_get_unique_index(instr->variables[0]->var->data.location);
2854 get_deref_offset(ctx->nir, instr->variables[0],
2855 false, NULL, per_vertex ? &vertex_index : NULL,
2856 &const_index, &indir_index);
2857
2858 if (!instr->variables[0]->var->data.patch) {
2859 stride = unpack_param(&ctx->ac, ctx->tcs_out_layout, 13, 8);
2860 dw_addr = get_tcs_out_current_patch_offset(ctx);
2861 } else {
2862 dw_addr = get_tcs_out_current_patch_data_offset(ctx);
2863 }
2864
2865 dw_addr = get_dw_address(ctx, dw_addr, param, const_index, is_compact, vertex_index, stride,
2866 indir_index);
2867
2868 unsigned comp = instr->variables[0]->var->data.location_frac;
2869 for (unsigned i = comp; i < instr->num_components + comp; i++) {
2870 value[i] = ac_lds_load(&ctx->ac, dw_addr);
2871 dw_addr = LLVMBuildAdd(ctx->builder, dw_addr,
2872 ctx->ac.i32_1, "");
2873 }
2874 result = ac_build_varying_gather_values(&ctx->ac, value, instr->num_components, comp);
2875 result = LLVMBuildBitCast(ctx->builder, result, get_def_type(ctx->nir, &instr->dest.ssa), "");
2876 return result;
2877 }
2878
2879 static void
2880 store_tcs_output(struct ac_shader_abi *abi,
2881 LLVMValueRef vertex_index,
2882 LLVMValueRef param_index,
2883 unsigned const_index,
2884 unsigned location,
2885 unsigned driver_location,
2886 LLVMValueRef src,
2887 unsigned component,
2888 bool is_patch,
2889 bool is_compact,
2890 unsigned writemask)
2891 {
2892 struct nir_to_llvm_context *ctx = nir_to_llvm_context_from_abi(abi);
2893 LLVMValueRef dw_addr;
2894 LLVMValueRef stride = NULL;
2895 LLVMValueRef buf_addr = NULL;
2896 unsigned param;
2897 bool store_lds = true;
2898
2899 if (is_patch) {
2900 if (!(ctx->tcs_patch_outputs_read & (1U << (location - VARYING_SLOT_PATCH0))))
2901 store_lds = false;
2902 } else {
2903 if (!(ctx->tcs_outputs_read & (1ULL << location)))
2904 store_lds = false;
2905 }
2906
2907 param = shader_io_get_unique_index(location);
2908 if (location == VARYING_SLOT_CLIP_DIST0 &&
2909 is_compact && const_index > 3) {
2910 const_index -= 3;
2911 param++;
2912 }
2913
2914 if (!is_patch) {
2915 stride = unpack_param(&ctx->ac, ctx->tcs_out_layout, 13, 8);
2916 dw_addr = get_tcs_out_current_patch_offset(ctx);
2917 } else {
2918 dw_addr = get_tcs_out_current_patch_data_offset(ctx);
2919 }
2920
2921 mark_tess_output(ctx, is_patch, param);
2922
2923 dw_addr = get_dw_address(ctx, dw_addr, param, const_index, is_compact, vertex_index, stride,
2924 param_index);
2925 buf_addr = get_tcs_tes_buffer_address_params(ctx, param, const_index, is_compact,
2926 vertex_index, param_index);
2927
2928 bool is_tess_factor = false;
2929 if (location == VARYING_SLOT_TESS_LEVEL_INNER ||
2930 location == VARYING_SLOT_TESS_LEVEL_OUTER)
2931 is_tess_factor = true;
2932
2933 unsigned base = is_compact ? const_index : 0;
2934 for (unsigned chan = 0; chan < 8; chan++) {
2935 if (!(writemask & (1 << chan)))
2936 continue;
2937 LLVMValueRef value = ac_llvm_extract_elem(&ctx->ac, src, chan - component);
2938
2939 if (store_lds || is_tess_factor)
2940 ac_lds_store(&ctx->ac, dw_addr, value);
2941
2942 if (!is_tess_factor && writemask != 0xF)
2943 ac_build_buffer_store_dword(&ctx->ac, ctx->hs_ring_tess_offchip, value, 1,
2944 buf_addr, ctx->oc_lds,
2945 4 * (base + chan), 1, 0, true, false);
2946
2947 dw_addr = LLVMBuildAdd(ctx->builder, dw_addr,
2948 ctx->ac.i32_1, "");
2949 }
2950
2951 if (writemask == 0xF) {
2952 ac_build_buffer_store_dword(&ctx->ac, ctx->hs_ring_tess_offchip, src, 4,
2953 buf_addr, ctx->oc_lds,
2954 (base * 4), 1, 0, true, false);
2955 }
2956 }
2957
2958 static LLVMValueRef
2959 load_tes_input(struct ac_shader_abi *abi,
2960 LLVMValueRef vertex_index,
2961 LLVMValueRef param_index,
2962 unsigned const_index,
2963 unsigned location,
2964 unsigned driver_location,
2965 unsigned component,
2966 unsigned num_components,
2967 bool is_patch,
2968 bool is_compact)
2969 {
2970 struct nir_to_llvm_context *ctx = nir_to_llvm_context_from_abi(abi);
2971 LLVMValueRef buf_addr;
2972 LLVMValueRef result;
2973 unsigned param = shader_io_get_unique_index(location);
2974
2975 if (location == VARYING_SLOT_CLIP_DIST0 && is_compact && const_index > 3) {
2976 const_index -= 3;
2977 param++;
2978 }
2979
2980 buf_addr = get_tcs_tes_buffer_address_params(ctx, param, const_index,
2981 is_compact, vertex_index, param_index);
2982
2983 LLVMValueRef comp_offset = LLVMConstInt(ctx->ac.i32, component * 4, false);
2984 buf_addr = LLVMBuildAdd(ctx->builder, buf_addr, comp_offset, "");
2985
2986 result = ac_build_buffer_load(&ctx->ac, ctx->hs_ring_tess_offchip, num_components, NULL,
2987 buf_addr, ctx->oc_lds, is_compact ? (4 * const_index) : 0, 1, 0, true, false);
2988 result = trim_vector(&ctx->ac, result, num_components);
2989 return result;
2990 }
2991
2992 static LLVMValueRef
2993 load_gs_input(struct ac_shader_abi *abi,
2994 unsigned location,
2995 unsigned driver_location,
2996 unsigned component,
2997 unsigned num_components,
2998 unsigned vertex_index,
2999 unsigned const_index,
3000 LLVMTypeRef type)
3001 {
3002 struct nir_to_llvm_context *ctx = nir_to_llvm_context_from_abi(abi);
3003 LLVMValueRef vtx_offset;
3004 LLVMValueRef args[9];
3005 unsigned param, vtx_offset_param;
3006 LLVMValueRef value[4], result;
3007
3008 vtx_offset_param = vertex_index;
3009 assert(vtx_offset_param < 6);
3010 vtx_offset = LLVMBuildMul(ctx->builder, ctx->gs_vtx_offset[vtx_offset_param],
3011 LLVMConstInt(ctx->ac.i32, 4, false), "");
3012
3013 param = shader_io_get_unique_index(location);
3014
3015 for (unsigned i = component; i < num_components + component; i++) {
3016 if (ctx->ac.chip_class >= GFX9) {
3017 LLVMValueRef dw_addr = ctx->gs_vtx_offset[vtx_offset_param];
3018 dw_addr = LLVMBuildAdd(ctx->ac.builder, dw_addr,
3019 LLVMConstInt(ctx->ac.i32, param * 4 + i + const_index, 0), "");
3020 value[i] = ac_lds_load(&ctx->ac, dw_addr);
3021 } else {
3022 args[0] = ctx->esgs_ring;
3023 args[1] = vtx_offset;
3024 args[2] = LLVMConstInt(ctx->ac.i32, (param * 4 + i + const_index) * 256, false);
3025 args[3] = ctx->ac.i32_0;
3026 args[4] = ctx->ac.i32_1; /* OFFEN */
3027 args[5] = ctx->ac.i32_0; /* IDXEN */
3028 args[6] = ctx->ac.i32_1; /* GLC */
3029 args[7] = ctx->ac.i32_0; /* SLC */
3030 args[8] = ctx->ac.i32_0; /* TFE */
3031
3032 value[i] = ac_build_intrinsic(&ctx->ac, "llvm.SI.buffer.load.dword.i32.i32",
3033 ctx->ac.i32, args, 9,
3034 AC_FUNC_ATTR_READONLY |
3035 AC_FUNC_ATTR_LEGACY);
3036 }
3037 }
3038 result = ac_build_varying_gather_values(&ctx->ac, value, num_components, component);
3039
3040 return result;
3041 }
3042
3043 static LLVMValueRef
3044 build_gep_for_deref(struct ac_nir_context *ctx,
3045 nir_deref_var *deref)
3046 {
3047 struct hash_entry *entry = _mesa_hash_table_search(ctx->vars, deref->var);
3048 assert(entry->data);
3049 LLVMValueRef val = entry->data;
3050 nir_deref *tail = deref->deref.child;
3051 while (tail != NULL) {
3052 LLVMValueRef offset;
3053 switch (tail->deref_type) {
3054 case nir_deref_type_array: {
3055 nir_deref_array *array = nir_deref_as_array(tail);
3056 offset = LLVMConstInt(ctx->ac.i32, array->base_offset, 0);
3057 if (array->deref_array_type ==
3058 nir_deref_array_type_indirect) {
3059 offset = LLVMBuildAdd(ctx->ac.builder, offset,
3060 get_src(ctx,
3061 array->indirect),
3062 "");
3063 }
3064 break;
3065 }
3066 case nir_deref_type_struct: {
3067 nir_deref_struct *deref_struct =
3068 nir_deref_as_struct(tail);
3069 offset = LLVMConstInt(ctx->ac.i32,
3070 deref_struct->index, 0);
3071 break;
3072 }
3073 default:
3074 unreachable("bad deref type");
3075 }
3076 val = ac_build_gep0(&ctx->ac, val, offset);
3077 tail = tail->child;
3078 }
3079 return val;
3080 }
3081
3082 static LLVMValueRef visit_load_var(struct ac_nir_context *ctx,
3083 nir_intrinsic_instr *instr)
3084 {
3085 LLVMValueRef values[8];
3086 int idx = instr->variables[0]->var->data.driver_location;
3087 int ve = instr->dest.ssa.num_components;
3088 unsigned comp = instr->variables[0]->var->data.location_frac;
3089 LLVMValueRef indir_index;
3090 LLVMValueRef ret;
3091 unsigned const_index;
3092 unsigned stride = instr->variables[0]->var->data.compact ? 1 : 4;
3093 bool vs_in = ctx->stage == MESA_SHADER_VERTEX &&
3094 instr->variables[0]->var->data.mode == nir_var_shader_in;
3095 get_deref_offset(ctx, instr->variables[0], vs_in, NULL, NULL,
3096 &const_index, &indir_index);
3097
3098 if (instr->dest.ssa.bit_size == 64)
3099 ve *= 2;
3100
3101 switch (instr->variables[0]->var->data.mode) {
3102 case nir_var_shader_in:
3103 if (ctx->stage == MESA_SHADER_TESS_CTRL ||
3104 ctx->stage == MESA_SHADER_TESS_EVAL) {
3105 LLVMValueRef result;
3106 LLVMValueRef vertex_index = NULL;
3107 LLVMValueRef indir_index = NULL;
3108 unsigned const_index = 0;
3109 unsigned location = instr->variables[0]->var->data.location;
3110 unsigned driver_location = instr->variables[0]->var->data.driver_location;
3111 const bool is_patch = instr->variables[0]->var->data.patch;
3112 const bool is_compact = instr->variables[0]->var->data.compact;
3113
3114 get_deref_offset(ctx, instr->variables[0],
3115 false, NULL, is_patch ? NULL : &vertex_index,
3116 &const_index, &indir_index);
3117
3118 result = ctx->abi->load_tess_inputs(ctx->abi, vertex_index, indir_index,
3119 const_index, location, driver_location,
3120 instr->variables[0]->var->data.location_frac,
3121 instr->num_components,
3122 is_patch, is_compact);
3123 return LLVMBuildBitCast(ctx->ac.builder, result, get_def_type(ctx, &instr->dest.ssa), "");
3124 }
3125
3126 if (ctx->stage == MESA_SHADER_GEOMETRY) {
3127 LLVMValueRef indir_index;
3128 unsigned const_index, vertex_index;
3129 get_deref_offset(ctx, instr->variables[0],
3130 false, &vertex_index, NULL,
3131 &const_index, &indir_index);
3132 return ctx->abi->load_inputs(ctx->abi, instr->variables[0]->var->data.location,
3133 instr->variables[0]->var->data.driver_location,
3134 instr->variables[0]->var->data.location_frac, ve,
3135 vertex_index, const_index,
3136 nir2llvmtype(ctx, instr->variables[0]->var->type));
3137 }
3138
3139 for (unsigned chan = comp; chan < ve + comp; chan++) {
3140 if (indir_index) {
3141 unsigned count = glsl_count_attribute_slots(
3142 instr->variables[0]->var->type,
3143 ctx->stage == MESA_SHADER_VERTEX);
3144 count -= chan / 4;
3145 LLVMValueRef tmp_vec = ac_build_gather_values_extended(
3146 &ctx->ac, ctx->abi->inputs + idx + chan, count,
3147 stride, false, true);
3148
3149 values[chan] = LLVMBuildExtractElement(ctx->ac.builder,
3150 tmp_vec,
3151 indir_index, "");
3152 } else
3153 values[chan] = ctx->abi->inputs[idx + chan + const_index * stride];
3154 }
3155 break;
3156 case nir_var_local:
3157 for (unsigned chan = 0; chan < ve; chan++) {
3158 if (indir_index) {
3159 unsigned count = glsl_count_attribute_slots(
3160 instr->variables[0]->var->type, false);
3161 count -= chan / 4;
3162 LLVMValueRef tmp_vec = ac_build_gather_values_extended(
3163 &ctx->ac, ctx->locals + idx + chan, count,
3164 stride, true, true);
3165
3166 values[chan] = LLVMBuildExtractElement(ctx->ac.builder,
3167 tmp_vec,
3168 indir_index, "");
3169 } else {
3170 values[chan] = LLVMBuildLoad(ctx->ac.builder, ctx->locals[idx + chan + const_index * stride], "");
3171 }
3172 }
3173 break;
3174 case nir_var_shared: {
3175 LLVMValueRef address = build_gep_for_deref(ctx,
3176 instr->variables[0]);
3177 LLVMValueRef val = LLVMBuildLoad(ctx->ac.builder, address, "");
3178 return LLVMBuildBitCast(ctx->ac.builder, val,
3179 get_def_type(ctx, &instr->dest.ssa),
3180 "");
3181 }
3182 case nir_var_shader_out:
3183 if (ctx->stage == MESA_SHADER_TESS_CTRL)
3184 return load_tcs_output(ctx->nctx, instr);
3185
3186 for (unsigned chan = comp; chan < ve + comp; chan++) {
3187 if (indir_index) {
3188 unsigned count = glsl_count_attribute_slots(
3189 instr->variables[0]->var->type, false);
3190 count -= chan / 4;
3191 LLVMValueRef tmp_vec = ac_build_gather_values_extended(
3192 &ctx->ac, ctx->outputs + idx + chan, count,
3193 stride, true, true);
3194
3195 values[chan] = LLVMBuildExtractElement(ctx->ac.builder,
3196 tmp_vec,
3197 indir_index, "");
3198 } else {
3199 values[chan] = LLVMBuildLoad(ctx->ac.builder,
3200 ctx->outputs[idx + chan + const_index * stride],
3201 "");
3202 }
3203 }
3204 break;
3205 default:
3206 unreachable("unhandle variable mode");
3207 }
3208 ret = ac_build_varying_gather_values(&ctx->ac, values, ve, comp);
3209 return LLVMBuildBitCast(ctx->ac.builder, ret, get_def_type(ctx, &instr->dest.ssa), "");
3210 }
3211
3212 static void
3213 visit_store_var(struct ac_nir_context *ctx,
3214 nir_intrinsic_instr *instr)
3215 {
3216 LLVMValueRef temp_ptr, value;
3217 int idx = instr->variables[0]->var->data.driver_location;
3218 unsigned comp = instr->variables[0]->var->data.location_frac;
3219 LLVMValueRef src = ac_to_float(&ctx->ac, get_src(ctx, instr->src[0]));
3220 int writemask = instr->const_index[0] << comp;
3221 LLVMValueRef indir_index;
3222 unsigned const_index;
3223 get_deref_offset(ctx, instr->variables[0], false,
3224 NULL, NULL, &const_index, &indir_index);
3225
3226 if (get_elem_bits(&ctx->ac, LLVMTypeOf(src)) == 64) {
3227 int old_writemask = writemask;
3228
3229 src = LLVMBuildBitCast(ctx->ac.builder, src,
3230 LLVMVectorType(ctx->ac.f32, ac_get_llvm_num_components(src) * 2),
3231 "");
3232
3233 writemask = 0;
3234 for (unsigned chan = 0; chan < 4; chan++) {
3235 if (old_writemask & (1 << chan))
3236 writemask |= 3u << (2 * chan);
3237 }
3238 }
3239
3240 switch (instr->variables[0]->var->data.mode) {
3241 case nir_var_shader_out:
3242
3243 if (ctx->stage == MESA_SHADER_TESS_CTRL) {
3244 LLVMValueRef vertex_index = NULL;
3245 LLVMValueRef indir_index = NULL;
3246 unsigned const_index = 0;
3247 const unsigned location = instr->variables[0]->var->data.location;
3248 const unsigned driver_location = instr->variables[0]->var->data.driver_location;
3249 const unsigned comp = instr->variables[0]->var->data.location_frac;
3250 const bool is_patch = instr->variables[0]->var->data.patch;
3251 const bool is_compact = instr->variables[0]->var->data.compact;
3252
3253 get_deref_offset(ctx, instr->variables[0],
3254 false, NULL, is_patch ? NULL : &vertex_index,
3255 &const_index, &indir_index);
3256
3257 ctx->abi->store_tcs_outputs(ctx->abi, vertex_index, indir_index,
3258 const_index, location, driver_location,
3259 src, comp, is_patch, is_compact, writemask);
3260 return;
3261 }
3262
3263 for (unsigned chan = 0; chan < 8; chan++) {
3264 int stride = 4;
3265 if (!(writemask & (1 << chan)))
3266 continue;
3267
3268 value = ac_llvm_extract_elem(&ctx->ac, src, chan - comp);
3269
3270 if (instr->variables[0]->var->data.compact)
3271 stride = 1;
3272 if (indir_index) {
3273 unsigned count = glsl_count_attribute_slots(
3274 instr->variables[0]->var->type, false);
3275 count -= chan / 4;
3276 LLVMValueRef tmp_vec = ac_build_gather_values_extended(
3277 &ctx->ac, ctx->outputs + idx + chan, count,
3278 stride, true, true);
3279
3280 tmp_vec = LLVMBuildInsertElement(ctx->ac.builder, tmp_vec,
3281 value, indir_index, "");
3282 build_store_values_extended(&ctx->ac, ctx->outputs + idx + chan,
3283 count, stride, tmp_vec);
3284
3285 } else {
3286 temp_ptr = ctx->outputs[idx + chan + const_index * stride];
3287
3288 LLVMBuildStore(ctx->ac.builder, value, temp_ptr);
3289 }
3290 }
3291 break;
3292 case nir_var_local:
3293 for (unsigned chan = 0; chan < 8; chan++) {
3294 if (!(writemask & (1 << chan)))
3295 continue;
3296
3297 value = ac_llvm_extract_elem(&ctx->ac, src, chan);
3298 if (indir_index) {
3299 unsigned count = glsl_count_attribute_slots(
3300 instr->variables[0]->var->type, false);
3301 count -= chan / 4;
3302 LLVMValueRef tmp_vec = ac_build_gather_values_extended(
3303 &ctx->ac, ctx->locals + idx + chan, count,
3304 4, true, true);
3305
3306 tmp_vec = LLVMBuildInsertElement(ctx->ac.builder, tmp_vec,
3307 value, indir_index, "");
3308 build_store_values_extended(&ctx->ac, ctx->locals + idx + chan,
3309 count, 4, tmp_vec);
3310 } else {
3311 temp_ptr = ctx->locals[idx + chan + const_index * 4];
3312
3313 LLVMBuildStore(ctx->ac.builder, value, temp_ptr);
3314 }
3315 }
3316 break;
3317 case nir_var_shared: {
3318 int writemask = instr->const_index[0];
3319 LLVMValueRef address = build_gep_for_deref(ctx,
3320 instr->variables[0]);
3321 LLVMValueRef val = get_src(ctx, instr->src[0]);
3322 unsigned components =
3323 glsl_get_vector_elements(
3324 nir_deref_tail(&instr->variables[0]->deref)->type);
3325 if (writemask == (1 << components) - 1) {
3326 val = LLVMBuildBitCast(
3327 ctx->ac.builder, val,
3328 LLVMGetElementType(LLVMTypeOf(address)), "");
3329 LLVMBuildStore(ctx->ac.builder, val, address);
3330 } else {
3331 for (unsigned chan = 0; chan < 4; chan++) {
3332 if (!(writemask & (1 << chan)))
3333 continue;
3334 LLVMValueRef ptr =
3335 LLVMBuildStructGEP(ctx->ac.builder,
3336 address, chan, "");
3337 LLVMValueRef src = ac_llvm_extract_elem(&ctx->ac, val,
3338 chan);
3339 src = LLVMBuildBitCast(
3340 ctx->ac.builder, src,
3341 LLVMGetElementType(LLVMTypeOf(ptr)), "");
3342 LLVMBuildStore(ctx->ac.builder, src, ptr);
3343 }
3344 }
3345 break;
3346 }
3347 default:
3348 break;
3349 }
3350 }
3351
3352 static int image_type_to_components_count(enum glsl_sampler_dim dim, bool array)
3353 {
3354 switch (dim) {
3355 case GLSL_SAMPLER_DIM_BUF:
3356 return 1;
3357 case GLSL_SAMPLER_DIM_1D:
3358 return array ? 2 : 1;
3359 case GLSL_SAMPLER_DIM_2D:
3360 return array ? 3 : 2;
3361 case GLSL_SAMPLER_DIM_MS:
3362 return array ? 4 : 3;
3363 case GLSL_SAMPLER_DIM_3D:
3364 case GLSL_SAMPLER_DIM_CUBE:
3365 return 3;
3366 case GLSL_SAMPLER_DIM_RECT:
3367 case GLSL_SAMPLER_DIM_SUBPASS:
3368 return 2;
3369 case GLSL_SAMPLER_DIM_SUBPASS_MS:
3370 return 3;
3371 default:
3372 break;
3373 }
3374 return 0;
3375 }
3376
3377
3378
3379 /* Adjust the sample index according to FMASK.
3380 *
3381 * For uncompressed MSAA surfaces, FMASK should return 0x76543210,
3382 * which is the identity mapping. Each nibble says which physical sample
3383 * should be fetched to get that sample.
3384 *
3385 * For example, 0x11111100 means there are only 2 samples stored and
3386 * the second sample covers 3/4 of the pixel. When reading samples 0
3387 * and 1, return physical sample 0 (determined by the first two 0s
3388 * in FMASK), otherwise return physical sample 1.
3389 *
3390 * The sample index should be adjusted as follows:
3391 * sample_index = (fmask >> (sample_index * 4)) & 0xF;
3392 */
3393 static LLVMValueRef adjust_sample_index_using_fmask(struct ac_llvm_context *ctx,
3394 LLVMValueRef coord_x, LLVMValueRef coord_y,
3395 LLVMValueRef coord_z,
3396 LLVMValueRef sample_index,
3397 LLVMValueRef fmask_desc_ptr)
3398 {
3399 LLVMValueRef fmask_load_address[4];
3400 LLVMValueRef res;
3401
3402 fmask_load_address[0] = coord_x;
3403 fmask_load_address[1] = coord_y;
3404 if (coord_z) {
3405 fmask_load_address[2] = coord_z;
3406 fmask_load_address[3] = LLVMGetUndef(ctx->i32);
3407 }
3408
3409 struct ac_image_args args = {0};
3410
3411 args.opcode = ac_image_load;
3412 args.da = coord_z ? true : false;
3413 args.resource = fmask_desc_ptr;
3414 args.dmask = 0xf;
3415 args.addr = ac_build_gather_values(ctx, fmask_load_address, coord_z ? 4 : 2);
3416
3417 res = ac_build_image_opcode(ctx, &args);
3418
3419 res = ac_to_integer(ctx, res);
3420 LLVMValueRef four = LLVMConstInt(ctx->i32, 4, false);
3421 LLVMValueRef F = LLVMConstInt(ctx->i32, 0xf, false);
3422
3423 LLVMValueRef fmask = LLVMBuildExtractElement(ctx->builder,
3424 res,
3425 ctx->i32_0, "");
3426
3427 LLVMValueRef sample_index4 =
3428 LLVMBuildMul(ctx->builder, sample_index, four, "");
3429 LLVMValueRef shifted_fmask =
3430 LLVMBuildLShr(ctx->builder, fmask, sample_index4, "");
3431 LLVMValueRef final_sample =
3432 LLVMBuildAnd(ctx->builder, shifted_fmask, F, "");
3433
3434 /* Don't rewrite the sample index if WORD1.DATA_FORMAT of the FMASK
3435 * resource descriptor is 0 (invalid),
3436 */
3437 LLVMValueRef fmask_desc =
3438 LLVMBuildBitCast(ctx->builder, fmask_desc_ptr,
3439 ctx->v8i32, "");
3440
3441 LLVMValueRef fmask_word1 =
3442 LLVMBuildExtractElement(ctx->builder, fmask_desc,
3443 ctx->i32_1, "");
3444
3445 LLVMValueRef word1_is_nonzero =
3446 LLVMBuildICmp(ctx->builder, LLVMIntNE,
3447 fmask_word1, ctx->i32_0, "");
3448
3449 /* Replace the MSAA sample index. */
3450 sample_index =
3451 LLVMBuildSelect(ctx->builder, word1_is_nonzero,
3452 final_sample, sample_index, "");
3453 return sample_index;
3454 }
3455
3456 static LLVMValueRef get_image_coords(struct ac_nir_context *ctx,
3457 const nir_intrinsic_instr *instr)
3458 {
3459 const struct glsl_type *type = instr->variables[0]->var->type;
3460 if(instr->variables[0]->deref.child)
3461 type = instr->variables[0]->deref.child->type;
3462
3463 LLVMValueRef src0 = get_src(ctx, instr->src[0]);
3464 LLVMValueRef coords[4];
3465 LLVMValueRef masks[] = {
3466 LLVMConstInt(ctx->ac.i32, 0, false), LLVMConstInt(ctx->ac.i32, 1, false),
3467 LLVMConstInt(ctx->ac.i32, 2, false), LLVMConstInt(ctx->ac.i32, 3, false),
3468 };
3469 LLVMValueRef res;
3470 LLVMValueRef sample_index = ac_llvm_extract_elem(&ctx->ac, get_src(ctx, instr->src[1]), 0);
3471
3472 int count;
3473 enum glsl_sampler_dim dim = glsl_get_sampler_dim(type);
3474 bool is_array = glsl_sampler_type_is_array(type);
3475 bool add_frag_pos = (dim == GLSL_SAMPLER_DIM_SUBPASS ||
3476 dim == GLSL_SAMPLER_DIM_SUBPASS_MS);
3477 bool is_ms = (dim == GLSL_SAMPLER_DIM_MS ||
3478 dim == GLSL_SAMPLER_DIM_SUBPASS_MS);
3479 bool gfx9_1d = ctx->ac.chip_class >= GFX9 && dim == GLSL_SAMPLER_DIM_1D;
3480 count = image_type_to_components_count(dim, is_array);
3481
3482 if (is_ms) {
3483 LLVMValueRef fmask_load_address[3];
3484 int chan;
3485
3486 fmask_load_address[0] = LLVMBuildExtractElement(ctx->ac.builder, src0, masks[0], "");
3487 fmask_load_address[1] = LLVMBuildExtractElement(ctx->ac.builder, src0, masks[1], "");
3488 if (is_array)
3489 fmask_load_address[2] = LLVMBuildExtractElement(ctx->ac.builder, src0, masks[2], "");
3490 else
3491 fmask_load_address[2] = NULL;
3492 if (add_frag_pos) {
3493 for (chan = 0; chan < 2; ++chan)
3494 fmask_load_address[chan] =
3495 LLVMBuildAdd(ctx->ac.builder, fmask_load_address[chan],
3496 LLVMBuildFPToUI(ctx->ac.builder, ctx->abi->frag_pos[chan],
3497 ctx->ac.i32, ""), "");
3498 fmask_load_address[2] = ac_to_integer(&ctx->ac, ctx->abi->inputs[radeon_llvm_reg_index_soa(VARYING_SLOT_LAYER, 0)]);
3499 }
3500 sample_index = adjust_sample_index_using_fmask(&ctx->ac,
3501 fmask_load_address[0],
3502 fmask_load_address[1],
3503 fmask_load_address[2],
3504 sample_index,
3505 get_sampler_desc(ctx, instr->variables[0], AC_DESC_FMASK, NULL, true, false));
3506 }
3507 if (count == 1 && !gfx9_1d) {
3508 if (instr->src[0].ssa->num_components)
3509 res = LLVMBuildExtractElement(ctx->ac.builder, src0, masks[0], "");
3510 else
3511 res = src0;
3512 } else {
3513 int chan;
3514 if (is_ms)
3515 count--;
3516 for (chan = 0; chan < count; ++chan) {
3517 coords[chan] = ac_llvm_extract_elem(&ctx->ac, src0, chan);
3518 }
3519 if (add_frag_pos) {
3520 for (chan = 0; chan < 2; ++chan)
3521 coords[chan] = LLVMBuildAdd(ctx->ac.builder, coords[chan], LLVMBuildFPToUI(ctx->ac.builder, ctx->abi->frag_pos[chan],
3522 ctx->ac.i32, ""), "");
3523 coords[2] = ac_to_integer(&ctx->ac, ctx->abi->inputs[radeon_llvm_reg_index_soa(VARYING_SLOT_LAYER, 0)]);
3524 count++;
3525 }
3526
3527 if (gfx9_1d) {
3528 if (is_array) {
3529 coords[2] = coords[1];
3530 coords[1] = ctx->ac.i32_0;
3531 } else
3532 coords[1] = ctx->ac.i32_0;
3533 count++;
3534 }
3535
3536 if (is_ms) {
3537 coords[count] = sample_index;
3538 count++;
3539 }
3540
3541 if (count == 3) {
3542 coords[3] = LLVMGetUndef(ctx->ac.i32);
3543 count = 4;
3544 }
3545 res = ac_build_gather_values(&ctx->ac, coords, count);
3546 }
3547 return res;
3548 }
3549
3550 static LLVMValueRef visit_image_load(struct ac_nir_context *ctx,
3551 const nir_intrinsic_instr *instr)
3552 {
3553 LLVMValueRef params[7];
3554 LLVMValueRef res;
3555 char intrinsic_name[64];
3556 const nir_variable *var = instr->variables[0]->var;
3557 const struct glsl_type *type = var->type;
3558
3559 if(instr->variables[0]->deref.child)
3560 type = instr->variables[0]->deref.child->type;
3561
3562 type = glsl_without_array(type);
3563 if (glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_BUF) {
3564 params[0] = get_sampler_desc(ctx, instr->variables[0], AC_DESC_BUFFER, NULL, true, false);
3565 params[1] = LLVMBuildExtractElement(ctx->ac.builder, get_src(ctx, instr->src[0]),
3566 ctx->ac.i32_0, ""); /* vindex */
3567 params[2] = ctx->ac.i32_0; /* voffset */
3568 params[3] = ctx->ac.i1false; /* glc */
3569 params[4] = ctx->ac.i1false; /* slc */
3570 res = ac_build_intrinsic(&ctx->ac, "llvm.amdgcn.buffer.load.format.v4f32", ctx->ac.v4f32,
3571 params, 5, 0);
3572
3573 res = trim_vector(&ctx->ac, res, instr->dest.ssa.num_components);
3574 res = ac_to_integer(&ctx->ac, res);
3575 } else {
3576 bool is_da = glsl_sampler_type_is_array(type) ||
3577 glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_CUBE ||
3578 glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_SUBPASS ||
3579 glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_SUBPASS_MS;
3580 LLVMValueRef da = is_da ? ctx->ac.i1true : ctx->ac.i1false;
3581 LLVMValueRef glc = ctx->ac.i1false;
3582 LLVMValueRef slc = ctx->ac.i1false;
3583
3584 params[0] = get_image_coords(ctx, instr);
3585 params[1] = get_sampler_desc(ctx, instr->variables[0], AC_DESC_IMAGE, NULL, true, false);
3586 params[2] = LLVMConstInt(ctx->ac.i32, 15, false); /* dmask */
3587 if (HAVE_LLVM <= 0x0309) {
3588 params[3] = ctx->ac.i1false; /* r128 */
3589 params[4] = da;
3590 params[5] = glc;
3591 params[6] = slc;
3592 } else {
3593 LLVMValueRef lwe = ctx->ac.i1false;
3594 params[3] = glc;
3595 params[4] = slc;
3596 params[5] = lwe;
3597 params[6] = da;
3598 }
3599
3600 ac_get_image_intr_name("llvm.amdgcn.image.load",
3601 ctx->ac.v4f32, /* vdata */
3602 LLVMTypeOf(params[0]), /* coords */
3603 LLVMTypeOf(params[1]), /* rsrc */
3604 intrinsic_name, sizeof(intrinsic_name));
3605
3606 res = ac_build_intrinsic(&ctx->ac, intrinsic_name, ctx->ac.v4f32,
3607 params, 7, AC_FUNC_ATTR_READONLY);
3608 }
3609 return ac_to_integer(&ctx->ac, res);
3610 }
3611
3612 static void visit_image_store(struct ac_nir_context *ctx,
3613 nir_intrinsic_instr *instr)
3614 {
3615 LLVMValueRef params[8];
3616 char intrinsic_name[64];
3617 const nir_variable *var = instr->variables[0]->var;
3618 const struct glsl_type *type = glsl_without_array(var->type);
3619 LLVMValueRef glc = ctx->ac.i1false;
3620 bool force_glc = ctx->ac.chip_class == SI;
3621 if (force_glc)
3622 glc = ctx->ac.i1true;
3623
3624 if (glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_BUF) {
3625 params[0] = ac_to_float(&ctx->ac, get_src(ctx, instr->src[2])); /* data */
3626 params[1] = get_sampler_desc(ctx, instr->variables[0], AC_DESC_BUFFER, NULL, true, true);
3627 params[2] = LLVMBuildExtractElement(ctx->ac.builder, get_src(ctx, instr->src[0]),
3628 ctx->ac.i32_0, ""); /* vindex */
3629 params[3] = ctx->ac.i32_0; /* voffset */
3630 params[4] = glc; /* glc */
3631 params[5] = ctx->ac.i1false; /* slc */
3632 ac_build_intrinsic(&ctx->ac, "llvm.amdgcn.buffer.store.format.v4f32", ctx->ac.voidt,
3633 params, 6, 0);
3634 } else {
3635 bool is_da = glsl_sampler_type_is_array(type) ||
3636 glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_CUBE;
3637 LLVMValueRef da = is_da ? ctx->ac.i1true : ctx->ac.i1false;
3638 LLVMValueRef slc = ctx->ac.i1false;
3639
3640 params[0] = ac_to_float(&ctx->ac, get_src(ctx, instr->src[2]));
3641 params[1] = get_image_coords(ctx, instr); /* coords */
3642 params[2] = get_sampler_desc(ctx, instr->variables[0], AC_DESC_IMAGE, NULL, true, true);
3643 params[3] = LLVMConstInt(ctx->ac.i32, 15, false); /* dmask */
3644 if (HAVE_LLVM <= 0x0309) {
3645 params[4] = ctx->ac.i1false; /* r128 */
3646 params[5] = da;
3647 params[6] = glc;
3648 params[7] = slc;
3649 } else {
3650 LLVMValueRef lwe = ctx->ac.i1false;
3651 params[4] = glc;
3652 params[5] = slc;
3653 params[6] = lwe;
3654 params[7] = da;
3655 }
3656
3657 ac_get_image_intr_name("llvm.amdgcn.image.store",
3658 LLVMTypeOf(params[0]), /* vdata */
3659 LLVMTypeOf(params[1]), /* coords */
3660 LLVMTypeOf(params[2]), /* rsrc */
3661 intrinsic_name, sizeof(intrinsic_name));
3662
3663 ac_build_intrinsic(&ctx->ac, intrinsic_name, ctx->ac.voidt,
3664 params, 8, 0);
3665 }
3666
3667 }
3668
3669 static LLVMValueRef visit_image_atomic(struct ac_nir_context *ctx,
3670 const nir_intrinsic_instr *instr)
3671 {
3672 LLVMValueRef params[7];
3673 int param_count = 0;
3674 const nir_variable *var = instr->variables[0]->var;
3675
3676 const char *atomic_name;
3677 char intrinsic_name[41];
3678 const struct glsl_type *type = glsl_without_array(var->type);
3679 MAYBE_UNUSED int length;
3680
3681 bool is_unsigned = glsl_get_sampler_result_type(type) == GLSL_TYPE_UINT;
3682
3683 switch (instr->intrinsic) {
3684 case nir_intrinsic_image_atomic_add:
3685 atomic_name = "add";
3686 break;
3687 case nir_intrinsic_image_atomic_min:
3688 atomic_name = is_unsigned ? "umin" : "smin";
3689 break;
3690 case nir_intrinsic_image_atomic_max:
3691 atomic_name = is_unsigned ? "umax" : "smax";
3692 break;
3693 case nir_intrinsic_image_atomic_and:
3694 atomic_name = "and";
3695 break;
3696 case nir_intrinsic_image_atomic_or:
3697 atomic_name = "or";
3698 break;
3699 case nir_intrinsic_image_atomic_xor:
3700 atomic_name = "xor";
3701 break;
3702 case nir_intrinsic_image_atomic_exchange:
3703 atomic_name = "swap";
3704 break;
3705 case nir_intrinsic_image_atomic_comp_swap:
3706 atomic_name = "cmpswap";
3707 break;
3708 default:
3709 abort();
3710 }
3711
3712 if (instr->intrinsic == nir_intrinsic_image_atomic_comp_swap)
3713 params[param_count++] = get_src(ctx, instr->src[3]);
3714 params[param_count++] = get_src(ctx, instr->src[2]);
3715
3716 if (glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_BUF) {
3717 params[param_count++] = get_sampler_desc(ctx, instr->variables[0], AC_DESC_BUFFER,
3718 NULL, true, true);
3719 params[param_count++] = LLVMBuildExtractElement(ctx->ac.builder, get_src(ctx, instr->src[0]),
3720 ctx->ac.i32_0, ""); /* vindex */
3721 params[param_count++] = ctx->ac.i32_0; /* voffset */
3722 params[param_count++] = ctx->ac.i1false; /* slc */
3723
3724 length = snprintf(intrinsic_name, sizeof(intrinsic_name),
3725 "llvm.amdgcn.buffer.atomic.%s", atomic_name);
3726 } else {
3727 char coords_type[8];
3728
3729 bool da = glsl_sampler_type_is_array(type) ||
3730 glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_CUBE;
3731
3732 LLVMValueRef coords = params[param_count++] = get_image_coords(ctx, instr);
3733 params[param_count++] = get_sampler_desc(ctx, instr->variables[0], AC_DESC_IMAGE,
3734 NULL, true, true);
3735 params[param_count++] = ctx->ac.i1false; /* r128 */
3736 params[param_count++] = da ? ctx->ac.i1true : ctx->ac.i1false; /* da */
3737 params[param_count++] = ctx->ac.i1false; /* slc */
3738
3739 build_int_type_name(LLVMTypeOf(coords),
3740 coords_type, sizeof(coords_type));
3741
3742 length = snprintf(intrinsic_name, sizeof(intrinsic_name),
3743 "llvm.amdgcn.image.atomic.%s.%s", atomic_name, coords_type);
3744 }
3745
3746 assert(length < sizeof(intrinsic_name));
3747 return ac_build_intrinsic(&ctx->ac, intrinsic_name, ctx->ac.i32, params, param_count, 0);
3748 }
3749
3750 static LLVMValueRef visit_image_size(struct ac_nir_context *ctx,
3751 const nir_intrinsic_instr *instr)
3752 {
3753 LLVMValueRef res;
3754 const nir_variable *var = instr->variables[0]->var;
3755 const struct glsl_type *type = instr->variables[0]->var->type;
3756 bool da = glsl_sampler_type_is_array(var->type) ||
3757 glsl_get_sampler_dim(var->type) == GLSL_SAMPLER_DIM_CUBE;
3758 if(instr->variables[0]->deref.child)
3759 type = instr->variables[0]->deref.child->type;
3760
3761 if (glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_BUF)
3762 return get_buffer_size(ctx,
3763 get_sampler_desc(ctx, instr->variables[0],
3764 AC_DESC_BUFFER, NULL, true, false), true);
3765
3766 struct ac_image_args args = { 0 };
3767
3768 args.da = da;
3769 args.dmask = 0xf;
3770 args.resource = get_sampler_desc(ctx, instr->variables[0], AC_DESC_IMAGE, NULL, true, false);
3771 args.opcode = ac_image_get_resinfo;
3772 args.addr = ctx->ac.i32_0;
3773
3774 res = ac_build_image_opcode(&ctx->ac, &args);
3775
3776 LLVMValueRef two = LLVMConstInt(ctx->ac.i32, 2, false);
3777
3778 if (glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_CUBE &&
3779 glsl_sampler_type_is_array(type)) {
3780 LLVMValueRef six = LLVMConstInt(ctx->ac.i32, 6, false);
3781 LLVMValueRef z = LLVMBuildExtractElement(ctx->ac.builder, res, two, "");
3782 z = LLVMBuildSDiv(ctx->ac.builder, z, six, "");
3783 res = LLVMBuildInsertElement(ctx->ac.builder, res, z, two, "");
3784 }
3785 if (ctx->ac.chip_class >= GFX9 &&
3786 glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_1D &&
3787 glsl_sampler_type_is_array(type)) {
3788 LLVMValueRef layers = LLVMBuildExtractElement(ctx->ac.builder, res, two, "");
3789 res = LLVMBuildInsertElement(ctx->ac.builder, res, layers,
3790 ctx->ac.i32_1, "");
3791
3792 }
3793 return res;
3794 }
3795
3796 #define NOOP_WAITCNT 0xf7f
3797 #define LGKM_CNT 0x07f
3798 #define VM_CNT 0xf70
3799
3800 static void emit_membar(struct nir_to_llvm_context *ctx,
3801 const nir_intrinsic_instr *instr)
3802 {
3803 unsigned waitcnt = NOOP_WAITCNT;
3804
3805 switch (instr->intrinsic) {
3806 case nir_intrinsic_memory_barrier:
3807 case nir_intrinsic_group_memory_barrier:
3808 waitcnt &= VM_CNT & LGKM_CNT;
3809 break;
3810 case nir_intrinsic_memory_barrier_atomic_counter:
3811 case nir_intrinsic_memory_barrier_buffer:
3812 case nir_intrinsic_memory_barrier_image:
3813 waitcnt &= VM_CNT;
3814 break;
3815 case nir_intrinsic_memory_barrier_shared:
3816 waitcnt &= LGKM_CNT;
3817 break;
3818 default:
3819 break;
3820 }
3821 if (waitcnt != NOOP_WAITCNT)
3822 ac_build_waitcnt(&ctx->ac, waitcnt);
3823 }
3824
3825 static void emit_barrier(struct nir_to_llvm_context *ctx)
3826 {
3827 /* SI only (thanks to a hw bug workaround):
3828 * The real barrier instruction isn’t needed, because an entire patch
3829 * always fits into a single wave.
3830 */
3831 if (ctx->options->chip_class == SI &&
3832 ctx->stage == MESA_SHADER_TESS_CTRL) {
3833 ac_build_waitcnt(&ctx->ac, LGKM_CNT & VM_CNT);
3834 return;
3835 }
3836 ac_build_intrinsic(&ctx->ac, "llvm.amdgcn.s.barrier",
3837 ctx->ac.voidt, NULL, 0, AC_FUNC_ATTR_CONVERGENT);
3838 }
3839
3840 static void emit_discard_if(struct ac_nir_context *ctx,
3841 const nir_intrinsic_instr *instr)
3842 {
3843 LLVMValueRef cond;
3844
3845 cond = LLVMBuildICmp(ctx->ac.builder, LLVMIntEQ,
3846 get_src(ctx, instr->src[0]),
3847 ctx->ac.i32_0, "");
3848 ac_build_kill_if_false(&ctx->ac, cond);
3849 }
3850
3851 static LLVMValueRef
3852 visit_load_local_invocation_index(struct nir_to_llvm_context *ctx)
3853 {
3854 LLVMValueRef result;
3855 LLVMValueRef thread_id = ac_get_thread_id(&ctx->ac);
3856 result = LLVMBuildAnd(ctx->builder, ctx->tg_size,
3857 LLVMConstInt(ctx->ac.i32, 0xfc0, false), "");
3858
3859 return LLVMBuildAdd(ctx->builder, result, thread_id, "");
3860 }
3861
3862 static LLVMValueRef visit_var_atomic(struct nir_to_llvm_context *ctx,
3863 const nir_intrinsic_instr *instr)
3864 {
3865 LLVMValueRef ptr, result;
3866 LLVMValueRef src = get_src(ctx->nir, instr->src[0]);
3867 ptr = build_gep_for_deref(ctx->nir, instr->variables[0]);
3868
3869 if (instr->intrinsic == nir_intrinsic_var_atomic_comp_swap) {
3870 LLVMValueRef src1 = get_src(ctx->nir, instr->src[1]);
3871 result = LLVMBuildAtomicCmpXchg(ctx->builder,
3872 ptr, src, src1,
3873 LLVMAtomicOrderingSequentiallyConsistent,
3874 LLVMAtomicOrderingSequentiallyConsistent,
3875 false);
3876 } else {
3877 LLVMAtomicRMWBinOp op;
3878 switch (instr->intrinsic) {
3879 case nir_intrinsic_var_atomic_add:
3880 op = LLVMAtomicRMWBinOpAdd;
3881 break;
3882 case nir_intrinsic_var_atomic_umin:
3883 op = LLVMAtomicRMWBinOpUMin;
3884 break;
3885 case nir_intrinsic_var_atomic_umax:
3886 op = LLVMAtomicRMWBinOpUMax;
3887 break;
3888 case nir_intrinsic_var_atomic_imin:
3889 op = LLVMAtomicRMWBinOpMin;
3890 break;
3891 case nir_intrinsic_var_atomic_imax:
3892 op = LLVMAtomicRMWBinOpMax;
3893 break;
3894 case nir_intrinsic_var_atomic_and:
3895 op = LLVMAtomicRMWBinOpAnd;
3896 break;
3897 case nir_intrinsic_var_atomic_or:
3898 op = LLVMAtomicRMWBinOpOr;
3899 break;
3900 case nir_intrinsic_var_atomic_xor:
3901 op = LLVMAtomicRMWBinOpXor;
3902 break;
3903 case nir_intrinsic_var_atomic_exchange:
3904 op = LLVMAtomicRMWBinOpXchg;
3905 break;
3906 default:
3907 return NULL;
3908 }
3909
3910 result = LLVMBuildAtomicRMW(ctx->builder, op, ptr, ac_to_integer(&ctx->ac, src),
3911 LLVMAtomicOrderingSequentiallyConsistent,
3912 false);
3913 }
3914 return result;
3915 }
3916
3917 #define INTERP_CENTER 0
3918 #define INTERP_CENTROID 1
3919 #define INTERP_SAMPLE 2
3920
3921 static LLVMValueRef lookup_interp_param(struct nir_to_llvm_context *ctx,
3922 enum glsl_interp_mode interp, unsigned location)
3923 {
3924 switch (interp) {
3925 case INTERP_MODE_FLAT:
3926 default:
3927 return NULL;
3928 case INTERP_MODE_SMOOTH:
3929 case INTERP_MODE_NONE:
3930 if (location == INTERP_CENTER)
3931 return ctx->persp_center;
3932 else if (location == INTERP_CENTROID)
3933 return ctx->persp_centroid;
3934 else if (location == INTERP_SAMPLE)
3935 return ctx->persp_sample;
3936 break;
3937 case INTERP_MODE_NOPERSPECTIVE:
3938 if (location == INTERP_CENTER)
3939 return ctx->linear_center;
3940 else if (location == INTERP_CENTROID)
3941 return ctx->linear_centroid;
3942 else if (location == INTERP_SAMPLE)
3943 return ctx->linear_sample;
3944 break;
3945 }
3946 return NULL;
3947 }
3948
3949 static LLVMValueRef load_sample_position(struct nir_to_llvm_context *ctx,
3950 LLVMValueRef sample_id)
3951 {
3952 LLVMValueRef result;
3953 LLVMValueRef ptr = ac_build_gep0(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->ac.i32, RING_PS_SAMPLE_POSITIONS, false));
3954
3955 ptr = LLVMBuildBitCast(ctx->builder, ptr,
3956 const_array(ctx->ac.v2f32, 64), "");
3957
3958 sample_id = LLVMBuildAdd(ctx->builder, sample_id, ctx->sample_pos_offset, "");
3959 result = ac_build_load_invariant(&ctx->ac, ptr, sample_id);
3960
3961 return result;
3962 }
3963
3964 static LLVMValueRef load_sample_pos(struct ac_nir_context *ctx)
3965 {
3966 LLVMValueRef values[2];
3967
3968 values[0] = emit_ffract(&ctx->ac, ctx->abi->frag_pos[0]);
3969 values[1] = emit_ffract(&ctx->ac, ctx->abi->frag_pos[1]);
3970 return ac_build_gather_values(&ctx->ac, values, 2);
3971 }
3972
3973 static LLVMValueRef visit_interp(struct nir_to_llvm_context *ctx,
3974 const nir_intrinsic_instr *instr)
3975 {
3976 LLVMValueRef result[4];
3977 LLVMValueRef interp_param, attr_number;
3978 unsigned location;
3979 unsigned chan;
3980 LLVMValueRef src_c0 = NULL;
3981 LLVMValueRef src_c1 = NULL;
3982 LLVMValueRef src0 = NULL;
3983 int input_index = instr->variables[0]->var->data.location - VARYING_SLOT_VAR0;
3984 switch (instr->intrinsic) {
3985 case nir_intrinsic_interp_var_at_centroid:
3986 location = INTERP_CENTROID;
3987 break;
3988 case nir_intrinsic_interp_var_at_sample:
3989 case nir_intrinsic_interp_var_at_offset:
3990 location = INTERP_CENTER;
3991 src0 = get_src(ctx->nir, instr->src[0]);
3992 break;
3993 default:
3994 break;
3995 }
3996
3997 if (instr->intrinsic == nir_intrinsic_interp_var_at_offset) {
3998 src_c0 = ac_to_float(&ctx->ac, LLVMBuildExtractElement(ctx->builder, src0, ctx->ac.i32_0, ""));
3999 src_c1 = ac_to_float(&ctx->ac, LLVMBuildExtractElement(ctx->builder, src0, ctx->ac.i32_1, ""));
4000 } else if (instr->intrinsic == nir_intrinsic_interp_var_at_sample) {
4001 LLVMValueRef sample_position;
4002 LLVMValueRef halfval = LLVMConstReal(ctx->ac.f32, 0.5f);
4003
4004 /* fetch sample ID */
4005 sample_position = load_sample_position(ctx, src0);
4006
4007 src_c0 = LLVMBuildExtractElement(ctx->builder, sample_position, ctx->ac.i32_0, "");
4008 src_c0 = LLVMBuildFSub(ctx->builder, src_c0, halfval, "");
4009 src_c1 = LLVMBuildExtractElement(ctx->builder, sample_position, ctx->ac.i32_1, "");
4010 src_c1 = LLVMBuildFSub(ctx->builder, src_c1, halfval, "");
4011 }
4012 interp_param = lookup_interp_param(ctx, instr->variables[0]->var->data.interpolation, location);
4013 attr_number = LLVMConstInt(ctx->ac.i32, input_index, false);
4014
4015 if (location == INTERP_CENTER) {
4016 LLVMValueRef ij_out[2];
4017 LLVMValueRef ddxy_out = emit_ddxy_interp(ctx->nir, interp_param);
4018
4019 /*
4020 * take the I then J parameters, and the DDX/Y for it, and
4021 * calculate the IJ inputs for the interpolator.
4022 * temp1 = ddx * offset/sample.x + I;
4023 * interp_param.I = ddy * offset/sample.y + temp1;
4024 * temp1 = ddx * offset/sample.x + J;
4025 * interp_param.J = ddy * offset/sample.y + temp1;
4026 */
4027 for (unsigned i = 0; i < 2; i++) {
4028 LLVMValueRef ix_ll = LLVMConstInt(ctx->ac.i32, i, false);
4029 LLVMValueRef iy_ll = LLVMConstInt(ctx->ac.i32, i + 2, false);
4030 LLVMValueRef ddx_el = LLVMBuildExtractElement(ctx->builder,
4031 ddxy_out, ix_ll, "");
4032 LLVMValueRef ddy_el = LLVMBuildExtractElement(ctx->builder,
4033 ddxy_out, iy_ll, "");
4034 LLVMValueRef interp_el = LLVMBuildExtractElement(ctx->builder,
4035 interp_param, ix_ll, "");
4036 LLVMValueRef temp1, temp2;
4037
4038 interp_el = LLVMBuildBitCast(ctx->builder, interp_el,
4039 ctx->ac.f32, "");
4040
4041 temp1 = LLVMBuildFMul(ctx->builder, ddx_el, src_c0, "");
4042 temp1 = LLVMBuildFAdd(ctx->builder, temp1, interp_el, "");
4043
4044 temp2 = LLVMBuildFMul(ctx->builder, ddy_el, src_c1, "");
4045 temp2 = LLVMBuildFAdd(ctx->builder, temp2, temp1, "");
4046
4047 ij_out[i] = LLVMBuildBitCast(ctx->builder,
4048 temp2, ctx->ac.i32, "");
4049 }
4050 interp_param = ac_build_gather_values(&ctx->ac, ij_out, 2);
4051
4052 }
4053
4054 for (chan = 0; chan < 4; chan++) {
4055 LLVMValueRef llvm_chan = LLVMConstInt(ctx->ac.i32, chan, false);
4056
4057 if (interp_param) {
4058 interp_param = LLVMBuildBitCast(ctx->builder,
4059 interp_param, ctx->ac.v2f32, "");
4060 LLVMValueRef i = LLVMBuildExtractElement(
4061 ctx->builder, interp_param, ctx->ac.i32_0, "");
4062 LLVMValueRef j = LLVMBuildExtractElement(
4063 ctx->builder, interp_param, ctx->ac.i32_1, "");
4064
4065 result[chan] = ac_build_fs_interp(&ctx->ac,
4066 llvm_chan, attr_number,
4067 ctx->prim_mask, i, j);
4068 } else {
4069 result[chan] = ac_build_fs_interp_mov(&ctx->ac,
4070 LLVMConstInt(ctx->ac.i32, 2, false),
4071 llvm_chan, attr_number,
4072 ctx->prim_mask);
4073 }
4074 }
4075 return ac_build_varying_gather_values(&ctx->ac, result, instr->num_components,
4076 instr->variables[0]->var->data.location_frac);
4077 }
4078
4079 static void
4080 visit_emit_vertex(struct ac_shader_abi *abi, unsigned stream, LLVMValueRef *addrs)
4081 {
4082 LLVMValueRef gs_next_vertex;
4083 LLVMValueRef can_emit;
4084 int idx;
4085 struct nir_to_llvm_context *ctx = nir_to_llvm_context_from_abi(abi);
4086
4087 /* Write vertex attribute values to GSVS ring */
4088 gs_next_vertex = LLVMBuildLoad(ctx->builder,
4089 ctx->gs_next_vertex,
4090 "");
4091
4092 /* If this thread has already emitted the declared maximum number of
4093 * vertices, kill it: excessive vertex emissions are not supposed to
4094 * have any effect, and GS threads have no externally observable
4095 * effects other than emitting vertices.
4096 */
4097 can_emit = LLVMBuildICmp(ctx->builder, LLVMIntULT, gs_next_vertex,
4098 LLVMConstInt(ctx->ac.i32, ctx->gs_max_out_vertices, false), "");
4099 ac_build_kill_if_false(&ctx->ac, can_emit);
4100
4101 /* loop num outputs */
4102 idx = 0;
4103 for (unsigned i = 0; i < RADEON_LLVM_MAX_OUTPUTS; ++i) {
4104 LLVMValueRef *out_ptr = &addrs[i * 4];
4105 int length = 4;
4106 int slot = idx;
4107 int slot_inc = 1;
4108
4109 if (!(ctx->output_mask & (1ull << i)))
4110 continue;
4111
4112 if (i == VARYING_SLOT_CLIP_DIST0) {
4113 /* pack clip and cull into a single set of slots */
4114 length = ctx->num_output_clips + ctx->num_output_culls;
4115 if (length > 4)
4116 slot_inc = 2;
4117 }
4118 for (unsigned j = 0; j < length; j++) {
4119 LLVMValueRef out_val = LLVMBuildLoad(ctx->builder,
4120 out_ptr[j], "");
4121 LLVMValueRef voffset = LLVMConstInt(ctx->ac.i32, (slot * 4 + j) * ctx->gs_max_out_vertices, false);
4122 voffset = LLVMBuildAdd(ctx->builder, voffset, gs_next_vertex, "");
4123 voffset = LLVMBuildMul(ctx->builder, voffset, LLVMConstInt(ctx->ac.i32, 4, false), "");
4124
4125 out_val = LLVMBuildBitCast(ctx->builder, out_val, ctx->ac.i32, "");
4126
4127 ac_build_buffer_store_dword(&ctx->ac, ctx->gsvs_ring,
4128 out_val, 1,
4129 voffset, ctx->gs2vs_offset, 0,
4130 1, 1, true, true);
4131 }
4132 idx += slot_inc;
4133 }
4134
4135 gs_next_vertex = LLVMBuildAdd(ctx->builder, gs_next_vertex,
4136 ctx->ac.i32_1, "");
4137 LLVMBuildStore(ctx->builder, gs_next_vertex, ctx->gs_next_vertex);
4138
4139 ac_build_sendmsg(&ctx->ac, AC_SENDMSG_GS_OP_EMIT | AC_SENDMSG_GS | (0 << 8), ctx->gs_wave_id);
4140 }
4141
4142 static void
4143 visit_end_primitive(struct nir_to_llvm_context *ctx,
4144 const nir_intrinsic_instr *instr)
4145 {
4146 ac_build_sendmsg(&ctx->ac, AC_SENDMSG_GS_OP_CUT | AC_SENDMSG_GS | (0 << 8), ctx->gs_wave_id);
4147 }
4148
4149 static LLVMValueRef
4150 visit_load_tess_coord(struct nir_to_llvm_context *ctx,
4151 const nir_intrinsic_instr *instr)
4152 {
4153 LLVMValueRef coord[4] = {
4154 ctx->tes_u,
4155 ctx->tes_v,
4156 ctx->ac.f32_0,
4157 ctx->ac.f32_0,
4158 };
4159
4160 if (ctx->tes_primitive_mode == GL_TRIANGLES)
4161 coord[2] = LLVMBuildFSub(ctx->builder, ctx->ac.f32_1,
4162 LLVMBuildFAdd(ctx->builder, coord[0], coord[1], ""), "");
4163
4164 LLVMValueRef result = ac_build_gather_values(&ctx->ac, coord, instr->num_components);
4165 return LLVMBuildBitCast(ctx->builder, result,
4166 get_def_type(ctx->nir, &instr->dest.ssa), "");
4167 }
4168
4169 static void visit_intrinsic(struct ac_nir_context *ctx,
4170 nir_intrinsic_instr *instr)
4171 {
4172 LLVMValueRef result = NULL;
4173
4174 switch (instr->intrinsic) {
4175 case nir_intrinsic_load_work_group_id: {
4176 LLVMValueRef values[3];
4177
4178 for (int i = 0; i < 3; i++) {
4179 values[i] = ctx->nctx->workgroup_ids[i] ?
4180 ctx->nctx->workgroup_ids[i] : ctx->ac.i32_0;
4181 }
4182
4183 result = ac_build_gather_values(&ctx->ac, values, 3);
4184 break;
4185 }
4186 case nir_intrinsic_load_base_vertex: {
4187 result = ctx->abi->base_vertex;
4188 break;
4189 }
4190 case nir_intrinsic_load_vertex_id_zero_base: {
4191 result = ctx->abi->vertex_id;
4192 break;
4193 }
4194 case nir_intrinsic_load_local_invocation_id: {
4195 result = ctx->nctx->local_invocation_ids;
4196 break;
4197 }
4198 case nir_intrinsic_load_base_instance:
4199 result = ctx->abi->start_instance;
4200 break;
4201 case nir_intrinsic_load_draw_id:
4202 result = ctx->abi->draw_id;
4203 break;
4204 case nir_intrinsic_load_view_index:
4205 result = ctx->nctx->view_index ? ctx->nctx->view_index : ctx->ac.i32_0;
4206 break;
4207 case nir_intrinsic_load_invocation_id:
4208 if (ctx->stage == MESA_SHADER_TESS_CTRL)
4209 result = unpack_param(&ctx->ac, ctx->abi->tcs_rel_ids, 8, 5);
4210 else
4211 result = ctx->abi->gs_invocation_id;
4212 break;
4213 case nir_intrinsic_load_primitive_id:
4214 if (ctx->stage == MESA_SHADER_GEOMETRY) {
4215 result = ctx->abi->gs_prim_id;
4216 } else if (ctx->stage == MESA_SHADER_TESS_CTRL) {
4217 result = ctx->abi->tcs_patch_id;
4218 } else if (ctx->stage == MESA_SHADER_TESS_EVAL) {
4219 result = ctx->abi->tes_patch_id;
4220 } else
4221 fprintf(stderr, "Unknown primitive id intrinsic: %d", ctx->stage);
4222 break;
4223 case nir_intrinsic_load_sample_id:
4224 result = unpack_param(&ctx->ac, ctx->abi->ancillary, 8, 4);
4225 break;
4226 case nir_intrinsic_load_sample_pos:
4227 result = load_sample_pos(ctx);
4228 break;
4229 case nir_intrinsic_load_sample_mask_in:
4230 result = ctx->abi->sample_coverage;
4231 break;
4232 case nir_intrinsic_load_frag_coord: {
4233 LLVMValueRef values[4] = {
4234 ctx->abi->frag_pos[0],
4235 ctx->abi->frag_pos[1],
4236 ctx->abi->frag_pos[2],
4237 ac_build_fdiv(&ctx->ac, ctx->ac.f32_1, ctx->abi->frag_pos[3])
4238 };
4239 result = ac_build_gather_values(&ctx->ac, values, 4);
4240 break;
4241 }
4242 case nir_intrinsic_load_front_face:
4243 result = ctx->abi->front_face;
4244 break;
4245 case nir_intrinsic_load_instance_id:
4246 result = ctx->abi->instance_id;
4247 break;
4248 case nir_intrinsic_load_num_work_groups:
4249 result = ctx->nctx->num_work_groups;
4250 break;
4251 case nir_intrinsic_load_local_invocation_index:
4252 result = visit_load_local_invocation_index(ctx->nctx);
4253 break;
4254 case nir_intrinsic_load_push_constant:
4255 result = visit_load_push_constant(ctx->nctx, instr);
4256 break;
4257 case nir_intrinsic_vulkan_resource_index:
4258 result = visit_vulkan_resource_index(ctx->nctx, instr);
4259 break;
4260 case nir_intrinsic_vulkan_resource_reindex:
4261 result = visit_vulkan_resource_reindex(ctx->nctx, instr);
4262 break;
4263 case nir_intrinsic_store_ssbo:
4264 visit_store_ssbo(ctx, instr);
4265 break;
4266 case nir_intrinsic_load_ssbo:
4267 result = visit_load_buffer(ctx, instr);
4268 break;
4269 case nir_intrinsic_ssbo_atomic_add:
4270 case nir_intrinsic_ssbo_atomic_imin:
4271 case nir_intrinsic_ssbo_atomic_umin:
4272 case nir_intrinsic_ssbo_atomic_imax:
4273 case nir_intrinsic_ssbo_atomic_umax:
4274 case nir_intrinsic_ssbo_atomic_and:
4275 case nir_intrinsic_ssbo_atomic_or:
4276 case nir_intrinsic_ssbo_atomic_xor:
4277 case nir_intrinsic_ssbo_atomic_exchange:
4278 case nir_intrinsic_ssbo_atomic_comp_swap:
4279 result = visit_atomic_ssbo(ctx, instr);
4280 break;
4281 case nir_intrinsic_load_ubo:
4282 result = visit_load_ubo_buffer(ctx, instr);
4283 break;
4284 case nir_intrinsic_get_buffer_size:
4285 result = visit_get_buffer_size(ctx, instr);
4286 break;
4287 case nir_intrinsic_load_var:
4288 result = visit_load_var(ctx, instr);
4289 break;
4290 case nir_intrinsic_store_var:
4291 visit_store_var(ctx, instr);
4292 break;
4293 case nir_intrinsic_image_load:
4294 result = visit_image_load(ctx, instr);
4295 break;
4296 case nir_intrinsic_image_store:
4297 visit_image_store(ctx, instr);
4298 break;
4299 case nir_intrinsic_image_atomic_add:
4300 case nir_intrinsic_image_atomic_min:
4301 case nir_intrinsic_image_atomic_max:
4302 case nir_intrinsic_image_atomic_and:
4303 case nir_intrinsic_image_atomic_or:
4304 case nir_intrinsic_image_atomic_xor:
4305 case nir_intrinsic_image_atomic_exchange:
4306 case nir_intrinsic_image_atomic_comp_swap:
4307 result = visit_image_atomic(ctx, instr);
4308 break;
4309 case nir_intrinsic_image_size:
4310 result = visit_image_size(ctx, instr);
4311 break;
4312 case nir_intrinsic_discard:
4313 ac_build_intrinsic(&ctx->ac, "llvm.AMDGPU.kilp",
4314 LLVMVoidTypeInContext(ctx->ac.context),
4315 NULL, 0, AC_FUNC_ATTR_LEGACY);
4316 break;
4317 case nir_intrinsic_discard_if:
4318 emit_discard_if(ctx, instr);
4319 break;
4320 case nir_intrinsic_memory_barrier:
4321 case nir_intrinsic_group_memory_barrier:
4322 case nir_intrinsic_memory_barrier_atomic_counter:
4323 case nir_intrinsic_memory_barrier_buffer:
4324 case nir_intrinsic_memory_barrier_image:
4325 case nir_intrinsic_memory_barrier_shared:
4326 emit_membar(ctx->nctx, instr);
4327 break;
4328 case nir_intrinsic_barrier:
4329 emit_barrier(ctx->nctx);
4330 break;
4331 case nir_intrinsic_var_atomic_add:
4332 case nir_intrinsic_var_atomic_imin:
4333 case nir_intrinsic_var_atomic_umin:
4334 case nir_intrinsic_var_atomic_imax:
4335 case nir_intrinsic_var_atomic_umax:
4336 case nir_intrinsic_var_atomic_and:
4337 case nir_intrinsic_var_atomic_or:
4338 case nir_intrinsic_var_atomic_xor:
4339 case nir_intrinsic_var_atomic_exchange:
4340 case nir_intrinsic_var_atomic_comp_swap:
4341 result = visit_var_atomic(ctx->nctx, instr);
4342 break;
4343 case nir_intrinsic_interp_var_at_centroid:
4344 case nir_intrinsic_interp_var_at_sample:
4345 case nir_intrinsic_interp_var_at_offset:
4346 result = visit_interp(ctx->nctx, instr);
4347 break;
4348 case nir_intrinsic_emit_vertex:
4349 assert(instr->const_index[0] == 0);
4350 ctx->abi->emit_vertex(ctx->abi, 0, ctx->outputs);
4351 break;
4352 case nir_intrinsic_end_primitive:
4353 visit_end_primitive(ctx->nctx, instr);
4354 break;
4355 case nir_intrinsic_load_tess_coord:
4356 result = visit_load_tess_coord(ctx->nctx, instr);
4357 break;
4358 case nir_intrinsic_load_patch_vertices_in:
4359 result = LLVMConstInt(ctx->ac.i32, ctx->nctx->options->key.tcs.input_vertices, false);
4360 break;
4361 default:
4362 fprintf(stderr, "Unknown intrinsic: ");
4363 nir_print_instr(&instr->instr, stderr);
4364 fprintf(stderr, "\n");
4365 break;
4366 }
4367 if (result) {
4368 _mesa_hash_table_insert(ctx->defs, &instr->dest.ssa, result);
4369 }
4370 }
4371
4372 static LLVMValueRef radv_load_ssbo(struct ac_shader_abi *abi,
4373 LLVMValueRef buffer_ptr, bool write)
4374 {
4375 struct nir_to_llvm_context *ctx = nir_to_llvm_context_from_abi(abi);
4376
4377 if (write && ctx->stage == MESA_SHADER_FRAGMENT)
4378 ctx->shader_info->fs.writes_memory = true;
4379
4380 return LLVMBuildLoad(ctx->builder, buffer_ptr, "");
4381 }
4382
4383 static LLVMValueRef radv_load_ubo(struct ac_shader_abi *abi, LLVMValueRef buffer_ptr)
4384 {
4385 struct nir_to_llvm_context *ctx = nir_to_llvm_context_from_abi(abi);
4386
4387 return LLVMBuildLoad(ctx->builder, buffer_ptr, "");
4388 }
4389
4390 static LLVMValueRef radv_get_sampler_desc(struct ac_shader_abi *abi,
4391 unsigned descriptor_set,
4392 unsigned base_index,
4393 unsigned constant_index,
4394 LLVMValueRef index,
4395 enum ac_descriptor_type desc_type,
4396 bool image, bool write)
4397 {
4398 struct nir_to_llvm_context *ctx = nir_to_llvm_context_from_abi(abi);
4399 LLVMValueRef list = ctx->descriptor_sets[descriptor_set];
4400 struct radv_descriptor_set_layout *layout = ctx->options->layout->set[descriptor_set].layout;
4401 struct radv_descriptor_set_binding_layout *binding = layout->binding + base_index;
4402 unsigned offset = binding->offset;
4403 unsigned stride = binding->size;
4404 unsigned type_size;
4405 LLVMBuilderRef builder = ctx->builder;
4406 LLVMTypeRef type;
4407
4408 assert(base_index < layout->binding_count);
4409
4410 if (write && ctx->stage == MESA_SHADER_FRAGMENT)
4411 ctx->shader_info->fs.writes_memory = true;
4412
4413 switch (desc_type) {
4414 case AC_DESC_IMAGE:
4415 type = ctx->ac.v8i32;
4416 type_size = 32;
4417 break;
4418 case AC_DESC_FMASK:
4419 type = ctx->ac.v8i32;
4420 offset += 32;
4421 type_size = 32;
4422 break;
4423 case AC_DESC_SAMPLER:
4424 type = ctx->ac.v4i32;
4425 if (binding->type == VK_DESCRIPTOR_TYPE_COMBINED_IMAGE_SAMPLER)
4426 offset += 64;
4427
4428 type_size = 16;
4429 break;
4430 case AC_DESC_BUFFER:
4431 type = ctx->ac.v4i32;
4432 type_size = 16;
4433 break;
4434 default:
4435 unreachable("invalid desc_type\n");
4436 }
4437
4438 offset += constant_index * stride;
4439
4440 if (desc_type == AC_DESC_SAMPLER && binding->immutable_samplers_offset &&
4441 (!index || binding->immutable_samplers_equal)) {
4442 if (binding->immutable_samplers_equal)
4443 constant_index = 0;
4444
4445 const uint32_t *samplers = radv_immutable_samplers(layout, binding);
4446
4447 LLVMValueRef constants[] = {
4448 LLVMConstInt(ctx->ac.i32, samplers[constant_index * 4 + 0], 0),
4449 LLVMConstInt(ctx->ac.i32, samplers[constant_index * 4 + 1], 0),
4450 LLVMConstInt(ctx->ac.i32, samplers[constant_index * 4 + 2], 0),
4451 LLVMConstInt(ctx->ac.i32, samplers[constant_index * 4 + 3], 0),
4452 };
4453 return ac_build_gather_values(&ctx->ac, constants, 4);
4454 }
4455
4456 assert(stride % type_size == 0);
4457
4458 if (!index)
4459 index = ctx->ac.i32_0;
4460
4461 index = LLVMBuildMul(builder, index, LLVMConstInt(ctx->ac.i32, stride / type_size, 0), "");
4462
4463 list = ac_build_gep0(&ctx->ac, list, LLVMConstInt(ctx->ac.i32, offset, 0));
4464 list = LLVMBuildPointerCast(builder, list, const_array(type, 0), "");
4465
4466 return ac_build_load_to_sgpr(&ctx->ac, list, index);
4467 }
4468
4469 static LLVMValueRef get_sampler_desc(struct ac_nir_context *ctx,
4470 const nir_deref_var *deref,
4471 enum ac_descriptor_type desc_type,
4472 const nir_tex_instr *tex_instr,
4473 bool image, bool write)
4474 {
4475 LLVMValueRef index = NULL;
4476 unsigned constant_index = 0;
4477 unsigned descriptor_set;
4478 unsigned base_index;
4479
4480 if (!deref) {
4481 assert(tex_instr && !image);
4482 descriptor_set = 0;
4483 base_index = tex_instr->sampler_index;
4484 } else {
4485 const nir_deref *tail = &deref->deref;
4486 while (tail->child) {
4487 const nir_deref_array *child = nir_deref_as_array(tail->child);
4488 unsigned array_size = glsl_get_aoa_size(tail->child->type);
4489
4490 if (!array_size)
4491 array_size = 1;
4492
4493 assert(child->deref_array_type != nir_deref_array_type_wildcard);
4494
4495 if (child->deref_array_type == nir_deref_array_type_indirect) {
4496 LLVMValueRef indirect = get_src(ctx, child->indirect);
4497
4498 indirect = LLVMBuildMul(ctx->ac.builder, indirect,
4499 LLVMConstInt(ctx->ac.i32, array_size, false), "");
4500
4501 if (!index)
4502 index = indirect;
4503 else
4504 index = LLVMBuildAdd(ctx->ac.builder, index, indirect, "");
4505 }
4506
4507 constant_index += child->base_offset * array_size;
4508
4509 tail = &child->deref;
4510 }
4511 descriptor_set = deref->var->data.descriptor_set;
4512 base_index = deref->var->data.binding;
4513 }
4514
4515 return ctx->abi->load_sampler_desc(ctx->abi,
4516 descriptor_set,
4517 base_index,
4518 constant_index, index,
4519 desc_type, image, write);
4520 }
4521
4522 static void set_tex_fetch_args(struct ac_llvm_context *ctx,
4523 struct ac_image_args *args,
4524 const nir_tex_instr *instr,
4525 nir_texop op,
4526 LLVMValueRef res_ptr, LLVMValueRef samp_ptr,
4527 LLVMValueRef *param, unsigned count,
4528 unsigned dmask)
4529 {
4530 unsigned is_rect = 0;
4531 bool da = instr->is_array || instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE;
4532
4533 if (op == nir_texop_lod)
4534 da = false;
4535 /* Pad to power of two vector */
4536 while (count < util_next_power_of_two(count))
4537 param[count++] = LLVMGetUndef(ctx->i32);
4538
4539 if (count > 1)
4540 args->addr = ac_build_gather_values(ctx, param, count);
4541 else
4542 args->addr = param[0];
4543
4544 args->resource = res_ptr;
4545 args->sampler = samp_ptr;
4546
4547 if (instr->sampler_dim == GLSL_SAMPLER_DIM_BUF && op == nir_texop_txf) {
4548 args->addr = param[0];
4549 return;
4550 }
4551
4552 args->dmask = dmask;
4553 args->unorm = is_rect;
4554 args->da = da;
4555 }
4556
4557 /* Disable anisotropic filtering if BASE_LEVEL == LAST_LEVEL.
4558 *
4559 * SI-CI:
4560 * If BASE_LEVEL == LAST_LEVEL, the shader must disable anisotropic
4561 * filtering manually. The driver sets img7 to a mask clearing
4562 * MAX_ANISO_RATIO if BASE_LEVEL == LAST_LEVEL. The shader must do:
4563 * s_and_b32 samp0, samp0, img7
4564 *
4565 * VI:
4566 * The ANISO_OVERRIDE sampler field enables this fix in TA.
4567 */
4568 static LLVMValueRef sici_fix_sampler_aniso(struct ac_nir_context *ctx,
4569 LLVMValueRef res, LLVMValueRef samp)
4570 {
4571 LLVMBuilderRef builder = ctx->ac.builder;
4572 LLVMValueRef img7, samp0;
4573
4574 if (ctx->ac.chip_class >= VI)
4575 return samp;
4576
4577 img7 = LLVMBuildExtractElement(builder, res,
4578 LLVMConstInt(ctx->ac.i32, 7, 0), "");
4579 samp0 = LLVMBuildExtractElement(builder, samp,
4580 LLVMConstInt(ctx->ac.i32, 0, 0), "");
4581 samp0 = LLVMBuildAnd(builder, samp0, img7, "");
4582 return LLVMBuildInsertElement(builder, samp, samp0,
4583 LLVMConstInt(ctx->ac.i32, 0, 0), "");
4584 }
4585
4586 static void tex_fetch_ptrs(struct ac_nir_context *ctx,
4587 nir_tex_instr *instr,
4588 LLVMValueRef *res_ptr, LLVMValueRef *samp_ptr,
4589 LLVMValueRef *fmask_ptr)
4590 {
4591 if (instr->sampler_dim == GLSL_SAMPLER_DIM_BUF)
4592 *res_ptr = get_sampler_desc(ctx, instr->texture, AC_DESC_BUFFER, instr, false, false);
4593 else
4594 *res_ptr = get_sampler_desc(ctx, instr->texture, AC_DESC_IMAGE, instr, false, false);
4595 if (samp_ptr) {
4596 if (instr->sampler)
4597 *samp_ptr = get_sampler_desc(ctx, instr->sampler, AC_DESC_SAMPLER, instr, false, false);
4598 else
4599 *samp_ptr = get_sampler_desc(ctx, instr->texture, AC_DESC_SAMPLER, instr, false, false);
4600 if (instr->sampler_dim < GLSL_SAMPLER_DIM_RECT)
4601 *samp_ptr = sici_fix_sampler_aniso(ctx, *res_ptr, *samp_ptr);
4602 }
4603 if (fmask_ptr && !instr->sampler && (instr->op == nir_texop_txf_ms ||
4604 instr->op == nir_texop_samples_identical))
4605 *fmask_ptr = get_sampler_desc(ctx, instr->texture, AC_DESC_FMASK, instr, false, false);
4606 }
4607
4608 static LLVMValueRef apply_round_slice(struct ac_llvm_context *ctx,
4609 LLVMValueRef coord)
4610 {
4611 coord = ac_to_float(ctx, coord);
4612 coord = ac_build_intrinsic(ctx, "llvm.rint.f32", ctx->f32, &coord, 1, 0);
4613 coord = ac_to_integer(ctx, coord);
4614 return coord;
4615 }
4616
4617 static void visit_tex(struct ac_nir_context *ctx, nir_tex_instr *instr)
4618 {
4619 LLVMValueRef result = NULL;
4620 struct ac_image_args args = { 0 };
4621 unsigned dmask = 0xf;
4622 LLVMValueRef address[16];
4623 LLVMValueRef coords[5];
4624 LLVMValueRef coord = NULL, lod = NULL, comparator = NULL;
4625 LLVMValueRef bias = NULL, offsets = NULL;
4626 LLVMValueRef res_ptr, samp_ptr, fmask_ptr = NULL, sample_index = NULL;
4627 LLVMValueRef ddx = NULL, ddy = NULL;
4628 LLVMValueRef derivs[6];
4629 unsigned chan, count = 0;
4630 unsigned const_src = 0, num_deriv_comp = 0;
4631 bool lod_is_zero = false;
4632
4633 tex_fetch_ptrs(ctx, instr, &res_ptr, &samp_ptr, &fmask_ptr);
4634
4635 for (unsigned i = 0; i < instr->num_srcs; i++) {
4636 switch (instr->src[i].src_type) {
4637 case nir_tex_src_coord:
4638 coord = get_src(ctx, instr->src[i].src);
4639 break;
4640 case nir_tex_src_projector:
4641 break;
4642 case nir_tex_src_comparator:
4643 comparator = get_src(ctx, instr->src[i].src);
4644 break;
4645 case nir_tex_src_offset:
4646 offsets = get_src(ctx, instr->src[i].src);
4647 const_src = i;
4648 break;
4649 case nir_tex_src_bias:
4650 bias = get_src(ctx, instr->src[i].src);
4651 break;
4652 case nir_tex_src_lod: {
4653 nir_const_value *val = nir_src_as_const_value(instr->src[i].src);
4654
4655 if (val && val->i32[0] == 0)
4656 lod_is_zero = true;
4657 lod = get_src(ctx, instr->src[i].src);
4658 break;
4659 }
4660 case nir_tex_src_ms_index:
4661 sample_index = get_src(ctx, instr->src[i].src);
4662 break;
4663 case nir_tex_src_ms_mcs:
4664 break;
4665 case nir_tex_src_ddx:
4666 ddx = get_src(ctx, instr->src[i].src);
4667 num_deriv_comp = instr->src[i].src.ssa->num_components;
4668 break;
4669 case nir_tex_src_ddy:
4670 ddy = get_src(ctx, instr->src[i].src);
4671 break;
4672 case nir_tex_src_texture_offset:
4673 case nir_tex_src_sampler_offset:
4674 case nir_tex_src_plane:
4675 default:
4676 break;
4677 }
4678 }
4679
4680 if (instr->op == nir_texop_txs && instr->sampler_dim == GLSL_SAMPLER_DIM_BUF) {
4681 result = get_buffer_size(ctx, res_ptr, true);
4682 goto write_result;
4683 }
4684
4685 if (instr->op == nir_texop_texture_samples) {
4686 LLVMValueRef res, samples, is_msaa;
4687 res = LLVMBuildBitCast(ctx->ac.builder, res_ptr, ctx->ac.v8i32, "");
4688 samples = LLVMBuildExtractElement(ctx->ac.builder, res,
4689 LLVMConstInt(ctx->ac.i32, 3, false), "");
4690 is_msaa = LLVMBuildLShr(ctx->ac.builder, samples,
4691 LLVMConstInt(ctx->ac.i32, 28, false), "");
4692 is_msaa = LLVMBuildAnd(ctx->ac.builder, is_msaa,
4693 LLVMConstInt(ctx->ac.i32, 0xe, false), "");
4694 is_msaa = LLVMBuildICmp(ctx->ac.builder, LLVMIntEQ, is_msaa,
4695 LLVMConstInt(ctx->ac.i32, 0xe, false), "");
4696
4697 samples = LLVMBuildLShr(ctx->ac.builder, samples,
4698 LLVMConstInt(ctx->ac.i32, 16, false), "");
4699 samples = LLVMBuildAnd(ctx->ac.builder, samples,
4700 LLVMConstInt(ctx->ac.i32, 0xf, false), "");
4701 samples = LLVMBuildShl(ctx->ac.builder, ctx->ac.i32_1,
4702 samples, "");
4703 samples = LLVMBuildSelect(ctx->ac.builder, is_msaa, samples,
4704 ctx->ac.i32_1, "");
4705 result = samples;
4706 goto write_result;
4707 }
4708
4709 if (coord)
4710 for (chan = 0; chan < instr->coord_components; chan++)
4711 coords[chan] = ac_llvm_extract_elem(&ctx->ac, coord, chan);
4712
4713 if (offsets && instr->op != nir_texop_txf) {
4714 LLVMValueRef offset[3], pack;
4715 for (chan = 0; chan < 3; ++chan)
4716 offset[chan] = ctx->ac.i32_0;
4717
4718 args.offset = true;
4719 for (chan = 0; chan < ac_get_llvm_num_components(offsets); chan++) {
4720 offset[chan] = ac_llvm_extract_elem(&ctx->ac, offsets, chan);
4721 offset[chan] = LLVMBuildAnd(ctx->ac.builder, offset[chan],
4722 LLVMConstInt(ctx->ac.i32, 0x3f, false), "");
4723 if (chan)
4724 offset[chan] = LLVMBuildShl(ctx->ac.builder, offset[chan],
4725 LLVMConstInt(ctx->ac.i32, chan * 8, false), "");
4726 }
4727 pack = LLVMBuildOr(ctx->ac.builder, offset[0], offset[1], "");
4728 pack = LLVMBuildOr(ctx->ac.builder, pack, offset[2], "");
4729 address[count++] = pack;
4730
4731 }
4732 /* pack LOD bias value */
4733 if (instr->op == nir_texop_txb && bias) {
4734 address[count++] = bias;
4735 }
4736
4737 /* Pack depth comparison value */
4738 if (instr->is_shadow && comparator) {
4739 LLVMValueRef z = ac_to_float(&ctx->ac,
4740 ac_llvm_extract_elem(&ctx->ac, comparator, 0));
4741
4742 /* TC-compatible HTILE on radeonsi promotes Z16 and Z24 to Z32_FLOAT,
4743 * so the depth comparison value isn't clamped for Z16 and
4744 * Z24 anymore. Do it manually here.
4745 *
4746 * It's unnecessary if the original texture format was
4747 * Z32_FLOAT, but we don't know that here.
4748 */
4749 if (ctx->ac.chip_class == VI && ctx->abi->clamp_shadow_reference)
4750 z = ac_build_clamp(&ctx->ac, z);
4751
4752 address[count++] = z;
4753 }
4754
4755 /* pack derivatives */
4756 if (ddx || ddy) {
4757 int num_src_deriv_channels, num_dest_deriv_channels;
4758 switch (instr->sampler_dim) {
4759 case GLSL_SAMPLER_DIM_3D:
4760 case GLSL_SAMPLER_DIM_CUBE:
4761 num_deriv_comp = 3;
4762 num_src_deriv_channels = 3;
4763 num_dest_deriv_channels = 3;
4764 break;
4765 case GLSL_SAMPLER_DIM_2D:
4766 default:
4767 num_src_deriv_channels = 2;
4768 num_dest_deriv_channels = 2;
4769 num_deriv_comp = 2;
4770 break;
4771 case GLSL_SAMPLER_DIM_1D:
4772 num_src_deriv_channels = 1;
4773 if (ctx->ac.chip_class >= GFX9) {
4774 num_dest_deriv_channels = 2;
4775 num_deriv_comp = 2;
4776 } else {
4777 num_dest_deriv_channels = 1;
4778 num_deriv_comp = 1;
4779 }
4780 break;
4781 }
4782
4783 for (unsigned i = 0; i < num_src_deriv_channels; i++) {
4784 derivs[i] = ac_to_float(&ctx->ac, ac_llvm_extract_elem(&ctx->ac, ddx, i));
4785 derivs[num_dest_deriv_channels + i] = ac_to_float(&ctx->ac, ac_llvm_extract_elem(&ctx->ac, ddy, i));
4786 }
4787 for (unsigned i = num_src_deriv_channels; i < num_dest_deriv_channels; i++) {
4788 derivs[i] = ctx->ac.f32_0;
4789 derivs[num_dest_deriv_channels + i] = ctx->ac.f32_0;
4790 }
4791 }
4792
4793 if (instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE && coord) {
4794 for (chan = 0; chan < instr->coord_components; chan++)
4795 coords[chan] = ac_to_float(&ctx->ac, coords[chan]);
4796 if (instr->coord_components == 3)
4797 coords[3] = LLVMGetUndef(ctx->ac.f32);
4798 ac_prepare_cube_coords(&ctx->ac,
4799 instr->op == nir_texop_txd, instr->is_array,
4800 instr->op == nir_texop_lod, coords, derivs);
4801 if (num_deriv_comp)
4802 num_deriv_comp--;
4803 }
4804
4805 if (ddx || ddy) {
4806 for (unsigned i = 0; i < num_deriv_comp * 2; i++)
4807 address[count++] = derivs[i];
4808 }
4809
4810 /* Pack texture coordinates */
4811 if (coord) {
4812 address[count++] = coords[0];
4813 if (instr->coord_components > 1) {
4814 if (instr->sampler_dim == GLSL_SAMPLER_DIM_1D && instr->is_array && instr->op != nir_texop_txf) {
4815 coords[1] = apply_round_slice(&ctx->ac, coords[1]);
4816 }
4817 address[count++] = coords[1];
4818 }
4819 if (instr->coord_components > 2) {
4820 /* This seems like a bit of a hack - but it passes Vulkan CTS with it */
4821 if (instr->sampler_dim != GLSL_SAMPLER_DIM_3D &&
4822 instr->sampler_dim != GLSL_SAMPLER_DIM_CUBE &&
4823 instr->op != nir_texop_txf) {
4824 coords[2] = apply_round_slice(&ctx->ac, coords[2]);
4825 }
4826 address[count++] = coords[2];
4827 }
4828
4829 if (ctx->ac.chip_class >= GFX9) {
4830 LLVMValueRef filler;
4831 if (instr->op == nir_texop_txf)
4832 filler = ctx->ac.i32_0;
4833 else
4834 filler = LLVMConstReal(ctx->ac.f32, 0.5);
4835
4836 if (instr->sampler_dim == GLSL_SAMPLER_DIM_1D) {
4837 /* No nir_texop_lod, because it does not take a slice
4838 * even with array textures. */
4839 if (instr->is_array && instr->op != nir_texop_lod ) {
4840 address[count] = address[count - 1];
4841 address[count - 1] = filler;
4842 count++;
4843 } else
4844 address[count++] = filler;
4845 }
4846 }
4847 }
4848
4849 /* Pack LOD */
4850 if (lod && ((instr->op == nir_texop_txl && !lod_is_zero) ||
4851 instr->op == nir_texop_txf)) {
4852 address[count++] = lod;
4853 } else if (instr->op == nir_texop_txf_ms && sample_index) {
4854 address[count++] = sample_index;
4855 } else if(instr->op == nir_texop_txs) {
4856 count = 0;
4857 if (lod)
4858 address[count++] = lod;
4859 else
4860 address[count++] = ctx->ac.i32_0;
4861 }
4862
4863 for (chan = 0; chan < count; chan++) {
4864 address[chan] = LLVMBuildBitCast(ctx->ac.builder,
4865 address[chan], ctx->ac.i32, "");
4866 }
4867
4868 if (instr->op == nir_texop_samples_identical) {
4869 LLVMValueRef txf_address[4];
4870 struct ac_image_args txf_args = { 0 };
4871 unsigned txf_count = count;
4872 memcpy(txf_address, address, sizeof(txf_address));
4873
4874 if (!instr->is_array)
4875 txf_address[2] = ctx->ac.i32_0;
4876 txf_address[3] = ctx->ac.i32_0;
4877
4878 set_tex_fetch_args(&ctx->ac, &txf_args, instr, nir_texop_txf,
4879 fmask_ptr, NULL,
4880 txf_address, txf_count, 0xf);
4881
4882 result = build_tex_intrinsic(ctx, instr, false, &txf_args);
4883
4884 result = LLVMBuildExtractElement(ctx->ac.builder, result, ctx->ac.i32_0, "");
4885 result = emit_int_cmp(&ctx->ac, LLVMIntEQ, result, ctx->ac.i32_0);
4886 goto write_result;
4887 }
4888
4889 if (instr->sampler_dim == GLSL_SAMPLER_DIM_MS &&
4890 instr->op != nir_texop_txs) {
4891 unsigned sample_chan = instr->is_array ? 3 : 2;
4892 address[sample_chan] = adjust_sample_index_using_fmask(&ctx->ac,
4893 address[0],
4894 address[1],
4895 instr->is_array ? address[2] : NULL,
4896 address[sample_chan],
4897 fmask_ptr);
4898 }
4899
4900 if (offsets && instr->op == nir_texop_txf) {
4901 nir_const_value *const_offset =
4902 nir_src_as_const_value(instr->src[const_src].src);
4903 int num_offsets = instr->src[const_src].src.ssa->num_components;
4904 assert(const_offset);
4905 num_offsets = MIN2(num_offsets, instr->coord_components);
4906 if (num_offsets > 2)
4907 address[2] = LLVMBuildAdd(ctx->ac.builder,
4908 address[2], LLVMConstInt(ctx->ac.i32, const_offset->i32[2], false), "");
4909 if (num_offsets > 1)
4910 address[1] = LLVMBuildAdd(ctx->ac.builder,
4911 address[1], LLVMConstInt(ctx->ac.i32, const_offset->i32[1], false), "");
4912 address[0] = LLVMBuildAdd(ctx->ac.builder,
4913 address[0], LLVMConstInt(ctx->ac.i32, const_offset->i32[0], false), "");
4914
4915 }
4916
4917 /* TODO TG4 support */
4918 if (instr->op == nir_texop_tg4) {
4919 if (instr->is_shadow)
4920 dmask = 1;
4921 else
4922 dmask = 1 << instr->component;
4923 }
4924 set_tex_fetch_args(&ctx->ac, &args, instr, instr->op,
4925 res_ptr, samp_ptr, address, count, dmask);
4926
4927 result = build_tex_intrinsic(ctx, instr, lod_is_zero, &args);
4928
4929 if (instr->op == nir_texop_query_levels)
4930 result = LLVMBuildExtractElement(ctx->ac.builder, result, LLVMConstInt(ctx->ac.i32, 3, false), "");
4931 else if (instr->is_shadow && instr->is_new_style_shadow &&
4932 instr->op != nir_texop_txs && instr->op != nir_texop_lod &&
4933 instr->op != nir_texop_tg4)
4934 result = LLVMBuildExtractElement(ctx->ac.builder, result, ctx->ac.i32_0, "");
4935 else if (instr->op == nir_texop_txs &&
4936 instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE &&
4937 instr->is_array) {
4938 LLVMValueRef two = LLVMConstInt(ctx->ac.i32, 2, false);
4939 LLVMValueRef six = LLVMConstInt(ctx->ac.i32, 6, false);
4940 LLVMValueRef z = LLVMBuildExtractElement(ctx->ac.builder, result, two, "");
4941 z = LLVMBuildSDiv(ctx->ac.builder, z, six, "");
4942 result = LLVMBuildInsertElement(ctx->ac.builder, result, z, two, "");
4943 } else if (ctx->ac.chip_class >= GFX9 &&
4944 instr->op == nir_texop_txs &&
4945 instr->sampler_dim == GLSL_SAMPLER_DIM_1D &&
4946 instr->is_array) {
4947 LLVMValueRef two = LLVMConstInt(ctx->ac.i32, 2, false);
4948 LLVMValueRef layers = LLVMBuildExtractElement(ctx->ac.builder, result, two, "");
4949 result = LLVMBuildInsertElement(ctx->ac.builder, result, layers,
4950 ctx->ac.i32_1, "");
4951 } else if (instr->dest.ssa.num_components != 4)
4952 result = trim_vector(&ctx->ac, result, instr->dest.ssa.num_components);
4953
4954 write_result:
4955 if (result) {
4956 assert(instr->dest.is_ssa);
4957 result = ac_to_integer(&ctx->ac, result);
4958 _mesa_hash_table_insert(ctx->defs, &instr->dest.ssa, result);
4959 }
4960 }
4961
4962
4963 static void visit_phi(struct ac_nir_context *ctx, nir_phi_instr *instr)
4964 {
4965 LLVMTypeRef type = get_def_type(ctx, &instr->dest.ssa);
4966 LLVMValueRef result = LLVMBuildPhi(ctx->ac.builder, type, "");
4967
4968 _mesa_hash_table_insert(ctx->defs, &instr->dest.ssa, result);
4969 _mesa_hash_table_insert(ctx->phis, instr, result);
4970 }
4971
4972 static void visit_post_phi(struct ac_nir_context *ctx,
4973 nir_phi_instr *instr,
4974 LLVMValueRef llvm_phi)
4975 {
4976 nir_foreach_phi_src(src, instr) {
4977 LLVMBasicBlockRef block = get_block(ctx, src->pred);
4978 LLVMValueRef llvm_src = get_src(ctx, src->src);
4979
4980 LLVMAddIncoming(llvm_phi, &llvm_src, &block, 1);
4981 }
4982 }
4983
4984 static void phi_post_pass(struct ac_nir_context *ctx)
4985 {
4986 struct hash_entry *entry;
4987 hash_table_foreach(ctx->phis, entry) {
4988 visit_post_phi(ctx, (nir_phi_instr*)entry->key,
4989 (LLVMValueRef)entry->data);
4990 }
4991 }
4992
4993
4994 static void visit_ssa_undef(struct ac_nir_context *ctx,
4995 const nir_ssa_undef_instr *instr)
4996 {
4997 unsigned num_components = instr->def.num_components;
4998 LLVMValueRef undef;
4999
5000 if (num_components == 1)
5001 undef = LLVMGetUndef(ctx->ac.i32);
5002 else {
5003 undef = LLVMGetUndef(LLVMVectorType(ctx->ac.i32, num_components));
5004 }
5005 _mesa_hash_table_insert(ctx->defs, &instr->def, undef);
5006 }
5007
5008 static void visit_jump(struct ac_nir_context *ctx,
5009 const nir_jump_instr *instr)
5010 {
5011 switch (instr->type) {
5012 case nir_jump_break:
5013 LLVMBuildBr(ctx->ac.builder, ctx->break_block);
5014 LLVMClearInsertionPosition(ctx->ac.builder);
5015 break;
5016 case nir_jump_continue:
5017 LLVMBuildBr(ctx->ac.builder, ctx->continue_block);
5018 LLVMClearInsertionPosition(ctx->ac.builder);
5019 break;
5020 default:
5021 fprintf(stderr, "Unknown NIR jump instr: ");
5022 nir_print_instr(&instr->instr, stderr);
5023 fprintf(stderr, "\n");
5024 abort();
5025 }
5026 }
5027
5028 static void visit_cf_list(struct ac_nir_context *ctx,
5029 struct exec_list *list);
5030
5031 static void visit_block(struct ac_nir_context *ctx, nir_block *block)
5032 {
5033 LLVMBasicBlockRef llvm_block = LLVMGetInsertBlock(ctx->ac.builder);
5034 nir_foreach_instr(instr, block)
5035 {
5036 switch (instr->type) {
5037 case nir_instr_type_alu:
5038 visit_alu(ctx, nir_instr_as_alu(instr));
5039 break;
5040 case nir_instr_type_load_const:
5041 visit_load_const(ctx, nir_instr_as_load_const(instr));
5042 break;
5043 case nir_instr_type_intrinsic:
5044 visit_intrinsic(ctx, nir_instr_as_intrinsic(instr));
5045 break;
5046 case nir_instr_type_tex:
5047 visit_tex(ctx, nir_instr_as_tex(instr));
5048 break;
5049 case nir_instr_type_phi:
5050 visit_phi(ctx, nir_instr_as_phi(instr));
5051 break;
5052 case nir_instr_type_ssa_undef:
5053 visit_ssa_undef(ctx, nir_instr_as_ssa_undef(instr));
5054 break;
5055 case nir_instr_type_jump:
5056 visit_jump(ctx, nir_instr_as_jump(instr));
5057 break;
5058 default:
5059 fprintf(stderr, "Unknown NIR instr type: ");
5060 nir_print_instr(instr, stderr);
5061 fprintf(stderr, "\n");
5062 abort();
5063 }
5064 }
5065
5066 _mesa_hash_table_insert(ctx->defs, block, llvm_block);
5067 }
5068
5069 static void visit_if(struct ac_nir_context *ctx, nir_if *if_stmt)
5070 {
5071 LLVMValueRef value = get_src(ctx, if_stmt->condition);
5072
5073 LLVMValueRef fn = LLVMGetBasicBlockParent(LLVMGetInsertBlock(ctx->ac.builder));
5074 LLVMBasicBlockRef merge_block =
5075 LLVMAppendBasicBlockInContext(ctx->ac.context, fn, "");
5076 LLVMBasicBlockRef if_block =
5077 LLVMAppendBasicBlockInContext(ctx->ac.context, fn, "");
5078 LLVMBasicBlockRef else_block = merge_block;
5079 if (!exec_list_is_empty(&if_stmt->else_list))
5080 else_block = LLVMAppendBasicBlockInContext(
5081 ctx->ac.context, fn, "");
5082
5083 LLVMValueRef cond = LLVMBuildICmp(ctx->ac.builder, LLVMIntNE, value,
5084 ctx->ac.i32_0, "");
5085 LLVMBuildCondBr(ctx->ac.builder, cond, if_block, else_block);
5086
5087 LLVMPositionBuilderAtEnd(ctx->ac.builder, if_block);
5088 visit_cf_list(ctx, &if_stmt->then_list);
5089 if (LLVMGetInsertBlock(ctx->ac.builder))
5090 LLVMBuildBr(ctx->ac.builder, merge_block);
5091
5092 if (!exec_list_is_empty(&if_stmt->else_list)) {
5093 LLVMPositionBuilderAtEnd(ctx->ac.builder, else_block);
5094 visit_cf_list(ctx, &if_stmt->else_list);
5095 if (LLVMGetInsertBlock(ctx->ac.builder))
5096 LLVMBuildBr(ctx->ac.builder, merge_block);
5097 }
5098
5099 LLVMPositionBuilderAtEnd(ctx->ac.builder, merge_block);
5100 }
5101
5102 static void visit_loop(struct ac_nir_context *ctx, nir_loop *loop)
5103 {
5104 LLVMValueRef fn = LLVMGetBasicBlockParent(LLVMGetInsertBlock(ctx->ac.builder));
5105 LLVMBasicBlockRef continue_parent = ctx->continue_block;
5106 LLVMBasicBlockRef break_parent = ctx->break_block;
5107
5108 ctx->continue_block =
5109 LLVMAppendBasicBlockInContext(ctx->ac.context, fn, "");
5110 ctx->break_block =
5111 LLVMAppendBasicBlockInContext(ctx->ac.context, fn, "");
5112
5113 LLVMBuildBr(ctx->ac.builder, ctx->continue_block);
5114 LLVMPositionBuilderAtEnd(ctx->ac.builder, ctx->continue_block);
5115 visit_cf_list(ctx, &loop->body);
5116
5117 if (LLVMGetInsertBlock(ctx->ac.builder))
5118 LLVMBuildBr(ctx->ac.builder, ctx->continue_block);
5119 LLVMPositionBuilderAtEnd(ctx->ac.builder, ctx->break_block);
5120
5121 ctx->continue_block = continue_parent;
5122 ctx->break_block = break_parent;
5123 }
5124
5125 static void visit_cf_list(struct ac_nir_context *ctx,
5126 struct exec_list *list)
5127 {
5128 foreach_list_typed(nir_cf_node, node, node, list)
5129 {
5130 switch (node->type) {
5131 case nir_cf_node_block:
5132 visit_block(ctx, nir_cf_node_as_block(node));
5133 break;
5134
5135 case nir_cf_node_if:
5136 visit_if(ctx, nir_cf_node_as_if(node));
5137 break;
5138
5139 case nir_cf_node_loop:
5140 visit_loop(ctx, nir_cf_node_as_loop(node));
5141 break;
5142
5143 default:
5144 assert(0);
5145 }
5146 }
5147 }
5148
5149 static void
5150 handle_vs_input_decl(struct nir_to_llvm_context *ctx,
5151 struct nir_variable *variable)
5152 {
5153 LLVMValueRef t_list_ptr = ctx->vertex_buffers;
5154 LLVMValueRef t_offset;
5155 LLVMValueRef t_list;
5156 LLVMValueRef input;
5157 LLVMValueRef buffer_index;
5158 int index = variable->data.location - VERT_ATTRIB_GENERIC0;
5159 int idx = variable->data.location;
5160 unsigned attrib_count = glsl_count_attribute_slots(variable->type, true);
5161
5162 variable->data.driver_location = idx * 4;
5163
5164 if (ctx->options->key.vs.instance_rate_inputs & (1u << index)) {
5165 buffer_index = LLVMBuildAdd(ctx->builder, ctx->abi.instance_id,
5166 ctx->abi.start_instance, "");
5167 ctx->shader_info->vs.vgpr_comp_cnt = MAX2(3,
5168 ctx->shader_info->vs.vgpr_comp_cnt);
5169 } else
5170 buffer_index = LLVMBuildAdd(ctx->builder, ctx->abi.vertex_id,
5171 ctx->abi.base_vertex, "");
5172
5173 for (unsigned i = 0; i < attrib_count; ++i, ++idx) {
5174 t_offset = LLVMConstInt(ctx->ac.i32, index + i, false);
5175
5176 t_list = ac_build_load_to_sgpr(&ctx->ac, t_list_ptr, t_offset);
5177
5178 input = ac_build_buffer_load_format(&ctx->ac, t_list,
5179 buffer_index,
5180 ctx->ac.i32_0,
5181 true);
5182
5183 for (unsigned chan = 0; chan < 4; chan++) {
5184 LLVMValueRef llvm_chan = LLVMConstInt(ctx->ac.i32, chan, false);
5185 ctx->inputs[radeon_llvm_reg_index_soa(idx, chan)] =
5186 ac_to_integer(&ctx->ac, LLVMBuildExtractElement(ctx->builder,
5187 input, llvm_chan, ""));
5188 }
5189 }
5190 }
5191
5192 static void interp_fs_input(struct nir_to_llvm_context *ctx,
5193 unsigned attr,
5194 LLVMValueRef interp_param,
5195 LLVMValueRef prim_mask,
5196 LLVMValueRef result[4])
5197 {
5198 LLVMValueRef attr_number;
5199 unsigned chan;
5200 LLVMValueRef i, j;
5201 bool interp = interp_param != NULL;
5202
5203 attr_number = LLVMConstInt(ctx->ac.i32, attr, false);
5204
5205 /* fs.constant returns the param from the middle vertex, so it's not
5206 * really useful for flat shading. It's meant to be used for custom
5207 * interpolation (but the intrinsic can't fetch from the other two
5208 * vertices).
5209 *
5210 * Luckily, it doesn't matter, because we rely on the FLAT_SHADE state
5211 * to do the right thing. The only reason we use fs.constant is that
5212 * fs.interp cannot be used on integers, because they can be equal
5213 * to NaN.
5214 */
5215 if (interp) {
5216 interp_param = LLVMBuildBitCast(ctx->builder, interp_param,
5217 ctx->ac.v2f32, "");
5218
5219 i = LLVMBuildExtractElement(ctx->builder, interp_param,
5220 ctx->ac.i32_0, "");
5221 j = LLVMBuildExtractElement(ctx->builder, interp_param,
5222 ctx->ac.i32_1, "");
5223 }
5224
5225 for (chan = 0; chan < 4; chan++) {
5226 LLVMValueRef llvm_chan = LLVMConstInt(ctx->ac.i32, chan, false);
5227
5228 if (interp) {
5229 result[chan] = ac_build_fs_interp(&ctx->ac,
5230 llvm_chan,
5231 attr_number,
5232 prim_mask, i, j);
5233 } else {
5234 result[chan] = ac_build_fs_interp_mov(&ctx->ac,
5235 LLVMConstInt(ctx->ac.i32, 2, false),
5236 llvm_chan,
5237 attr_number,
5238 prim_mask);
5239 }
5240 }
5241 }
5242
5243 static void
5244 handle_fs_input_decl(struct nir_to_llvm_context *ctx,
5245 struct nir_variable *variable)
5246 {
5247 int idx = variable->data.location;
5248 unsigned attrib_count = glsl_count_attribute_slots(variable->type, false);
5249 LLVMValueRef interp;
5250
5251 variable->data.driver_location = idx * 4;
5252 ctx->input_mask |= ((1ull << attrib_count) - 1) << variable->data.location;
5253
5254 if (glsl_get_base_type(glsl_without_array(variable->type)) == GLSL_TYPE_FLOAT) {
5255 unsigned interp_type;
5256 if (variable->data.sample) {
5257 interp_type = INTERP_SAMPLE;
5258 ctx->shader_info->info.ps.force_persample = true;
5259 } else if (variable->data.centroid)
5260 interp_type = INTERP_CENTROID;
5261 else
5262 interp_type = INTERP_CENTER;
5263
5264 interp = lookup_interp_param(ctx, variable->data.interpolation, interp_type);
5265 } else
5266 interp = NULL;
5267
5268 for (unsigned i = 0; i < attrib_count; ++i)
5269 ctx->inputs[radeon_llvm_reg_index_soa(idx + i, 0)] = interp;
5270
5271 }
5272
5273 static void
5274 handle_vs_inputs(struct nir_to_llvm_context *ctx,
5275 struct nir_shader *nir) {
5276 nir_foreach_variable(variable, &nir->inputs)
5277 handle_vs_input_decl(ctx, variable);
5278 }
5279
5280 static void
5281 prepare_interp_optimize(struct nir_to_llvm_context *ctx,
5282 struct nir_shader *nir)
5283 {
5284 if (!ctx->options->key.fs.multisample)
5285 return;
5286
5287 bool uses_center = false;
5288 bool uses_centroid = false;
5289 nir_foreach_variable(variable, &nir->inputs) {
5290 if (glsl_get_base_type(glsl_without_array(variable->type)) != GLSL_TYPE_FLOAT ||
5291 variable->data.sample)
5292 continue;
5293
5294 if (variable->data.centroid)
5295 uses_centroid = true;
5296 else
5297 uses_center = true;
5298 }
5299
5300 if (uses_center && uses_centroid) {
5301 LLVMValueRef sel = LLVMBuildICmp(ctx->builder, LLVMIntSLT, ctx->prim_mask, ctx->ac.i32_0, "");
5302 ctx->persp_centroid = LLVMBuildSelect(ctx->builder, sel, ctx->persp_center, ctx->persp_centroid, "");
5303 ctx->linear_centroid = LLVMBuildSelect(ctx->builder, sel, ctx->linear_center, ctx->linear_centroid, "");
5304 }
5305 }
5306
5307 static void
5308 handle_fs_inputs(struct nir_to_llvm_context *ctx,
5309 struct nir_shader *nir)
5310 {
5311 prepare_interp_optimize(ctx, nir);
5312
5313 nir_foreach_variable(variable, &nir->inputs)
5314 handle_fs_input_decl(ctx, variable);
5315
5316 unsigned index = 0;
5317
5318 if (ctx->shader_info->info.ps.uses_input_attachments ||
5319 ctx->shader_info->info.needs_multiview_view_index)
5320 ctx->input_mask |= 1ull << VARYING_SLOT_LAYER;
5321
5322 for (unsigned i = 0; i < RADEON_LLVM_MAX_INPUTS; ++i) {
5323 LLVMValueRef interp_param;
5324 LLVMValueRef *inputs = ctx->inputs +radeon_llvm_reg_index_soa(i, 0);
5325
5326 if (!(ctx->input_mask & (1ull << i)))
5327 continue;
5328
5329 if (i >= VARYING_SLOT_VAR0 || i == VARYING_SLOT_PNTC ||
5330 i == VARYING_SLOT_PRIMITIVE_ID || i == VARYING_SLOT_LAYER) {
5331 interp_param = *inputs;
5332 interp_fs_input(ctx, index, interp_param, ctx->prim_mask,
5333 inputs);
5334
5335 if (!interp_param)
5336 ctx->shader_info->fs.flat_shaded_mask |= 1u << index;
5337 ++index;
5338 } else if (i == VARYING_SLOT_POS) {
5339 for(int i = 0; i < 3; ++i)
5340 inputs[i] = ctx->abi.frag_pos[i];
5341
5342 inputs[3] = ac_build_fdiv(&ctx->ac, ctx->ac.f32_1,
5343 ctx->abi.frag_pos[3]);
5344 }
5345 }
5346 ctx->shader_info->fs.num_interp = index;
5347 if (ctx->input_mask & (1 << VARYING_SLOT_PNTC))
5348 ctx->shader_info->fs.has_pcoord = true;
5349 if (ctx->input_mask & (1 << VARYING_SLOT_PRIMITIVE_ID))
5350 ctx->shader_info->fs.prim_id_input = true;
5351 if (ctx->input_mask & (1 << VARYING_SLOT_LAYER))
5352 ctx->shader_info->fs.layer_input = true;
5353 ctx->shader_info->fs.input_mask = ctx->input_mask >> VARYING_SLOT_VAR0;
5354
5355 if (ctx->shader_info->info.needs_multiview_view_index)
5356 ctx->view_index = ctx->inputs[radeon_llvm_reg_index_soa(VARYING_SLOT_LAYER, 0)];
5357 }
5358
5359 static LLVMValueRef
5360 ac_build_alloca(struct ac_llvm_context *ac,
5361 LLVMTypeRef type,
5362 const char *name)
5363 {
5364 LLVMBuilderRef builder = ac->builder;
5365 LLVMBasicBlockRef current_block = LLVMGetInsertBlock(builder);
5366 LLVMValueRef function = LLVMGetBasicBlockParent(current_block);
5367 LLVMBasicBlockRef first_block = LLVMGetEntryBasicBlock(function);
5368 LLVMValueRef first_instr = LLVMGetFirstInstruction(first_block);
5369 LLVMBuilderRef first_builder = LLVMCreateBuilderInContext(ac->context);
5370 LLVMValueRef res;
5371
5372 if (first_instr) {
5373 LLVMPositionBuilderBefore(first_builder, first_instr);
5374 } else {
5375 LLVMPositionBuilderAtEnd(first_builder, first_block);
5376 }
5377
5378 res = LLVMBuildAlloca(first_builder, type, name);
5379 LLVMBuildStore(builder, LLVMConstNull(type), res);
5380
5381 LLVMDisposeBuilder(first_builder);
5382
5383 return res;
5384 }
5385
5386 static LLVMValueRef si_build_alloca_undef(struct ac_llvm_context *ac,
5387 LLVMTypeRef type,
5388 const char *name)
5389 {
5390 LLVMValueRef ptr = ac_build_alloca(ac, type, name);
5391 LLVMBuildStore(ac->builder, LLVMGetUndef(type), ptr);
5392 return ptr;
5393 }
5394
5395 static void
5396 scan_shader_output_decl(struct nir_to_llvm_context *ctx,
5397 struct nir_variable *variable,
5398 struct nir_shader *shader,
5399 gl_shader_stage stage)
5400 {
5401 int idx = variable->data.location + variable->data.index;
5402 unsigned attrib_count = glsl_count_attribute_slots(variable->type, false);
5403 uint64_t mask_attribs;
5404
5405 variable->data.driver_location = idx * 4;
5406
5407 /* tess ctrl has it's own load/store paths for outputs */
5408 if (stage == MESA_SHADER_TESS_CTRL)
5409 return;
5410
5411 mask_attribs = ((1ull << attrib_count) - 1) << idx;
5412 if (stage == MESA_SHADER_VERTEX ||
5413 stage == MESA_SHADER_TESS_EVAL ||
5414 stage == MESA_SHADER_GEOMETRY) {
5415 if (idx == VARYING_SLOT_CLIP_DIST0) {
5416 int length = shader->info.clip_distance_array_size +
5417 shader->info.cull_distance_array_size;
5418 if (stage == MESA_SHADER_VERTEX) {
5419 ctx->shader_info->vs.outinfo.clip_dist_mask = (1 << shader->info.clip_distance_array_size) - 1;
5420 ctx->shader_info->vs.outinfo.cull_dist_mask = (1 << shader->info.cull_distance_array_size) - 1;
5421 }
5422 if (stage == MESA_SHADER_TESS_EVAL) {
5423 ctx->shader_info->tes.outinfo.clip_dist_mask = (1 << shader->info.clip_distance_array_size) - 1;
5424 ctx->shader_info->tes.outinfo.cull_dist_mask = (1 << shader->info.cull_distance_array_size) - 1;
5425 }
5426
5427 if (length > 4)
5428 attrib_count = 2;
5429 else
5430 attrib_count = 1;
5431 mask_attribs = 1ull << idx;
5432 }
5433 }
5434
5435 ctx->output_mask |= mask_attribs;
5436 }
5437
5438 static void
5439 handle_shader_output_decl(struct ac_nir_context *ctx,
5440 struct nir_shader *nir,
5441 struct nir_variable *variable)
5442 {
5443 unsigned output_loc = variable->data.driver_location / 4;
5444 unsigned attrib_count = glsl_count_attribute_slots(variable->type, false);
5445
5446 /* tess ctrl has it's own load/store paths for outputs */
5447 if (ctx->stage == MESA_SHADER_TESS_CTRL)
5448 return;
5449
5450 if (ctx->stage == MESA_SHADER_VERTEX ||
5451 ctx->stage == MESA_SHADER_TESS_EVAL ||
5452 ctx->stage == MESA_SHADER_GEOMETRY) {
5453 int idx = variable->data.location + variable->data.index;
5454 if (idx == VARYING_SLOT_CLIP_DIST0) {
5455 int length = nir->info.clip_distance_array_size +
5456 nir->info.cull_distance_array_size;
5457
5458 if (length > 4)
5459 attrib_count = 2;
5460 else
5461 attrib_count = 1;
5462 }
5463 }
5464
5465 for (unsigned i = 0; i < attrib_count; ++i) {
5466 for (unsigned chan = 0; chan < 4; chan++) {
5467 ctx->outputs[radeon_llvm_reg_index_soa(output_loc + i, chan)] =
5468 si_build_alloca_undef(&ctx->ac, ctx->ac.f32, "");
5469 }
5470 }
5471 }
5472
5473 static LLVMTypeRef
5474 glsl_base_to_llvm_type(struct nir_to_llvm_context *ctx,
5475 enum glsl_base_type type)
5476 {
5477 switch (type) {
5478 case GLSL_TYPE_INT:
5479 case GLSL_TYPE_UINT:
5480 case GLSL_TYPE_BOOL:
5481 case GLSL_TYPE_SUBROUTINE:
5482 return ctx->ac.i32;
5483 case GLSL_TYPE_FLOAT: /* TODO handle mediump */
5484 return ctx->ac.f32;
5485 case GLSL_TYPE_INT64:
5486 case GLSL_TYPE_UINT64:
5487 return ctx->ac.i64;
5488 case GLSL_TYPE_DOUBLE:
5489 return ctx->ac.f64;
5490 default:
5491 unreachable("unknown GLSL type");
5492 }
5493 }
5494
5495 static LLVMTypeRef
5496 glsl_to_llvm_type(struct nir_to_llvm_context *ctx,
5497 const struct glsl_type *type)
5498 {
5499 if (glsl_type_is_scalar(type)) {
5500 return glsl_base_to_llvm_type(ctx, glsl_get_base_type(type));
5501 }
5502
5503 if (glsl_type_is_vector(type)) {
5504 return LLVMVectorType(
5505 glsl_base_to_llvm_type(ctx, glsl_get_base_type(type)),
5506 glsl_get_vector_elements(type));
5507 }
5508
5509 if (glsl_type_is_matrix(type)) {
5510 return LLVMArrayType(
5511 glsl_to_llvm_type(ctx, glsl_get_column_type(type)),
5512 glsl_get_matrix_columns(type));
5513 }
5514
5515 if (glsl_type_is_array(type)) {
5516 return LLVMArrayType(
5517 glsl_to_llvm_type(ctx, glsl_get_array_element(type)),
5518 glsl_get_length(type));
5519 }
5520
5521 assert(glsl_type_is_struct(type));
5522
5523 LLVMTypeRef member_types[glsl_get_length(type)];
5524
5525 for (unsigned i = 0; i < glsl_get_length(type); i++) {
5526 member_types[i] =
5527 glsl_to_llvm_type(ctx,
5528 glsl_get_struct_field(type, i));
5529 }
5530
5531 return LLVMStructTypeInContext(ctx->context, member_types,
5532 glsl_get_length(type), false);
5533 }
5534
5535 static void
5536 setup_locals(struct ac_nir_context *ctx,
5537 struct nir_function *func)
5538 {
5539 int i, j;
5540 ctx->num_locals = 0;
5541 nir_foreach_variable(variable, &func->impl->locals) {
5542 unsigned attrib_count = glsl_count_attribute_slots(variable->type, false);
5543 variable->data.driver_location = ctx->num_locals * 4;
5544 ctx->num_locals += attrib_count;
5545 }
5546 ctx->locals = malloc(4 * ctx->num_locals * sizeof(LLVMValueRef));
5547 if (!ctx->locals)
5548 return;
5549
5550 for (i = 0; i < ctx->num_locals; i++) {
5551 for (j = 0; j < 4; j++) {
5552 ctx->locals[i * 4 + j] =
5553 si_build_alloca_undef(&ctx->ac, ctx->ac.f32, "temp");
5554 }
5555 }
5556 }
5557
5558 static void
5559 setup_shared(struct ac_nir_context *ctx,
5560 struct nir_shader *nir)
5561 {
5562 nir_foreach_variable(variable, &nir->shared) {
5563 LLVMValueRef shared =
5564 LLVMAddGlobalInAddressSpace(
5565 ctx->ac.module, glsl_to_llvm_type(ctx->nctx, variable->type),
5566 variable->name ? variable->name : "",
5567 LOCAL_ADDR_SPACE);
5568 _mesa_hash_table_insert(ctx->vars, variable, shared);
5569 }
5570 }
5571
5572 static LLVMValueRef
5573 emit_float_saturate(struct ac_llvm_context *ctx, LLVMValueRef v, float lo, float hi)
5574 {
5575 v = ac_to_float(ctx, v);
5576 v = emit_intrin_2f_param(ctx, "llvm.maxnum", ctx->f32, v, LLVMConstReal(ctx->f32, lo));
5577 return emit_intrin_2f_param(ctx, "llvm.minnum", ctx->f32, v, LLVMConstReal(ctx->f32, hi));
5578 }
5579
5580
5581 static LLVMValueRef emit_pack_int16(struct nir_to_llvm_context *ctx,
5582 LLVMValueRef src0, LLVMValueRef src1)
5583 {
5584 LLVMValueRef const16 = LLVMConstInt(ctx->ac.i32, 16, false);
5585 LLVMValueRef comp[2];
5586
5587 comp[0] = LLVMBuildAnd(ctx->builder, src0, LLVMConstInt(ctx->ac.i32, 65535, 0), "");
5588 comp[1] = LLVMBuildAnd(ctx->builder, src1, LLVMConstInt(ctx->ac.i32, 65535, 0), "");
5589 comp[1] = LLVMBuildShl(ctx->builder, comp[1], const16, "");
5590 return LLVMBuildOr(ctx->builder, comp[0], comp[1], "");
5591 }
5592
5593 /* Initialize arguments for the shader export intrinsic */
5594 static void
5595 si_llvm_init_export_args(struct nir_to_llvm_context *ctx,
5596 LLVMValueRef *values,
5597 unsigned target,
5598 struct ac_export_args *args)
5599 {
5600 /* Default is 0xf. Adjusted below depending on the format. */
5601 args->enabled_channels = 0xf;
5602
5603 /* Specify whether the EXEC mask represents the valid mask */
5604 args->valid_mask = 0;
5605
5606 /* Specify whether this is the last export */
5607 args->done = 0;
5608
5609 /* Specify the target we are exporting */
5610 args->target = target;
5611
5612 args->compr = false;
5613 args->out[0] = LLVMGetUndef(ctx->ac.f32);
5614 args->out[1] = LLVMGetUndef(ctx->ac.f32);
5615 args->out[2] = LLVMGetUndef(ctx->ac.f32);
5616 args->out[3] = LLVMGetUndef(ctx->ac.f32);
5617
5618 if (!values)
5619 return;
5620
5621 if (ctx->stage == MESA_SHADER_FRAGMENT && target >= V_008DFC_SQ_EXP_MRT) {
5622 LLVMValueRef val[4];
5623 unsigned index = target - V_008DFC_SQ_EXP_MRT;
5624 unsigned col_format = (ctx->options->key.fs.col_format >> (4 * index)) & 0xf;
5625 bool is_int8 = (ctx->options->key.fs.is_int8 >> index) & 1;
5626 bool is_int10 = (ctx->options->key.fs.is_int10 >> index) & 1;
5627
5628 switch(col_format) {
5629 case V_028714_SPI_SHADER_ZERO:
5630 args->enabled_channels = 0; /* writemask */
5631 args->target = V_008DFC_SQ_EXP_NULL;
5632 break;
5633
5634 case V_028714_SPI_SHADER_32_R:
5635 args->enabled_channels = 1;
5636 args->out[0] = values[0];
5637 break;
5638
5639 case V_028714_SPI_SHADER_32_GR:
5640 args->enabled_channels = 0x3;
5641 args->out[0] = values[0];
5642 args->out[1] = values[1];
5643 break;
5644
5645 case V_028714_SPI_SHADER_32_AR:
5646 args->enabled_channels = 0x9;
5647 args->out[0] = values[0];
5648 args->out[3] = values[3];
5649 break;
5650
5651 case V_028714_SPI_SHADER_FP16_ABGR:
5652 args->compr = 1;
5653
5654 for (unsigned chan = 0; chan < 2; chan++) {
5655 LLVMValueRef pack_args[2] = {
5656 values[2 * chan],
5657 values[2 * chan + 1]
5658 };
5659 LLVMValueRef packed;
5660
5661 packed = ac_build_cvt_pkrtz_f16(&ctx->ac, pack_args);
5662 args->out[chan] = packed;
5663 }
5664 break;
5665
5666 case V_028714_SPI_SHADER_UNORM16_ABGR:
5667 for (unsigned chan = 0; chan < 4; chan++) {
5668 val[chan] = ac_build_clamp(&ctx->ac, values[chan]);
5669 val[chan] = LLVMBuildFMul(ctx->builder, val[chan],
5670 LLVMConstReal(ctx->ac.f32, 65535), "");
5671 val[chan] = LLVMBuildFAdd(ctx->builder, val[chan],
5672 LLVMConstReal(ctx->ac.f32, 0.5), "");
5673 val[chan] = LLVMBuildFPToUI(ctx->builder, val[chan],
5674 ctx->ac.i32, "");
5675 }
5676
5677 args->compr = 1;
5678 args->out[0] = emit_pack_int16(ctx, val[0], val[1]);
5679 args->out[1] = emit_pack_int16(ctx, val[2], val[3]);
5680 break;
5681
5682 case V_028714_SPI_SHADER_SNORM16_ABGR:
5683 for (unsigned chan = 0; chan < 4; chan++) {
5684 val[chan] = emit_float_saturate(&ctx->ac, values[chan], -1, 1);
5685 val[chan] = LLVMBuildFMul(ctx->builder, val[chan],
5686 LLVMConstReal(ctx->ac.f32, 32767), "");
5687
5688 /* If positive, add 0.5, else add -0.5. */
5689 val[chan] = LLVMBuildFAdd(ctx->builder, val[chan],
5690 LLVMBuildSelect(ctx->builder,
5691 LLVMBuildFCmp(ctx->builder, LLVMRealOGE,
5692 val[chan], ctx->ac.f32_0, ""),
5693 LLVMConstReal(ctx->ac.f32, 0.5),
5694 LLVMConstReal(ctx->ac.f32, -0.5), ""), "");
5695 val[chan] = LLVMBuildFPToSI(ctx->builder, val[chan], ctx->ac.i32, "");
5696 }
5697
5698 args->compr = 1;
5699 args->out[0] = emit_pack_int16(ctx, val[0], val[1]);
5700 args->out[1] = emit_pack_int16(ctx, val[2], val[3]);
5701 break;
5702
5703 case V_028714_SPI_SHADER_UINT16_ABGR: {
5704 LLVMValueRef max_rgb = LLVMConstInt(ctx->ac.i32,
5705 is_int8 ? 255 : is_int10 ? 1023 : 65535, 0);
5706 LLVMValueRef max_alpha = !is_int10 ? max_rgb : LLVMConstInt(ctx->ac.i32, 3, 0);
5707
5708 for (unsigned chan = 0; chan < 4; chan++) {
5709 val[chan] = ac_to_integer(&ctx->ac, values[chan]);
5710 val[chan] = emit_minmax_int(&ctx->ac, LLVMIntULT, val[chan], chan == 3 ? max_alpha : max_rgb);
5711 }
5712
5713 args->compr = 1;
5714 args->out[0] = emit_pack_int16(ctx, val[0], val[1]);
5715 args->out[1] = emit_pack_int16(ctx, val[2], val[3]);
5716 break;
5717 }
5718
5719 case V_028714_SPI_SHADER_SINT16_ABGR: {
5720 LLVMValueRef max_rgb = LLVMConstInt(ctx->ac.i32,
5721 is_int8 ? 127 : is_int10 ? 511 : 32767, 0);
5722 LLVMValueRef min_rgb = LLVMConstInt(ctx->ac.i32,
5723 is_int8 ? -128 : is_int10 ? -512 : -32768, 0);
5724 LLVMValueRef max_alpha = !is_int10 ? max_rgb : ctx->ac.i32_1;
5725 LLVMValueRef min_alpha = !is_int10 ? min_rgb : LLVMConstInt(ctx->ac.i32, -2, 0);
5726
5727 /* Clamp. */
5728 for (unsigned chan = 0; chan < 4; chan++) {
5729 val[chan] = ac_to_integer(&ctx->ac, values[chan]);
5730 val[chan] = emit_minmax_int(&ctx->ac, LLVMIntSLT, val[chan], chan == 3 ? max_alpha : max_rgb);
5731 val[chan] = emit_minmax_int(&ctx->ac, LLVMIntSGT, val[chan], chan == 3 ? min_alpha : min_rgb);
5732 }
5733
5734 args->compr = 1;
5735 args->out[0] = emit_pack_int16(ctx, val[0], val[1]);
5736 args->out[1] = emit_pack_int16(ctx, val[2], val[3]);
5737 break;
5738 }
5739
5740 default:
5741 case V_028714_SPI_SHADER_32_ABGR:
5742 memcpy(&args->out[0], values, sizeof(values[0]) * 4);
5743 break;
5744 }
5745 } else
5746 memcpy(&args->out[0], values, sizeof(values[0]) * 4);
5747
5748 for (unsigned i = 0; i < 4; ++i)
5749 args->out[i] = ac_to_float(&ctx->ac, args->out[i]);
5750 }
5751
5752 static void
5753 handle_vs_outputs_post(struct nir_to_llvm_context *ctx,
5754 bool export_prim_id,
5755 struct ac_vs_output_info *outinfo)
5756 {
5757 uint32_t param_count = 0;
5758 unsigned target;
5759 unsigned pos_idx, num_pos_exports = 0;
5760 struct ac_export_args args, pos_args[4] = {};
5761 LLVMValueRef psize_value = NULL, layer_value = NULL, viewport_index_value = NULL;
5762 int i;
5763
5764 if (ctx->options->key.has_multiview_view_index) {
5765 LLVMValueRef* tmp_out = &ctx->nir->outputs[radeon_llvm_reg_index_soa(VARYING_SLOT_LAYER, 0)];
5766 if(!*tmp_out) {
5767 for(unsigned i = 0; i < 4; ++i)
5768 ctx->nir->outputs[radeon_llvm_reg_index_soa(VARYING_SLOT_LAYER, i)] =
5769 si_build_alloca_undef(&ctx->ac, ctx->ac.f32, "");
5770 }
5771
5772 LLVMBuildStore(ctx->builder, ac_to_float(&ctx->ac, ctx->view_index), *tmp_out);
5773 ctx->output_mask |= 1ull << VARYING_SLOT_LAYER;
5774 }
5775
5776 memset(outinfo->vs_output_param_offset, AC_EXP_PARAM_UNDEFINED,
5777 sizeof(outinfo->vs_output_param_offset));
5778
5779 if (ctx->output_mask & (1ull << VARYING_SLOT_CLIP_DIST0)) {
5780 LLVMValueRef slots[8];
5781 unsigned j;
5782
5783 if (outinfo->cull_dist_mask)
5784 outinfo->cull_dist_mask <<= ctx->num_output_clips;
5785
5786 i = VARYING_SLOT_CLIP_DIST0;
5787 for (j = 0; j < ctx->num_output_clips + ctx->num_output_culls; j++)
5788 slots[j] = ac_to_float(&ctx->ac, LLVMBuildLoad(ctx->builder,
5789 ctx->nir->outputs[radeon_llvm_reg_index_soa(i, j)], ""));
5790
5791 for (i = ctx->num_output_clips + ctx->num_output_culls; i < 8; i++)
5792 slots[i] = LLVMGetUndef(ctx->ac.f32);
5793
5794 if (ctx->num_output_clips + ctx->num_output_culls > 4) {
5795 target = V_008DFC_SQ_EXP_POS + 3;
5796 si_llvm_init_export_args(ctx, &slots[4], target, &args);
5797 memcpy(&pos_args[target - V_008DFC_SQ_EXP_POS],
5798 &args, sizeof(args));
5799 }
5800
5801 target = V_008DFC_SQ_EXP_POS + 2;
5802 si_llvm_init_export_args(ctx, &slots[0], target, &args);
5803 memcpy(&pos_args[target - V_008DFC_SQ_EXP_POS],
5804 &args, sizeof(args));
5805
5806 }
5807
5808 LLVMValueRef pos_values[4] = {ctx->ac.f32_0, ctx->ac.f32_0, ctx->ac.f32_0, ctx->ac.f32_1};
5809 if (ctx->output_mask & (1ull << VARYING_SLOT_POS)) {
5810 for (unsigned j = 0; j < 4; j++)
5811 pos_values[j] = LLVMBuildLoad(ctx->builder,
5812 ctx->nir->outputs[radeon_llvm_reg_index_soa(VARYING_SLOT_POS, j)], "");
5813 }
5814 si_llvm_init_export_args(ctx, pos_values, V_008DFC_SQ_EXP_POS, &pos_args[0]);
5815
5816 if (ctx->output_mask & (1ull << VARYING_SLOT_PSIZ)) {
5817 outinfo->writes_pointsize = true;
5818 psize_value = LLVMBuildLoad(ctx->builder,
5819 ctx->nir->outputs[radeon_llvm_reg_index_soa(VARYING_SLOT_PSIZ, 0)], "");
5820 }
5821
5822 if (ctx->output_mask & (1ull << VARYING_SLOT_LAYER)) {
5823 outinfo->writes_layer = true;
5824 layer_value = LLVMBuildLoad(ctx->builder,
5825 ctx->nir->outputs[radeon_llvm_reg_index_soa(VARYING_SLOT_LAYER, 0)], "");
5826 }
5827
5828 if (ctx->output_mask & (1ull << VARYING_SLOT_VIEWPORT)) {
5829 outinfo->writes_viewport_index = true;
5830 viewport_index_value = LLVMBuildLoad(ctx->builder,
5831 ctx->nir->outputs[radeon_llvm_reg_index_soa(VARYING_SLOT_VIEWPORT, 0)], "");
5832 }
5833
5834 if (outinfo->writes_pointsize ||
5835 outinfo->writes_layer ||
5836 outinfo->writes_viewport_index) {
5837 pos_args[1].enabled_channels = ((outinfo->writes_pointsize == true ? 1 : 0) |
5838 (outinfo->writes_layer == true ? 4 : 0));
5839 pos_args[1].valid_mask = 0;
5840 pos_args[1].done = 0;
5841 pos_args[1].target = V_008DFC_SQ_EXP_POS + 1;
5842 pos_args[1].compr = 0;
5843 pos_args[1].out[0] = ctx->ac.f32_0; /* X */
5844 pos_args[1].out[1] = ctx->ac.f32_0; /* Y */
5845 pos_args[1].out[2] = ctx->ac.f32_0; /* Z */
5846 pos_args[1].out[3] = ctx->ac.f32_0; /* W */
5847
5848 if (outinfo->writes_pointsize == true)
5849 pos_args[1].out[0] = psize_value;
5850 if (outinfo->writes_layer == true)
5851 pos_args[1].out[2] = layer_value;
5852 if (outinfo->writes_viewport_index == true) {
5853 if (ctx->options->chip_class >= GFX9) {
5854 /* GFX9 has the layer in out.z[10:0] and the viewport
5855 * index in out.z[19:16].
5856 */
5857 LLVMValueRef v = viewport_index_value;
5858 v = ac_to_integer(&ctx->ac, v);
5859 v = LLVMBuildShl(ctx->builder, v,
5860 LLVMConstInt(ctx->ac.i32, 16, false),
5861 "");
5862 v = LLVMBuildOr(ctx->builder, v,
5863 ac_to_integer(&ctx->ac, pos_args[1].out[2]), "");
5864
5865 pos_args[1].out[2] = ac_to_float(&ctx->ac, v);
5866 pos_args[1].enabled_channels |= 1 << 2;
5867 } else {
5868 pos_args[1].out[3] = viewport_index_value;
5869 pos_args[1].enabled_channels |= 1 << 3;
5870 }
5871 }
5872 }
5873 for (i = 0; i < 4; i++) {
5874 if (pos_args[i].out[0])
5875 num_pos_exports++;
5876 }
5877
5878 pos_idx = 0;
5879 for (i = 0; i < 4; i++) {
5880 if (!pos_args[i].out[0])
5881 continue;
5882
5883 /* Specify the target we are exporting */
5884 pos_args[i].target = V_008DFC_SQ_EXP_POS + pos_idx++;
5885 if (pos_idx == num_pos_exports)
5886 pos_args[i].done = 1;
5887 ac_build_export(&ctx->ac, &pos_args[i]);
5888 }
5889
5890 for (unsigned i = 0; i < RADEON_LLVM_MAX_OUTPUTS; ++i) {
5891 LLVMValueRef values[4];
5892 if (!(ctx->output_mask & (1ull << i)))
5893 continue;
5894
5895 for (unsigned j = 0; j < 4; j++)
5896 values[j] = ac_to_float(&ctx->ac, LLVMBuildLoad(ctx->builder,
5897 ctx->nir->outputs[radeon_llvm_reg_index_soa(i, j)], ""));
5898
5899 if (i == VARYING_SLOT_LAYER) {
5900 target = V_008DFC_SQ_EXP_PARAM + param_count;
5901 outinfo->vs_output_param_offset[VARYING_SLOT_LAYER] = param_count;
5902 param_count++;
5903 } else if (i == VARYING_SLOT_PRIMITIVE_ID) {
5904 target = V_008DFC_SQ_EXP_PARAM + param_count;
5905 outinfo->vs_output_param_offset[VARYING_SLOT_PRIMITIVE_ID] = param_count;
5906 param_count++;
5907 } else if (i >= VARYING_SLOT_VAR0) {
5908 outinfo->export_mask |= 1u << (i - VARYING_SLOT_VAR0);
5909 target = V_008DFC_SQ_EXP_PARAM + param_count;
5910 outinfo->vs_output_param_offset[i] = param_count;
5911 param_count++;
5912 } else
5913 continue;
5914
5915 si_llvm_init_export_args(ctx, values, target, &args);
5916
5917 if (target >= V_008DFC_SQ_EXP_POS &&
5918 target <= (V_008DFC_SQ_EXP_POS + 3)) {
5919 memcpy(&pos_args[target - V_008DFC_SQ_EXP_POS],
5920 &args, sizeof(args));
5921 } else {
5922 ac_build_export(&ctx->ac, &args);
5923 }
5924 }
5925
5926 if (export_prim_id) {
5927 LLVMValueRef values[4];
5928 target = V_008DFC_SQ_EXP_PARAM + param_count;
5929 outinfo->vs_output_param_offset[VARYING_SLOT_PRIMITIVE_ID] = param_count;
5930 param_count++;
5931
5932 values[0] = ctx->vs_prim_id;
5933 ctx->shader_info->vs.vgpr_comp_cnt = MAX2(2,
5934 ctx->shader_info->vs.vgpr_comp_cnt);
5935 for (unsigned j = 1; j < 4; j++)
5936 values[j] = ctx->ac.f32_0;
5937 si_llvm_init_export_args(ctx, values, target, &args);
5938 ac_build_export(&ctx->ac, &args);
5939 outinfo->export_prim_id = true;
5940 }
5941
5942 outinfo->pos_exports = num_pos_exports;
5943 outinfo->param_exports = param_count;
5944 }
5945
5946 static void
5947 handle_es_outputs_post(struct nir_to_llvm_context *ctx,
5948 struct ac_es_output_info *outinfo)
5949 {
5950 int j;
5951 uint64_t max_output_written = 0;
5952 LLVMValueRef lds_base = NULL;
5953
5954 for (unsigned i = 0; i < RADEON_LLVM_MAX_OUTPUTS; ++i) {
5955 int param_index;
5956 int length = 4;
5957
5958 if (!(ctx->output_mask & (1ull << i)))
5959 continue;
5960
5961 if (i == VARYING_SLOT_CLIP_DIST0)
5962 length = ctx->num_output_clips + ctx->num_output_culls;
5963
5964 param_index = shader_io_get_unique_index(i);
5965
5966 max_output_written = MAX2(param_index + (length > 4), max_output_written);
5967 }
5968
5969 outinfo->esgs_itemsize = (max_output_written + 1) * 16;
5970
5971 if (ctx->ac.chip_class >= GFX9) {
5972 unsigned itemsize_dw = outinfo->esgs_itemsize / 4;
5973 LLVMValueRef vertex_idx = ac_get_thread_id(&ctx->ac);
5974 LLVMValueRef wave_idx = ac_build_bfe(&ctx->ac, ctx->merged_wave_info,
5975 LLVMConstInt(ctx->ac.i32, 24, false),
5976 LLVMConstInt(ctx->ac.i32, 4, false), false);
5977 vertex_idx = LLVMBuildOr(ctx->ac.builder, vertex_idx,
5978 LLVMBuildMul(ctx->ac.builder, wave_idx,
5979 LLVMConstInt(ctx->ac.i32, 64, false), ""), "");
5980 lds_base = LLVMBuildMul(ctx->ac.builder, vertex_idx,
5981 LLVMConstInt(ctx->ac.i32, itemsize_dw, 0), "");
5982 }
5983
5984 for (unsigned i = 0; i < RADEON_LLVM_MAX_OUTPUTS; ++i) {
5985 LLVMValueRef dw_addr;
5986 LLVMValueRef *out_ptr = &ctx->nir->outputs[i * 4];
5987 int param_index;
5988 int length = 4;
5989
5990 if (!(ctx->output_mask & (1ull << i)))
5991 continue;
5992
5993 if (i == VARYING_SLOT_CLIP_DIST0)
5994 length = ctx->num_output_clips + ctx->num_output_culls;
5995
5996 param_index = shader_io_get_unique_index(i);
5997
5998 if (lds_base) {
5999 dw_addr = LLVMBuildAdd(ctx->builder, lds_base,
6000 LLVMConstInt(ctx->ac.i32, param_index * 4, false),
6001 "");
6002 }
6003 for (j = 0; j < length; j++) {
6004 LLVMValueRef out_val = LLVMBuildLoad(ctx->builder, out_ptr[j], "");
6005 out_val = LLVMBuildBitCast(ctx->builder, out_val, ctx->ac.i32, "");
6006
6007 if (ctx->ac.chip_class >= GFX9) {
6008 ac_lds_store(&ctx->ac, dw_addr,
6009 LLVMBuildLoad(ctx->builder, out_ptr[j], ""));
6010 dw_addr = LLVMBuildAdd(ctx->builder, dw_addr, ctx->ac.i32_1, "");
6011 } else {
6012 ac_build_buffer_store_dword(&ctx->ac,
6013 ctx->esgs_ring,
6014 out_val, 1,
6015 NULL, ctx->es2gs_offset,
6016 (4 * param_index + j) * 4,
6017 1, 1, true, true);
6018 }
6019 }
6020 }
6021 }
6022
6023 static void
6024 handle_ls_outputs_post(struct nir_to_llvm_context *ctx)
6025 {
6026 LLVMValueRef vertex_id = ctx->rel_auto_id;
6027 LLVMValueRef vertex_dw_stride = unpack_param(&ctx->ac, ctx->ls_out_layout, 13, 8);
6028 LLVMValueRef base_dw_addr = LLVMBuildMul(ctx->builder, vertex_id,
6029 vertex_dw_stride, "");
6030
6031 for (unsigned i = 0; i < RADEON_LLVM_MAX_OUTPUTS; ++i) {
6032 LLVMValueRef *out_ptr = &ctx->nir->outputs[i * 4];
6033 int length = 4;
6034
6035 if (!(ctx->output_mask & (1ull << i)))
6036 continue;
6037
6038 if (i == VARYING_SLOT_CLIP_DIST0)
6039 length = ctx->num_output_clips + ctx->num_output_culls;
6040 int param = shader_io_get_unique_index(i);
6041 mark_tess_output(ctx, false, param);
6042 if (length > 4)
6043 mark_tess_output(ctx, false, param + 1);
6044 LLVMValueRef dw_addr = LLVMBuildAdd(ctx->builder, base_dw_addr,
6045 LLVMConstInt(ctx->ac.i32, param * 4, false),
6046 "");
6047 for (unsigned j = 0; j < length; j++) {
6048 ac_lds_store(&ctx->ac, dw_addr,
6049 LLVMBuildLoad(ctx->builder, out_ptr[j], ""));
6050 dw_addr = LLVMBuildAdd(ctx->builder, dw_addr, ctx->ac.i32_1, "");
6051 }
6052 }
6053 }
6054
6055 struct ac_build_if_state
6056 {
6057 struct nir_to_llvm_context *ctx;
6058 LLVMValueRef condition;
6059 LLVMBasicBlockRef entry_block;
6060 LLVMBasicBlockRef true_block;
6061 LLVMBasicBlockRef false_block;
6062 LLVMBasicBlockRef merge_block;
6063 };
6064
6065 static LLVMBasicBlockRef
6066 ac_build_insert_new_block(struct nir_to_llvm_context *ctx, const char *name)
6067 {
6068 LLVMBasicBlockRef current_block;
6069 LLVMBasicBlockRef next_block;
6070 LLVMBasicBlockRef new_block;
6071
6072 /* get current basic block */
6073 current_block = LLVMGetInsertBlock(ctx->builder);
6074
6075 /* chqeck if there's another block after this one */
6076 next_block = LLVMGetNextBasicBlock(current_block);
6077 if (next_block) {
6078 /* insert the new block before the next block */
6079 new_block = LLVMInsertBasicBlockInContext(ctx->context, next_block, name);
6080 }
6081 else {
6082 /* append new block after current block */
6083 LLVMValueRef function = LLVMGetBasicBlockParent(current_block);
6084 new_block = LLVMAppendBasicBlockInContext(ctx->context, function, name);
6085 }
6086 return new_block;
6087 }
6088
6089 static void
6090 ac_nir_build_if(struct ac_build_if_state *ifthen,
6091 struct nir_to_llvm_context *ctx,
6092 LLVMValueRef condition)
6093 {
6094 LLVMBasicBlockRef block = LLVMGetInsertBlock(ctx->builder);
6095
6096 memset(ifthen, 0, sizeof *ifthen);
6097 ifthen->ctx = ctx;
6098 ifthen->condition = condition;
6099 ifthen->entry_block = block;
6100
6101 /* create endif/merge basic block for the phi functions */
6102 ifthen->merge_block = ac_build_insert_new_block(ctx, "endif-block");
6103
6104 /* create/insert true_block before merge_block */
6105 ifthen->true_block =
6106 LLVMInsertBasicBlockInContext(ctx->context,
6107 ifthen->merge_block,
6108 "if-true-block");
6109
6110 /* successive code goes into the true block */
6111 LLVMPositionBuilderAtEnd(ctx->builder, ifthen->true_block);
6112 }
6113
6114 /**
6115 * End a conditional.
6116 */
6117 static void
6118 ac_nir_build_endif(struct ac_build_if_state *ifthen)
6119 {
6120 LLVMBuilderRef builder = ifthen->ctx->builder;
6121
6122 /* Insert branch to the merge block from current block */
6123 LLVMBuildBr(builder, ifthen->merge_block);
6124
6125 /*
6126 * Now patch in the various branch instructions.
6127 */
6128
6129 /* Insert the conditional branch instruction at the end of entry_block */
6130 LLVMPositionBuilderAtEnd(builder, ifthen->entry_block);
6131 if (ifthen->false_block) {
6132 /* we have an else clause */
6133 LLVMBuildCondBr(builder, ifthen->condition,
6134 ifthen->true_block, ifthen->false_block);
6135 }
6136 else {
6137 /* no else clause */
6138 LLVMBuildCondBr(builder, ifthen->condition,
6139 ifthen->true_block, ifthen->merge_block);
6140 }
6141
6142 /* Resume building code at end of the ifthen->merge_block */
6143 LLVMPositionBuilderAtEnd(builder, ifthen->merge_block);
6144 }
6145
6146 static void
6147 write_tess_factors(struct nir_to_llvm_context *ctx)
6148 {
6149 unsigned stride, outer_comps, inner_comps;
6150 struct ac_build_if_state if_ctx, inner_if_ctx;
6151 LLVMValueRef invocation_id = unpack_param(&ctx->ac, ctx->abi.tcs_rel_ids, 8, 5);
6152 LLVMValueRef rel_patch_id = unpack_param(&ctx->ac, ctx->abi.tcs_rel_ids, 0, 8);
6153 unsigned tess_inner_index, tess_outer_index;
6154 LLVMValueRef lds_base, lds_inner, lds_outer, byteoffset, buffer;
6155 LLVMValueRef out[6], vec0, vec1, tf_base, inner[4], outer[4];
6156 int i;
6157 emit_barrier(ctx);
6158
6159 switch (ctx->options->key.tcs.primitive_mode) {
6160 case GL_ISOLINES:
6161 stride = 2;
6162 outer_comps = 2;
6163 inner_comps = 0;
6164 break;
6165 case GL_TRIANGLES:
6166 stride = 4;
6167 outer_comps = 3;
6168 inner_comps = 1;
6169 break;
6170 case GL_QUADS:
6171 stride = 6;
6172 outer_comps = 4;
6173 inner_comps = 2;
6174 break;
6175 default:
6176 return;
6177 }
6178
6179 ac_nir_build_if(&if_ctx, ctx,
6180 LLVMBuildICmp(ctx->builder, LLVMIntEQ,
6181 invocation_id, ctx->ac.i32_0, ""));
6182
6183 tess_inner_index = shader_io_get_unique_index(VARYING_SLOT_TESS_LEVEL_INNER);
6184 tess_outer_index = shader_io_get_unique_index(VARYING_SLOT_TESS_LEVEL_OUTER);
6185
6186 mark_tess_output(ctx, true, tess_inner_index);
6187 mark_tess_output(ctx, true, tess_outer_index);
6188 lds_base = get_tcs_out_current_patch_data_offset(ctx);
6189 lds_inner = LLVMBuildAdd(ctx->builder, lds_base,
6190 LLVMConstInt(ctx->ac.i32, tess_inner_index * 4, false), "");
6191 lds_outer = LLVMBuildAdd(ctx->builder, lds_base,
6192 LLVMConstInt(ctx->ac.i32, tess_outer_index * 4, false), "");
6193
6194 for (i = 0; i < 4; i++) {
6195 inner[i] = LLVMGetUndef(ctx->ac.i32);
6196 outer[i] = LLVMGetUndef(ctx->ac.i32);
6197 }
6198
6199 // LINES reverseal
6200 if (ctx->options->key.tcs.primitive_mode == GL_ISOLINES) {
6201 outer[0] = out[1] = ac_lds_load(&ctx->ac, lds_outer);
6202 lds_outer = LLVMBuildAdd(ctx->builder, lds_outer,
6203 ctx->ac.i32_1, "");
6204 outer[1] = out[0] = ac_lds_load(&ctx->ac, lds_outer);
6205 } else {
6206 for (i = 0; i < outer_comps; i++) {
6207 outer[i] = out[i] =
6208 ac_lds_load(&ctx->ac, lds_outer);
6209 lds_outer = LLVMBuildAdd(ctx->builder, lds_outer,
6210 ctx->ac.i32_1, "");
6211 }
6212 for (i = 0; i < inner_comps; i++) {
6213 inner[i] = out[outer_comps+i] =
6214 ac_lds_load(&ctx->ac, lds_inner);
6215 lds_inner = LLVMBuildAdd(ctx->builder, lds_inner,
6216 ctx->ac.i32_1, "");
6217 }
6218 }
6219
6220 /* Convert the outputs to vectors for stores. */
6221 vec0 = ac_build_gather_values(&ctx->ac, out, MIN2(stride, 4));
6222 vec1 = NULL;
6223
6224 if (stride > 4)
6225 vec1 = ac_build_gather_values(&ctx->ac, out + 4, stride - 4);
6226
6227
6228 buffer = ctx->hs_ring_tess_factor;
6229 tf_base = ctx->tess_factor_offset;
6230 byteoffset = LLVMBuildMul(ctx->builder, rel_patch_id,
6231 LLVMConstInt(ctx->ac.i32, 4 * stride, false), "");
6232 unsigned tf_offset = 0;
6233
6234 if (ctx->options->chip_class <= VI) {
6235 ac_nir_build_if(&inner_if_ctx, ctx,
6236 LLVMBuildICmp(ctx->builder, LLVMIntEQ,
6237 rel_patch_id, ctx->ac.i32_0, ""));
6238
6239 /* Store the dynamic HS control word. */
6240 ac_build_buffer_store_dword(&ctx->ac, buffer,
6241 LLVMConstInt(ctx->ac.i32, 0x80000000, false),
6242 1, ctx->ac.i32_0, tf_base,
6243 0, 1, 0, true, false);
6244 tf_offset += 4;
6245
6246 ac_nir_build_endif(&inner_if_ctx);
6247 }
6248
6249 /* Store the tessellation factors. */
6250 ac_build_buffer_store_dword(&ctx->ac, buffer, vec0,
6251 MIN2(stride, 4), byteoffset, tf_base,
6252 tf_offset, 1, 0, true, false);
6253 if (vec1)
6254 ac_build_buffer_store_dword(&ctx->ac, buffer, vec1,
6255 stride - 4, byteoffset, tf_base,
6256 16 + tf_offset, 1, 0, true, false);
6257
6258 //store to offchip for TES to read - only if TES reads them
6259 if (ctx->options->key.tcs.tes_reads_tess_factors) {
6260 LLVMValueRef inner_vec, outer_vec, tf_outer_offset;
6261 LLVMValueRef tf_inner_offset;
6262 unsigned param_outer, param_inner;
6263
6264 param_outer = shader_io_get_unique_index(VARYING_SLOT_TESS_LEVEL_OUTER);
6265 tf_outer_offset = get_tcs_tes_buffer_address(ctx, NULL,
6266 LLVMConstInt(ctx->ac.i32, param_outer, 0));
6267
6268 outer_vec = ac_build_gather_values(&ctx->ac, outer,
6269 util_next_power_of_two(outer_comps));
6270
6271 ac_build_buffer_store_dword(&ctx->ac, ctx->hs_ring_tess_offchip, outer_vec,
6272 outer_comps, tf_outer_offset,
6273 ctx->oc_lds, 0, 1, 0, true, false);
6274 if (inner_comps) {
6275 param_inner = shader_io_get_unique_index(VARYING_SLOT_TESS_LEVEL_INNER);
6276 tf_inner_offset = get_tcs_tes_buffer_address(ctx, NULL,
6277 LLVMConstInt(ctx->ac.i32, param_inner, 0));
6278
6279 inner_vec = inner_comps == 1 ? inner[0] :
6280 ac_build_gather_values(&ctx->ac, inner, inner_comps);
6281 ac_build_buffer_store_dword(&ctx->ac, ctx->hs_ring_tess_offchip, inner_vec,
6282 inner_comps, tf_inner_offset,
6283 ctx->oc_lds, 0, 1, 0, true, false);
6284 }
6285 }
6286 ac_nir_build_endif(&if_ctx);
6287 }
6288
6289 static void
6290 handle_tcs_outputs_post(struct nir_to_llvm_context *ctx)
6291 {
6292 write_tess_factors(ctx);
6293 }
6294
6295 static bool
6296 si_export_mrt_color(struct nir_to_llvm_context *ctx,
6297 LLVMValueRef *color, unsigned param, bool is_last,
6298 struct ac_export_args *args)
6299 {
6300 /* Export */
6301 si_llvm_init_export_args(ctx, color, param,
6302 args);
6303
6304 if (is_last) {
6305 args->valid_mask = 1; /* whether the EXEC mask is valid */
6306 args->done = 1; /* DONE bit */
6307 } else if (!args->enabled_channels)
6308 return false; /* unnecessary NULL export */
6309
6310 return true;
6311 }
6312
6313 static void
6314 radv_export_mrt_z(struct nir_to_llvm_context *ctx,
6315 LLVMValueRef depth, LLVMValueRef stencil,
6316 LLVMValueRef samplemask)
6317 {
6318 struct ac_export_args args;
6319
6320 ac_export_mrt_z(&ctx->ac, depth, stencil, samplemask, &args);
6321
6322 ac_build_export(&ctx->ac, &args);
6323 }
6324
6325 static void
6326 handle_fs_outputs_post(struct nir_to_llvm_context *ctx)
6327 {
6328 unsigned index = 0;
6329 LLVMValueRef depth = NULL, stencil = NULL, samplemask = NULL;
6330 struct ac_export_args color_args[8];
6331
6332 for (unsigned i = 0; i < RADEON_LLVM_MAX_OUTPUTS; ++i) {
6333 LLVMValueRef values[4];
6334
6335 if (!(ctx->output_mask & (1ull << i)))
6336 continue;
6337
6338 if (i == FRAG_RESULT_DEPTH) {
6339 ctx->shader_info->fs.writes_z = true;
6340 depth = ac_to_float(&ctx->ac, LLVMBuildLoad(ctx->builder,
6341 ctx->nir->outputs[radeon_llvm_reg_index_soa(i, 0)], ""));
6342 } else if (i == FRAG_RESULT_STENCIL) {
6343 ctx->shader_info->fs.writes_stencil = true;
6344 stencil = ac_to_float(&ctx->ac, LLVMBuildLoad(ctx->builder,
6345 ctx->nir->outputs[radeon_llvm_reg_index_soa(i, 0)], ""));
6346 } else if (i == FRAG_RESULT_SAMPLE_MASK) {
6347 ctx->shader_info->fs.writes_sample_mask = true;
6348 samplemask = ac_to_float(&ctx->ac, LLVMBuildLoad(ctx->builder,
6349 ctx->nir->outputs[radeon_llvm_reg_index_soa(i, 0)], ""));
6350 } else {
6351 bool last = false;
6352 for (unsigned j = 0; j < 4; j++)
6353 values[j] = ac_to_float(&ctx->ac, LLVMBuildLoad(ctx->builder,
6354 ctx->nir->outputs[radeon_llvm_reg_index_soa(i, j)], ""));
6355
6356 if (!ctx->shader_info->fs.writes_z && !ctx->shader_info->fs.writes_stencil && !ctx->shader_info->fs.writes_sample_mask)
6357 last = ctx->output_mask <= ((1ull << (i + 1)) - 1);
6358
6359 bool ret = si_export_mrt_color(ctx, values, V_008DFC_SQ_EXP_MRT + (i - FRAG_RESULT_DATA0), last, &color_args[index]);
6360 if (ret)
6361 index++;
6362 }
6363 }
6364
6365 for (unsigned i = 0; i < index; i++)
6366 ac_build_export(&ctx->ac, &color_args[i]);
6367 if (depth || stencil || samplemask)
6368 radv_export_mrt_z(ctx, depth, stencil, samplemask);
6369 else if (!index) {
6370 si_export_mrt_color(ctx, NULL, V_008DFC_SQ_EXP_NULL, true, &color_args[0]);
6371 ac_build_export(&ctx->ac, &color_args[0]);
6372 }
6373
6374 ctx->shader_info->fs.output_mask = index ? ((1ull << index) - 1) : 0;
6375 }
6376
6377 static void
6378 emit_gs_epilogue(struct nir_to_llvm_context *ctx)
6379 {
6380 ac_build_sendmsg(&ctx->ac, AC_SENDMSG_GS_OP_NOP | AC_SENDMSG_GS_DONE, ctx->gs_wave_id);
6381 }
6382
6383 static void
6384 handle_shader_outputs_post(struct ac_shader_abi *abi, unsigned max_outputs,
6385 LLVMValueRef *addrs)
6386 {
6387 struct nir_to_llvm_context *ctx = nir_to_llvm_context_from_abi(abi);
6388
6389 switch (ctx->stage) {
6390 case MESA_SHADER_VERTEX:
6391 if (ctx->options->key.vs.as_ls)
6392 handle_ls_outputs_post(ctx);
6393 else if (ctx->options->key.vs.as_es)
6394 handle_es_outputs_post(ctx, &ctx->shader_info->vs.es_info);
6395 else
6396 handle_vs_outputs_post(ctx, ctx->options->key.vs.export_prim_id,
6397 &ctx->shader_info->vs.outinfo);
6398 break;
6399 case MESA_SHADER_FRAGMENT:
6400 handle_fs_outputs_post(ctx);
6401 break;
6402 case MESA_SHADER_GEOMETRY:
6403 emit_gs_epilogue(ctx);
6404 break;
6405 case MESA_SHADER_TESS_CTRL:
6406 handle_tcs_outputs_post(ctx);
6407 break;
6408 case MESA_SHADER_TESS_EVAL:
6409 if (ctx->options->key.tes.as_es)
6410 handle_es_outputs_post(ctx, &ctx->shader_info->tes.es_info);
6411 else
6412 handle_vs_outputs_post(ctx, ctx->options->key.tes.export_prim_id,
6413 &ctx->shader_info->tes.outinfo);
6414 break;
6415 default:
6416 break;
6417 }
6418 }
6419
6420 static void ac_llvm_finalize_module(struct nir_to_llvm_context * ctx)
6421 {
6422 LLVMPassManagerRef passmgr;
6423 /* Create the pass manager */
6424 passmgr = LLVMCreateFunctionPassManagerForModule(
6425 ctx->module);
6426
6427 /* This pass should eliminate all the load and store instructions */
6428 LLVMAddPromoteMemoryToRegisterPass(passmgr);
6429
6430 /* Add some optimization passes */
6431 LLVMAddScalarReplAggregatesPass(passmgr);
6432 LLVMAddLICMPass(passmgr);
6433 LLVMAddAggressiveDCEPass(passmgr);
6434 LLVMAddCFGSimplificationPass(passmgr);
6435 LLVMAddInstructionCombiningPass(passmgr);
6436
6437 /* Run the pass */
6438 LLVMInitializeFunctionPassManager(passmgr);
6439 LLVMRunFunctionPassManager(passmgr, ctx->main_function);
6440 LLVMFinalizeFunctionPassManager(passmgr);
6441
6442 LLVMDisposeBuilder(ctx->builder);
6443 LLVMDisposePassManager(passmgr);
6444 }
6445
6446 static void
6447 ac_nir_eliminate_const_vs_outputs(struct nir_to_llvm_context *ctx)
6448 {
6449 struct ac_vs_output_info *outinfo;
6450
6451 switch (ctx->stage) {
6452 case MESA_SHADER_FRAGMENT:
6453 case MESA_SHADER_COMPUTE:
6454 case MESA_SHADER_TESS_CTRL:
6455 case MESA_SHADER_GEOMETRY:
6456 return;
6457 case MESA_SHADER_VERTEX:
6458 if (ctx->options->key.vs.as_ls ||
6459 ctx->options->key.vs.as_es)
6460 return;
6461 outinfo = &ctx->shader_info->vs.outinfo;
6462 break;
6463 case MESA_SHADER_TESS_EVAL:
6464 if (ctx->options->key.vs.as_es)
6465 return;
6466 outinfo = &ctx->shader_info->tes.outinfo;
6467 break;
6468 default:
6469 unreachable("Unhandled shader type");
6470 }
6471
6472 ac_optimize_vs_outputs(&ctx->ac,
6473 ctx->main_function,
6474 outinfo->vs_output_param_offset,
6475 VARYING_SLOT_MAX,
6476 &outinfo->param_exports);
6477 }
6478
6479 static void
6480 ac_setup_rings(struct nir_to_llvm_context *ctx)
6481 {
6482 if ((ctx->stage == MESA_SHADER_VERTEX && ctx->options->key.vs.as_es) ||
6483 (ctx->stage == MESA_SHADER_TESS_EVAL && ctx->options->key.tes.as_es)) {
6484 ctx->esgs_ring = ac_build_load_to_sgpr(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->ac.i32, RING_ESGS_VS, false));
6485 }
6486
6487 if (ctx->is_gs_copy_shader) {
6488 ctx->gsvs_ring = ac_build_load_to_sgpr(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->ac.i32, RING_GSVS_VS, false));
6489 }
6490 if (ctx->stage == MESA_SHADER_GEOMETRY) {
6491 LLVMValueRef tmp;
6492 ctx->esgs_ring = ac_build_load_to_sgpr(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->ac.i32, RING_ESGS_GS, false));
6493 ctx->gsvs_ring = ac_build_load_to_sgpr(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->ac.i32, RING_GSVS_GS, false));
6494
6495 ctx->gsvs_ring = LLVMBuildBitCast(ctx->builder, ctx->gsvs_ring, ctx->ac.v4i32, "");
6496
6497 ctx->gsvs_ring = LLVMBuildInsertElement(ctx->builder, ctx->gsvs_ring, ctx->gsvs_num_entries, LLVMConstInt(ctx->ac.i32, 2, false), "");
6498 tmp = LLVMBuildExtractElement(ctx->builder, ctx->gsvs_ring, ctx->ac.i32_1, "");
6499 tmp = LLVMBuildOr(ctx->builder, tmp, ctx->gsvs_ring_stride, "");
6500 ctx->gsvs_ring = LLVMBuildInsertElement(ctx->builder, ctx->gsvs_ring, tmp, ctx->ac.i32_1, "");
6501 }
6502
6503 if (ctx->stage == MESA_SHADER_TESS_CTRL ||
6504 ctx->stage == MESA_SHADER_TESS_EVAL) {
6505 ctx->hs_ring_tess_offchip = ac_build_load_to_sgpr(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->ac.i32, RING_HS_TESS_OFFCHIP, false));
6506 ctx->hs_ring_tess_factor = ac_build_load_to_sgpr(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->ac.i32, RING_HS_TESS_FACTOR, false));
6507 }
6508 }
6509
6510 static unsigned
6511 ac_nir_get_max_workgroup_size(enum chip_class chip_class,
6512 const struct nir_shader *nir)
6513 {
6514 switch (nir->info.stage) {
6515 case MESA_SHADER_TESS_CTRL:
6516 return chip_class >= CIK ? 128 : 64;
6517 case MESA_SHADER_GEOMETRY:
6518 return chip_class >= GFX9 ? 128 : 64;
6519 case MESA_SHADER_COMPUTE:
6520 break;
6521 default:
6522 return 0;
6523 }
6524
6525 unsigned max_workgroup_size = nir->info.cs.local_size[0] *
6526 nir->info.cs.local_size[1] *
6527 nir->info.cs.local_size[2];
6528 return max_workgroup_size;
6529 }
6530
6531 /* Fixup the HW not emitting the TCS regs if there are no HS threads. */
6532 static void ac_nir_fixup_ls_hs_input_vgprs(struct nir_to_llvm_context *ctx)
6533 {
6534 LLVMValueRef count = ac_build_bfe(&ctx->ac, ctx->merged_wave_info,
6535 LLVMConstInt(ctx->ac.i32, 8, false),
6536 LLVMConstInt(ctx->ac.i32, 8, false), false);
6537 LLVMValueRef hs_empty = LLVMBuildICmp(ctx->ac.builder, LLVMIntEQ, count,
6538 ctx->ac.i32_0, "");
6539 ctx->abi.instance_id = LLVMBuildSelect(ctx->ac.builder, hs_empty, ctx->rel_auto_id, ctx->abi.instance_id, "");
6540 ctx->vs_prim_id = LLVMBuildSelect(ctx->ac.builder, hs_empty, ctx->abi.vertex_id, ctx->vs_prim_id, "");
6541 ctx->rel_auto_id = LLVMBuildSelect(ctx->ac.builder, hs_empty, ctx->abi.tcs_rel_ids, ctx->rel_auto_id, "");
6542 ctx->abi.vertex_id = LLVMBuildSelect(ctx->ac.builder, hs_empty, ctx->abi.tcs_patch_id, ctx->abi.vertex_id, "");
6543 }
6544
6545 static void prepare_gs_input_vgprs(struct nir_to_llvm_context *ctx)
6546 {
6547 for(int i = 5; i >= 0; --i) {
6548 ctx->gs_vtx_offset[i] = ac_build_bfe(&ctx->ac, ctx->gs_vtx_offset[i & ~1],
6549 LLVMConstInt(ctx->ac.i32, (i & 1) * 16, false),
6550 LLVMConstInt(ctx->ac.i32, 16, false), false);
6551 }
6552
6553 ctx->gs_wave_id = ac_build_bfe(&ctx->ac, ctx->merged_wave_info,
6554 LLVMConstInt(ctx->ac.i32, 16, false),
6555 LLVMConstInt(ctx->ac.i32, 8, false), false);
6556 }
6557
6558 void ac_nir_translate(struct ac_llvm_context *ac, struct ac_shader_abi *abi,
6559 struct nir_shader *nir, struct nir_to_llvm_context *nctx)
6560 {
6561 struct ac_nir_context ctx = {};
6562 struct nir_function *func;
6563
6564 ctx.ac = *ac;
6565 ctx.abi = abi;
6566
6567 ctx.nctx = nctx;
6568 if (nctx)
6569 nctx->nir = &ctx;
6570
6571 ctx.stage = nir->info.stage;
6572
6573 ctx.main_function = LLVMGetBasicBlockParent(LLVMGetInsertBlock(ctx.ac.builder));
6574
6575 nir_foreach_variable(variable, &nir->outputs)
6576 handle_shader_output_decl(&ctx, nir, variable);
6577
6578 ctx.defs = _mesa_hash_table_create(NULL, _mesa_hash_pointer,
6579 _mesa_key_pointer_equal);
6580 ctx.phis = _mesa_hash_table_create(NULL, _mesa_hash_pointer,
6581 _mesa_key_pointer_equal);
6582 ctx.vars = _mesa_hash_table_create(NULL, _mesa_hash_pointer,
6583 _mesa_key_pointer_equal);
6584
6585 func = (struct nir_function *)exec_list_get_head(&nir->functions);
6586
6587 setup_locals(&ctx, func);
6588
6589 if (nir->info.stage == MESA_SHADER_COMPUTE)
6590 setup_shared(&ctx, nir);
6591
6592 visit_cf_list(&ctx, &func->impl->body);
6593 phi_post_pass(&ctx);
6594
6595 ctx.abi->emit_outputs(ctx.abi, RADEON_LLVM_MAX_OUTPUTS,
6596 ctx.outputs);
6597
6598 free(ctx.locals);
6599 ralloc_free(ctx.defs);
6600 ralloc_free(ctx.phis);
6601 ralloc_free(ctx.vars);
6602
6603 if (nctx)
6604 nctx->nir = NULL;
6605 }
6606
6607 static
6608 LLVMModuleRef ac_translate_nir_to_llvm(LLVMTargetMachineRef tm,
6609 struct nir_shader *const *shaders,
6610 int shader_count,
6611 struct ac_shader_variant_info *shader_info,
6612 const struct ac_nir_compiler_options *options)
6613 {
6614 struct nir_to_llvm_context ctx = {0};
6615 unsigned i;
6616 ctx.options = options;
6617 ctx.shader_info = shader_info;
6618 ctx.context = LLVMContextCreate();
6619 ctx.module = LLVMModuleCreateWithNameInContext("shader", ctx.context);
6620
6621 ac_llvm_context_init(&ctx.ac, ctx.context, options->chip_class,
6622 options->family);
6623 ctx.ac.module = ctx.module;
6624 LLVMSetTarget(ctx.module, options->supports_spill ? "amdgcn-mesa-mesa3d" : "amdgcn--");
6625
6626 LLVMTargetDataRef data_layout = LLVMCreateTargetDataLayout(tm);
6627 char *data_layout_str = LLVMCopyStringRepOfTargetData(data_layout);
6628 LLVMSetDataLayout(ctx.module, data_layout_str);
6629 LLVMDisposeTargetData(data_layout);
6630 LLVMDisposeMessage(data_layout_str);
6631
6632 ctx.builder = LLVMCreateBuilderInContext(ctx.context);
6633 ctx.ac.builder = ctx.builder;
6634
6635 memset(shader_info, 0, sizeof(*shader_info));
6636
6637 for(int i = 0; i < shader_count; ++i)
6638 ac_nir_shader_info_pass(shaders[i], options, &shader_info->info);
6639
6640 for (i = 0; i < AC_UD_MAX_SETS; i++)
6641 shader_info->user_sgprs_locs.descriptor_sets[i].sgpr_idx = -1;
6642 for (i = 0; i < AC_UD_MAX_UD; i++)
6643 shader_info->user_sgprs_locs.shader_data[i].sgpr_idx = -1;
6644
6645 ctx.max_workgroup_size = 0;
6646 for (int i = 0; i < shader_count; ++i) {
6647 ctx.max_workgroup_size = MAX2(ctx.max_workgroup_size,
6648 ac_nir_get_max_workgroup_size(ctx.options->chip_class,
6649 shaders[i]));
6650 }
6651
6652 create_function(&ctx, shaders[shader_count - 1]->info.stage, shader_count >= 2,
6653 shader_count >= 2 ? shaders[shader_count - 2]->info.stage : MESA_SHADER_VERTEX);
6654
6655 ctx.abi.inputs = &ctx.inputs[0];
6656 ctx.abi.emit_outputs = handle_shader_outputs_post;
6657 ctx.abi.emit_vertex = visit_emit_vertex;
6658 ctx.abi.load_ubo = radv_load_ubo;
6659 ctx.abi.load_ssbo = radv_load_ssbo;
6660 ctx.abi.load_sampler_desc = radv_get_sampler_desc;
6661 ctx.abi.clamp_shadow_reference = false;
6662
6663 if (shader_count >= 2)
6664 ac_init_exec_full_mask(&ctx.ac);
6665
6666 if (ctx.ac.chip_class == GFX9 &&
6667 shaders[shader_count - 1]->info.stage == MESA_SHADER_TESS_CTRL)
6668 ac_nir_fixup_ls_hs_input_vgprs(&ctx);
6669
6670 for(int i = 0; i < shader_count; ++i) {
6671 ctx.stage = shaders[i]->info.stage;
6672 ctx.output_mask = 0;
6673 ctx.tess_outputs_written = 0;
6674 ctx.num_output_clips = shaders[i]->info.clip_distance_array_size;
6675 ctx.num_output_culls = shaders[i]->info.cull_distance_array_size;
6676
6677 if (shaders[i]->info.stage == MESA_SHADER_GEOMETRY) {
6678 ctx.gs_next_vertex = ac_build_alloca(&ctx.ac, ctx.ac.i32, "gs_next_vertex");
6679 ctx.gs_max_out_vertices = shaders[i]->info.gs.vertices_out;
6680 ctx.abi.load_inputs = load_gs_input;
6681 } else if (shaders[i]->info.stage == MESA_SHADER_TESS_CTRL) {
6682 ctx.tcs_outputs_read = shaders[i]->info.outputs_read;
6683 ctx.tcs_patch_outputs_read = shaders[i]->info.patch_outputs_read;
6684 ctx.abi.load_tess_inputs = load_tcs_input;
6685 ctx.abi.store_tcs_outputs = store_tcs_output;
6686 } else if (shaders[i]->info.stage == MESA_SHADER_TESS_EVAL) {
6687 ctx.tes_primitive_mode = shaders[i]->info.tess.primitive_mode;
6688 ctx.abi.load_tess_inputs = load_tes_input;
6689 } else if (shaders[i]->info.stage == MESA_SHADER_VERTEX) {
6690 if (shader_info->info.vs.needs_instance_id) {
6691 ctx.shader_info->vs.vgpr_comp_cnt =
6692 MAX2(3, ctx.shader_info->vs.vgpr_comp_cnt);
6693 }
6694 } else if (shaders[i]->info.stage == MESA_SHADER_FRAGMENT) {
6695 shader_info->fs.can_discard = shaders[i]->info.fs.uses_discard;
6696 }
6697
6698 if (i)
6699 emit_barrier(&ctx);
6700
6701 ac_setup_rings(&ctx);
6702
6703 LLVMBasicBlockRef merge_block;
6704 if (shader_count >= 2) {
6705 LLVMValueRef fn = LLVMGetBasicBlockParent(LLVMGetInsertBlock(ctx.ac.builder));
6706 LLVMBasicBlockRef then_block = LLVMAppendBasicBlockInContext(ctx.ac.context, fn, "");
6707 merge_block = LLVMAppendBasicBlockInContext(ctx.ac.context, fn, "");
6708
6709 LLVMValueRef count = ac_build_bfe(&ctx.ac, ctx.merged_wave_info,
6710 LLVMConstInt(ctx.ac.i32, 8 * i, false),
6711 LLVMConstInt(ctx.ac.i32, 8, false), false);
6712 LLVMValueRef thread_id = ac_get_thread_id(&ctx.ac);
6713 LLVMValueRef cond = LLVMBuildICmp(ctx.ac.builder, LLVMIntULT,
6714 thread_id, count, "");
6715 LLVMBuildCondBr(ctx.ac.builder, cond, then_block, merge_block);
6716
6717 LLVMPositionBuilderAtEnd(ctx.ac.builder, then_block);
6718 }
6719
6720 if (shaders[i]->info.stage == MESA_SHADER_FRAGMENT)
6721 handle_fs_inputs(&ctx, shaders[i]);
6722 else if(shaders[i]->info.stage == MESA_SHADER_VERTEX)
6723 handle_vs_inputs(&ctx, shaders[i]);
6724 else if(shader_count >= 2 && shaders[i]->info.stage == MESA_SHADER_GEOMETRY)
6725 prepare_gs_input_vgprs(&ctx);
6726
6727 nir_foreach_variable(variable, &shaders[i]->outputs)
6728 scan_shader_output_decl(&ctx, variable, shaders[i], shaders[i]->info.stage);
6729
6730 ac_nir_translate(&ctx.ac, &ctx.abi, shaders[i], &ctx);
6731
6732 if (shader_count >= 2) {
6733 LLVMBuildBr(ctx.ac.builder, merge_block);
6734 LLVMPositionBuilderAtEnd(ctx.ac.builder, merge_block);
6735 }
6736
6737 if (shaders[i]->info.stage == MESA_SHADER_GEOMETRY) {
6738 unsigned addclip = shaders[i]->info.clip_distance_array_size +
6739 shaders[i]->info.cull_distance_array_size > 4;
6740 shader_info->gs.gsvs_vertex_size = (util_bitcount64(ctx.output_mask) + addclip) * 16;
6741 shader_info->gs.max_gsvs_emit_size = shader_info->gs.gsvs_vertex_size *
6742 shaders[i]->info.gs.vertices_out;
6743 } else if (shaders[i]->info.stage == MESA_SHADER_TESS_CTRL) {
6744 shader_info->tcs.outputs_written = ctx.tess_outputs_written;
6745 shader_info->tcs.patch_outputs_written = ctx.tess_patch_outputs_written;
6746 } else if (shaders[i]->info.stage == MESA_SHADER_VERTEX && ctx.options->key.vs.as_ls) {
6747 shader_info->vs.outputs_written = ctx.tess_outputs_written;
6748 }
6749 }
6750
6751 LLVMBuildRetVoid(ctx.builder);
6752
6753 ac_llvm_finalize_module(&ctx);
6754
6755 if (shader_count == 1)
6756 ac_nir_eliminate_const_vs_outputs(&ctx);
6757
6758 return ctx.module;
6759 }
6760
6761 static void ac_diagnostic_handler(LLVMDiagnosticInfoRef di, void *context)
6762 {
6763 unsigned *retval = (unsigned *)context;
6764 LLVMDiagnosticSeverity severity = LLVMGetDiagInfoSeverity(di);
6765 char *description = LLVMGetDiagInfoDescription(di);
6766
6767 if (severity == LLVMDSError) {
6768 *retval = 1;
6769 fprintf(stderr, "LLVM triggered Diagnostic Handler: %s\n",
6770 description);
6771 }
6772
6773 LLVMDisposeMessage(description);
6774 }
6775
6776 static unsigned ac_llvm_compile(LLVMModuleRef M,
6777 struct ac_shader_binary *binary,
6778 LLVMTargetMachineRef tm)
6779 {
6780 unsigned retval = 0;
6781 char *err;
6782 LLVMContextRef llvm_ctx;
6783 LLVMMemoryBufferRef out_buffer;
6784 unsigned buffer_size;
6785 const char *buffer_data;
6786 LLVMBool mem_err;
6787
6788 /* Setup Diagnostic Handler*/
6789 llvm_ctx = LLVMGetModuleContext(M);
6790
6791 LLVMContextSetDiagnosticHandler(llvm_ctx, ac_diagnostic_handler,
6792 &retval);
6793
6794 /* Compile IR*/
6795 mem_err = LLVMTargetMachineEmitToMemoryBuffer(tm, M, LLVMObjectFile,
6796 &err, &out_buffer);
6797
6798 /* Process Errors/Warnings */
6799 if (mem_err) {
6800 fprintf(stderr, "%s: %s", __FUNCTION__, err);
6801 free(err);
6802 retval = 1;
6803 goto out;
6804 }
6805
6806 /* Extract Shader Code*/
6807 buffer_size = LLVMGetBufferSize(out_buffer);
6808 buffer_data = LLVMGetBufferStart(out_buffer);
6809
6810 ac_elf_read(buffer_data, buffer_size, binary);
6811
6812 /* Clean up */
6813 LLVMDisposeMemoryBuffer(out_buffer);
6814
6815 out:
6816 return retval;
6817 }
6818
6819 static void ac_compile_llvm_module(LLVMTargetMachineRef tm,
6820 LLVMModuleRef llvm_module,
6821 struct ac_shader_binary *binary,
6822 struct ac_shader_config *config,
6823 struct ac_shader_variant_info *shader_info,
6824 gl_shader_stage stage,
6825 bool dump_shader, bool supports_spill)
6826 {
6827 if (dump_shader)
6828 ac_dump_module(llvm_module);
6829
6830 memset(binary, 0, sizeof(*binary));
6831 int v = ac_llvm_compile(llvm_module, binary, tm);
6832 if (v) {
6833 fprintf(stderr, "compile failed\n");
6834 }
6835
6836 if (dump_shader)
6837 fprintf(stderr, "disasm:\n%s\n", binary->disasm_string);
6838
6839 ac_shader_binary_read_config(binary, config, 0, supports_spill);
6840
6841 LLVMContextRef ctx = LLVMGetModuleContext(llvm_module);
6842 LLVMDisposeModule(llvm_module);
6843 LLVMContextDispose(ctx);
6844
6845 if (stage == MESA_SHADER_FRAGMENT) {
6846 shader_info->num_input_vgprs = 0;
6847 if (G_0286CC_PERSP_SAMPLE_ENA(config->spi_ps_input_addr))
6848 shader_info->num_input_vgprs += 2;
6849 if (G_0286CC_PERSP_CENTER_ENA(config->spi_ps_input_addr))
6850 shader_info->num_input_vgprs += 2;
6851 if (G_0286CC_PERSP_CENTROID_ENA(config->spi_ps_input_addr))
6852 shader_info->num_input_vgprs += 2;
6853 if (G_0286CC_PERSP_PULL_MODEL_ENA(config->spi_ps_input_addr))
6854 shader_info->num_input_vgprs += 3;
6855 if (G_0286CC_LINEAR_SAMPLE_ENA(config->spi_ps_input_addr))
6856 shader_info->num_input_vgprs += 2;
6857 if (G_0286CC_LINEAR_CENTER_ENA(config->spi_ps_input_addr))
6858 shader_info->num_input_vgprs += 2;
6859 if (G_0286CC_LINEAR_CENTROID_ENA(config->spi_ps_input_addr))
6860 shader_info->num_input_vgprs += 2;
6861 if (G_0286CC_LINE_STIPPLE_TEX_ENA(config->spi_ps_input_addr))
6862 shader_info->num_input_vgprs += 1;
6863 if (G_0286CC_POS_X_FLOAT_ENA(config->spi_ps_input_addr))
6864 shader_info->num_input_vgprs += 1;
6865 if (G_0286CC_POS_Y_FLOAT_ENA(config->spi_ps_input_addr))
6866 shader_info->num_input_vgprs += 1;
6867 if (G_0286CC_POS_Z_FLOAT_ENA(config->spi_ps_input_addr))
6868 shader_info->num_input_vgprs += 1;
6869 if (G_0286CC_POS_W_FLOAT_ENA(config->spi_ps_input_addr))
6870 shader_info->num_input_vgprs += 1;
6871 if (G_0286CC_FRONT_FACE_ENA(config->spi_ps_input_addr))
6872 shader_info->num_input_vgprs += 1;
6873 if (G_0286CC_ANCILLARY_ENA(config->spi_ps_input_addr))
6874 shader_info->num_input_vgprs += 1;
6875 if (G_0286CC_SAMPLE_COVERAGE_ENA(config->spi_ps_input_addr))
6876 shader_info->num_input_vgprs += 1;
6877 if (G_0286CC_POS_FIXED_PT_ENA(config->spi_ps_input_addr))
6878 shader_info->num_input_vgprs += 1;
6879 }
6880 config->num_vgprs = MAX2(config->num_vgprs, shader_info->num_input_vgprs);
6881
6882 /* +3 for scratch wave offset and VCC */
6883 config->num_sgprs = MAX2(config->num_sgprs,
6884 shader_info->num_input_sgprs + 3);
6885 }
6886
6887 static void
6888 ac_fill_shader_info(struct ac_shader_variant_info *shader_info, struct nir_shader *nir, const struct ac_nir_compiler_options *options)
6889 {
6890 switch (nir->info.stage) {
6891 case MESA_SHADER_COMPUTE:
6892 for (int i = 0; i < 3; ++i)
6893 shader_info->cs.block_size[i] = nir->info.cs.local_size[i];
6894 break;
6895 case MESA_SHADER_FRAGMENT:
6896 shader_info->fs.early_fragment_test = nir->info.fs.early_fragment_tests;
6897 break;
6898 case MESA_SHADER_GEOMETRY:
6899 shader_info->gs.vertices_in = nir->info.gs.vertices_in;
6900 shader_info->gs.vertices_out = nir->info.gs.vertices_out;
6901 shader_info->gs.output_prim = nir->info.gs.output_primitive;
6902 shader_info->gs.invocations = nir->info.gs.invocations;
6903 break;
6904 case MESA_SHADER_TESS_EVAL:
6905 shader_info->tes.primitive_mode = nir->info.tess.primitive_mode;
6906 shader_info->tes.spacing = nir->info.tess.spacing;
6907 shader_info->tes.ccw = nir->info.tess.ccw;
6908 shader_info->tes.point_mode = nir->info.tess.point_mode;
6909 shader_info->tes.as_es = options->key.tes.as_es;
6910 break;
6911 case MESA_SHADER_TESS_CTRL:
6912 shader_info->tcs.tcs_vertices_out = nir->info.tess.tcs_vertices_out;
6913 break;
6914 case MESA_SHADER_VERTEX:
6915 shader_info->vs.as_es = options->key.vs.as_es;
6916 shader_info->vs.as_ls = options->key.vs.as_ls;
6917 /* in LS mode we need at least 1, invocation id needs 3, handled elsewhere */
6918 if (options->key.vs.as_ls)
6919 shader_info->vs.vgpr_comp_cnt = MAX2(1, shader_info->vs.vgpr_comp_cnt);
6920 break;
6921 default:
6922 break;
6923 }
6924 }
6925
6926 void ac_compile_nir_shader(LLVMTargetMachineRef tm,
6927 struct ac_shader_binary *binary,
6928 struct ac_shader_config *config,
6929 struct ac_shader_variant_info *shader_info,
6930 struct nir_shader *const *nir,
6931 int nir_count,
6932 const struct ac_nir_compiler_options *options,
6933 bool dump_shader)
6934 {
6935
6936 LLVMModuleRef llvm_module = ac_translate_nir_to_llvm(tm, nir, nir_count, shader_info,
6937 options);
6938
6939 ac_compile_llvm_module(tm, llvm_module, binary, config, shader_info, nir[0]->info.stage, dump_shader, options->supports_spill);
6940 for (int i = 0; i < nir_count; ++i)
6941 ac_fill_shader_info(shader_info, nir[i], options);
6942 }
6943
6944 static void
6945 ac_gs_copy_shader_emit(struct nir_to_llvm_context *ctx)
6946 {
6947 LLVMValueRef args[9];
6948 args[0] = ctx->gsvs_ring;
6949 args[1] = LLVMBuildMul(ctx->builder, ctx->abi.vertex_id, LLVMConstInt(ctx->ac.i32, 4, false), "");
6950 args[3] = ctx->ac.i32_0;
6951 args[4] = ctx->ac.i32_1; /* OFFEN */
6952 args[5] = ctx->ac.i32_0; /* IDXEN */
6953 args[6] = ctx->ac.i32_1; /* GLC */
6954 args[7] = ctx->ac.i32_1; /* SLC */
6955 args[8] = ctx->ac.i32_0; /* TFE */
6956
6957 int idx = 0;
6958
6959 for (unsigned i = 0; i < RADEON_LLVM_MAX_OUTPUTS; ++i) {
6960 int length = 4;
6961 int slot = idx;
6962 int slot_inc = 1;
6963 if (!(ctx->output_mask & (1ull << i)))
6964 continue;
6965
6966 if (i == VARYING_SLOT_CLIP_DIST0) {
6967 /* unpack clip and cull from a single set of slots */
6968 length = ctx->num_output_clips + ctx->num_output_culls;
6969 if (length > 4)
6970 slot_inc = 2;
6971 }
6972
6973 for (unsigned j = 0; j < length; j++) {
6974 LLVMValueRef value;
6975 args[2] = LLVMConstInt(ctx->ac.i32,
6976 (slot * 4 + j) *
6977 ctx->gs_max_out_vertices * 16 * 4, false);
6978
6979 value = ac_build_intrinsic(&ctx->ac,
6980 "llvm.SI.buffer.load.dword.i32.i32",
6981 ctx->ac.i32, args, 9,
6982 AC_FUNC_ATTR_READONLY |
6983 AC_FUNC_ATTR_LEGACY);
6984
6985 LLVMBuildStore(ctx->builder,
6986 ac_to_float(&ctx->ac, value), ctx->nir->outputs[radeon_llvm_reg_index_soa(i, j)]);
6987 }
6988 idx += slot_inc;
6989 }
6990 handle_vs_outputs_post(ctx, false, &ctx->shader_info->vs.outinfo);
6991 }
6992
6993 void ac_create_gs_copy_shader(LLVMTargetMachineRef tm,
6994 struct nir_shader *geom_shader,
6995 struct ac_shader_binary *binary,
6996 struct ac_shader_config *config,
6997 struct ac_shader_variant_info *shader_info,
6998 const struct ac_nir_compiler_options *options,
6999 bool dump_shader)
7000 {
7001 struct nir_to_llvm_context ctx = {0};
7002 ctx.context = LLVMContextCreate();
7003 ctx.module = LLVMModuleCreateWithNameInContext("shader", ctx.context);
7004 ctx.options = options;
7005 ctx.shader_info = shader_info;
7006
7007 ac_llvm_context_init(&ctx.ac, ctx.context, options->chip_class,
7008 options->family);
7009 ctx.ac.module = ctx.module;
7010
7011 ctx.is_gs_copy_shader = true;
7012 LLVMSetTarget(ctx.module, "amdgcn--");
7013
7014 ctx.builder = LLVMCreateBuilderInContext(ctx.context);
7015 ctx.ac.builder = ctx.builder;
7016 ctx.stage = MESA_SHADER_VERTEX;
7017
7018 create_function(&ctx, MESA_SHADER_VERTEX, false, MESA_SHADER_VERTEX);
7019
7020 ctx.gs_max_out_vertices = geom_shader->info.gs.vertices_out;
7021 ac_setup_rings(&ctx);
7022
7023 ctx.num_output_clips = geom_shader->info.clip_distance_array_size;
7024 ctx.num_output_culls = geom_shader->info.cull_distance_array_size;
7025
7026 struct ac_nir_context nir_ctx = {};
7027 nir_ctx.ac = ctx.ac;
7028 nir_ctx.abi = &ctx.abi;
7029
7030 nir_ctx.nctx = &ctx;
7031 ctx.nir = &nir_ctx;
7032
7033 nir_foreach_variable(variable, &geom_shader->outputs) {
7034 scan_shader_output_decl(&ctx, variable, geom_shader, MESA_SHADER_VERTEX);
7035 handle_shader_output_decl(&nir_ctx, geom_shader, variable);
7036 }
7037
7038 ac_gs_copy_shader_emit(&ctx);
7039
7040 ctx.nir = NULL;
7041
7042 LLVMBuildRetVoid(ctx.builder);
7043
7044 ac_llvm_finalize_module(&ctx);
7045
7046 ac_compile_llvm_module(tm, ctx.module, binary, config, shader_info,
7047 MESA_SHADER_VERTEX,
7048 dump_shader, options->supports_spill);
7049 }