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10 * Software is furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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21 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
31 #include "ac_shader_util.h"
33 #include "aco_builder.h"
34 #include "aco_interface.h"
35 #include "aco_instruction_selection_setup.cpp"
36 #include "util/fast_idiv_by_const.h"
41 class loop_info_RAII
{
43 unsigned header_idx_old
;
45 bool divergent_cont_old
;
46 bool divergent_branch_old
;
47 bool divergent_if_old
;
50 loop_info_RAII(isel_context
* ctx
, unsigned loop_header_idx
, Block
* loop_exit
)
52 header_idx_old(ctx
->cf_info
.parent_loop
.header_idx
), exit_old(ctx
->cf_info
.parent_loop
.exit
),
53 divergent_cont_old(ctx
->cf_info
.parent_loop
.has_divergent_continue
),
54 divergent_branch_old(ctx
->cf_info
.parent_loop
.has_divergent_branch
),
55 divergent_if_old(ctx
->cf_info
.parent_if
.is_divergent
)
57 ctx
->cf_info
.parent_loop
.header_idx
= loop_header_idx
;
58 ctx
->cf_info
.parent_loop
.exit
= loop_exit
;
59 ctx
->cf_info
.parent_loop
.has_divergent_continue
= false;
60 ctx
->cf_info
.parent_loop
.has_divergent_branch
= false;
61 ctx
->cf_info
.parent_if
.is_divergent
= false;
62 ctx
->cf_info
.loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
+ 1;
67 ctx
->cf_info
.parent_loop
.header_idx
= header_idx_old
;
68 ctx
->cf_info
.parent_loop
.exit
= exit_old
;
69 ctx
->cf_info
.parent_loop
.has_divergent_continue
= divergent_cont_old
;
70 ctx
->cf_info
.parent_loop
.has_divergent_branch
= divergent_branch_old
;
71 ctx
->cf_info
.parent_if
.is_divergent
= divergent_if_old
;
72 ctx
->cf_info
.loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
- 1;
73 if (!ctx
->cf_info
.loop_nest_depth
&& !ctx
->cf_info
.parent_if
.is_divergent
)
74 ctx
->cf_info
.exec_potentially_empty_discard
= false;
82 bool exec_potentially_empty_discard_old
;
83 bool exec_potentially_empty_break_old
;
84 uint16_t exec_potentially_empty_break_depth_old
;
88 bool uniform_has_then_branch
;
89 bool then_branch_divergent
;
94 static bool visit_cf_list(struct isel_context
*ctx
,
95 struct exec_list
*list
);
97 static void add_logical_edge(unsigned pred_idx
, Block
*succ
)
99 succ
->logical_preds
.emplace_back(pred_idx
);
103 static void add_linear_edge(unsigned pred_idx
, Block
*succ
)
105 succ
->linear_preds
.emplace_back(pred_idx
);
108 static void add_edge(unsigned pred_idx
, Block
*succ
)
110 add_logical_edge(pred_idx
, succ
);
111 add_linear_edge(pred_idx
, succ
);
114 static void append_logical_start(Block
*b
)
116 Builder(NULL
, b
).pseudo(aco_opcode::p_logical_start
);
119 static void append_logical_end(Block
*b
)
121 Builder(NULL
, b
).pseudo(aco_opcode::p_logical_end
);
124 Temp
get_ssa_temp(struct isel_context
*ctx
, nir_ssa_def
*def
)
126 assert(ctx
->allocated
[def
->index
].id());
127 return ctx
->allocated
[def
->index
];
130 Temp
emit_mbcnt(isel_context
*ctx
, Definition dst
,
131 Operand mask_lo
= Operand((uint32_t) -1), Operand mask_hi
= Operand((uint32_t) -1))
133 Builder
bld(ctx
->program
, ctx
->block
);
134 Definition lo_def
= ctx
->program
->wave_size
== 32 ? dst
: bld
.def(v1
);
135 Temp thread_id_lo
= bld
.vop3(aco_opcode::v_mbcnt_lo_u32_b32
, lo_def
, mask_lo
, Operand(0u));
137 if (ctx
->program
->wave_size
== 32) {
140 Temp thread_id_hi
= bld
.vop3(aco_opcode::v_mbcnt_hi_u32_b32
, dst
, mask_hi
, thread_id_lo
);
145 Temp
emit_wqm(isel_context
*ctx
, Temp src
, Temp dst
=Temp(0, s1
), bool program_needs_wqm
= false)
147 Builder
bld(ctx
->program
, ctx
->block
);
150 dst
= bld
.tmp(src
.regClass());
152 assert(src
.size() == dst
.size());
154 if (ctx
->stage
!= fragment_fs
) {
158 bld
.copy(Definition(dst
), src
);
162 bld
.pseudo(aco_opcode::p_wqm
, Definition(dst
), src
);
163 ctx
->program
->needs_wqm
|= program_needs_wqm
;
167 static Temp
emit_bpermute(isel_context
*ctx
, Builder
&bld
, Temp index
, Temp data
)
169 if (index
.regClass() == s1
)
170 return bld
.readlane(bld
.def(s1
), data
, index
);
172 if (ctx
->options
->chip_class
<= GFX7
) {
173 /* GFX6-7: there is no bpermute instruction */
174 Operand
index_op(index
);
175 Operand
input_data(data
);
176 index_op
.setLateKill(true);
177 input_data
.setLateKill(true);
179 return bld
.pseudo(aco_opcode::p_bpermute
, bld
.def(v1
), bld
.def(bld
.lm
), bld
.def(bld
.lm
, vcc
), index_op
, input_data
);
180 } else if (ctx
->options
->chip_class
>= GFX10
&& ctx
->program
->wave_size
== 64) {
181 /* GFX10 wave64 mode: emulate full-wave bpermute */
182 if (!ctx
->has_gfx10_wave64_bpermute
) {
183 ctx
->has_gfx10_wave64_bpermute
= true;
184 ctx
->program
->config
->num_shared_vgprs
= 8; /* Shared VGPRs are allocated in groups of 8 */
185 ctx
->program
->vgpr_limit
-= 4; /* We allocate 8 shared VGPRs, so we'll have 4 fewer normal VGPRs */
188 Temp index_is_lo
= bld
.vopc(aco_opcode::v_cmp_ge_u32
, bld
.def(bld
.lm
), Operand(31u), index
);
189 Builder::Result index_is_lo_split
= bld
.pseudo(aco_opcode::p_split_vector
, bld
.def(s1
), bld
.def(s1
), index_is_lo
);
190 Temp index_is_lo_n1
= bld
.sop1(aco_opcode::s_not_b32
, bld
.def(s1
), bld
.def(s1
, scc
), index_is_lo_split
.def(1).getTemp());
191 Operand same_half
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s2
), index_is_lo_split
.def(0).getTemp(), index_is_lo_n1
);
192 Operand index_x4
= bld
.vop2(aco_opcode::v_lshlrev_b32
, bld
.def(v1
), Operand(2u), index
);
193 Operand
input_data(data
);
195 index_x4
.setLateKill(true);
196 input_data
.setLateKill(true);
197 same_half
.setLateKill(true);
199 return bld
.pseudo(aco_opcode::p_bpermute
, bld
.def(v1
), bld
.def(s2
), bld
.def(s1
, scc
), index_x4
, input_data
, same_half
);
201 /* GFX8-9 or GFX10 wave32: bpermute works normally */
202 Temp index_x4
= bld
.vop2(aco_opcode::v_lshlrev_b32
, bld
.def(v1
), Operand(2u), index
);
203 return bld
.ds(aco_opcode::ds_bpermute_b32
, bld
.def(v1
), index_x4
, data
);
207 Temp
as_vgpr(isel_context
*ctx
, Temp val
)
209 if (val
.type() == RegType::sgpr
) {
210 Builder
bld(ctx
->program
, ctx
->block
);
211 return bld
.copy(bld
.def(RegType::vgpr
, val
.size()), val
);
213 assert(val
.type() == RegType::vgpr
);
217 //assumes a != 0xffffffff
218 void emit_v_div_u32(isel_context
*ctx
, Temp dst
, Temp a
, uint32_t b
)
221 Builder
bld(ctx
->program
, ctx
->block
);
223 if (util_is_power_of_two_or_zero(b
)) {
224 bld
.vop2(aco_opcode::v_lshrrev_b32
, Definition(dst
), Operand((uint32_t)util_logbase2(b
)), a
);
228 util_fast_udiv_info info
= util_compute_fast_udiv_info(b
, 32, 32);
230 assert(info
.multiplier
<= 0xffffffff);
232 bool pre_shift
= info
.pre_shift
!= 0;
233 bool increment
= info
.increment
!= 0;
234 bool multiply
= true;
235 bool post_shift
= info
.post_shift
!= 0;
237 if (!pre_shift
&& !increment
&& !multiply
&& !post_shift
) {
238 bld
.vop1(aco_opcode::v_mov_b32
, Definition(dst
), a
);
242 Temp pre_shift_dst
= a
;
244 pre_shift_dst
= (increment
|| multiply
|| post_shift
) ? bld
.tmp(v1
) : dst
;
245 bld
.vop2(aco_opcode::v_lshrrev_b32
, Definition(pre_shift_dst
), Operand((uint32_t)info
.pre_shift
), a
);
248 Temp increment_dst
= pre_shift_dst
;
250 increment_dst
= (post_shift
|| multiply
) ? bld
.tmp(v1
) : dst
;
251 bld
.vadd32(Definition(increment_dst
), Operand((uint32_t) info
.increment
), pre_shift_dst
);
254 Temp multiply_dst
= increment_dst
;
256 multiply_dst
= post_shift
? bld
.tmp(v1
) : dst
;
257 bld
.vop3(aco_opcode::v_mul_hi_u32
, Definition(multiply_dst
), increment_dst
,
258 bld
.vop1(aco_opcode::v_mov_b32
, bld
.def(v1
), Operand((uint32_t)info
.multiplier
)));
262 bld
.vop2(aco_opcode::v_lshrrev_b32
, Definition(dst
), Operand((uint32_t)info
.post_shift
), multiply_dst
);
266 void emit_extract_vector(isel_context
* ctx
, Temp src
, uint32_t idx
, Temp dst
)
268 Builder
bld(ctx
->program
, ctx
->block
);
269 bld
.pseudo(aco_opcode::p_extract_vector
, Definition(dst
), src
, Operand(idx
));
273 Temp
emit_extract_vector(isel_context
* ctx
, Temp src
, uint32_t idx
, RegClass dst_rc
)
275 /* no need to extract the whole vector */
276 if (src
.regClass() == dst_rc
) {
281 assert(src
.bytes() > (idx
* dst_rc
.bytes()));
282 Builder
bld(ctx
->program
, ctx
->block
);
283 auto it
= ctx
->allocated_vec
.find(src
.id());
284 if (it
!= ctx
->allocated_vec
.end() && dst_rc
.bytes() == it
->second
[idx
].regClass().bytes()) {
285 if (it
->second
[idx
].regClass() == dst_rc
) {
286 return it
->second
[idx
];
288 assert(!dst_rc
.is_subdword());
289 assert(dst_rc
.type() == RegType::vgpr
&& it
->second
[idx
].type() == RegType::sgpr
);
290 return bld
.copy(bld
.def(dst_rc
), it
->second
[idx
]);
294 if (dst_rc
.is_subdword())
295 src
= as_vgpr(ctx
, src
);
297 if (src
.bytes() == dst_rc
.bytes()) {
299 return bld
.copy(bld
.def(dst_rc
), src
);
301 Temp dst
= bld
.tmp(dst_rc
);
302 emit_extract_vector(ctx
, src
, idx
, dst
);
307 void emit_split_vector(isel_context
* ctx
, Temp vec_src
, unsigned num_components
)
309 if (num_components
== 1)
311 if (ctx
->allocated_vec
.find(vec_src
.id()) != ctx
->allocated_vec
.end())
314 if (num_components
> vec_src
.size()) {
315 if (vec_src
.type() == RegType::sgpr
) {
316 /* should still help get_alu_src() */
317 emit_split_vector(ctx
, vec_src
, vec_src
.size());
320 /* sub-dword split */
321 rc
= RegClass(RegType::vgpr
, vec_src
.bytes() / num_components
).as_subdword();
323 rc
= RegClass(vec_src
.type(), vec_src
.size() / num_components
);
325 aco_ptr
<Pseudo_instruction
> split
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_split_vector
, Format::PSEUDO
, 1, num_components
)};
326 split
->operands
[0] = Operand(vec_src
);
327 std::array
<Temp
,NIR_MAX_VEC_COMPONENTS
> elems
;
328 for (unsigned i
= 0; i
< num_components
; i
++) {
329 elems
[i
] = {ctx
->program
->allocateId(), rc
};
330 split
->definitions
[i
] = Definition(elems
[i
]);
332 ctx
->block
->instructions
.emplace_back(std::move(split
));
333 ctx
->allocated_vec
.emplace(vec_src
.id(), elems
);
336 /* This vector expansion uses a mask to determine which elements in the new vector
337 * come from the original vector. The other elements are undefined. */
338 void expand_vector(isel_context
* ctx
, Temp vec_src
, Temp dst
, unsigned num_components
, unsigned mask
)
340 emit_split_vector(ctx
, vec_src
, util_bitcount(mask
));
345 Builder
bld(ctx
->program
, ctx
->block
);
346 if (num_components
== 1) {
347 if (dst
.type() == RegType::sgpr
)
348 bld
.pseudo(aco_opcode::p_as_uniform
, Definition(dst
), vec_src
);
350 bld
.copy(Definition(dst
), vec_src
);
354 unsigned component_size
= dst
.size() / num_components
;
355 std::array
<Temp
,NIR_MAX_VEC_COMPONENTS
> elems
;
357 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, num_components
, 1)};
358 vec
->definitions
[0] = Definition(dst
);
360 for (unsigned i
= 0; i
< num_components
; i
++) {
361 if (mask
& (1 << i
)) {
362 Temp src
= emit_extract_vector(ctx
, vec_src
, k
++, RegClass(vec_src
.type(), component_size
));
363 if (dst
.type() == RegType::sgpr
)
364 src
= bld
.as_uniform(src
);
365 vec
->operands
[i
] = Operand(src
);
367 vec
->operands
[i
] = Operand(0u);
369 elems
[i
] = vec
->operands
[i
].getTemp();
371 ctx
->block
->instructions
.emplace_back(std::move(vec
));
372 ctx
->allocated_vec
.emplace(dst
.id(), elems
);
375 /* adjust misaligned small bit size loads */
376 void byte_align_scalar(isel_context
*ctx
, Temp vec
, Operand offset
, Temp dst
)
378 Builder
bld(ctx
->program
, ctx
->block
);
380 Temp select
= Temp();
381 if (offset
.isConstant()) {
382 assert(offset
.constantValue() && offset
.constantValue() < 4);
383 shift
= Operand(offset
.constantValue() * 8);
385 /* bit_offset = 8 * (offset & 0x3) */
386 Temp tmp
= bld
.sop2(aco_opcode::s_and_b32
, bld
.def(s1
), bld
.def(s1
, scc
), offset
, Operand(3u));
387 select
= bld
.tmp(s1
);
388 shift
= bld
.sop2(aco_opcode::s_lshl_b32
, bld
.def(s1
), bld
.scc(Definition(select
)), tmp
, Operand(3u));
391 if (vec
.size() == 1) {
392 bld
.sop2(aco_opcode::s_lshr_b32
, Definition(dst
), bld
.def(s1
, scc
), vec
, shift
);
393 } else if (vec
.size() == 2) {
394 Temp tmp
= dst
.size() == 2 ? dst
: bld
.tmp(s2
);
395 bld
.sop2(aco_opcode::s_lshr_b64
, Definition(tmp
), bld
.def(s1
, scc
), vec
, shift
);
397 emit_split_vector(ctx
, dst
, 2);
399 emit_extract_vector(ctx
, tmp
, 0, dst
);
400 } else if (vec
.size() == 4) {
401 Temp lo
= bld
.tmp(s2
), hi
= bld
.tmp(s2
);
402 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lo
), Definition(hi
), vec
);
403 hi
= bld
.pseudo(aco_opcode::p_extract_vector
, bld
.def(s1
), hi
, Operand(0u));
404 if (select
!= Temp())
405 hi
= bld
.sop2(aco_opcode::s_cselect_b32
, bld
.def(s1
), hi
, Operand(0u), bld
.scc(select
));
406 lo
= bld
.sop2(aco_opcode::s_lshr_b64
, bld
.def(s2
), bld
.def(s1
, scc
), lo
, shift
);
407 Temp mid
= bld
.tmp(s1
);
408 lo
= bld
.pseudo(aco_opcode::p_split_vector
, bld
.def(s1
), Definition(mid
), lo
);
409 hi
= bld
.sop2(aco_opcode::s_lshl_b32
, bld
.def(s1
), bld
.def(s1
, scc
), hi
, shift
);
410 mid
= bld
.sop2(aco_opcode::s_or_b32
, bld
.def(s1
), bld
.def(s1
, scc
), hi
, mid
);
411 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lo
, mid
);
412 emit_split_vector(ctx
, dst
, 2);
416 void byte_align_vector(isel_context
*ctx
, Temp vec
, Operand offset
, Temp dst
, unsigned component_size
)
418 Builder
bld(ctx
->program
, ctx
->block
);
419 if (offset
.isTemp()) {
420 Temp tmp
[4] = {vec
, vec
, vec
, vec
};
422 if (vec
.size() == 4) {
423 tmp
[0] = bld
.tmp(v1
), tmp
[1] = bld
.tmp(v1
), tmp
[2] = bld
.tmp(v1
), tmp
[3] = bld
.tmp(v1
);
424 bld
.pseudo(aco_opcode::p_split_vector
, Definition(tmp
[0]), Definition(tmp
[1]), Definition(tmp
[2]), Definition(tmp
[3]), vec
);
425 } else if (vec
.size() == 3) {
426 tmp
[0] = bld
.tmp(v1
), tmp
[1] = bld
.tmp(v1
), tmp
[2] = bld
.tmp(v1
);
427 bld
.pseudo(aco_opcode::p_split_vector
, Definition(tmp
[0]), Definition(tmp
[1]), Definition(tmp
[2]), vec
);
428 } else if (vec
.size() == 2) {
429 tmp
[0] = bld
.tmp(v1
), tmp
[1] = bld
.tmp(v1
), tmp
[2] = tmp
[1];
430 bld
.pseudo(aco_opcode::p_split_vector
, Definition(tmp
[0]), Definition(tmp
[1]), vec
);
432 for (unsigned i
= 0; i
< dst
.size(); i
++)
433 tmp
[i
] = bld
.vop3(aco_opcode::v_alignbyte_b32
, bld
.def(v1
), tmp
[i
+ 1], tmp
[i
], offset
);
437 vec
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), tmp
[0], tmp
[1]);
439 offset
= Operand(0u);
442 unsigned num_components
= dst
.bytes() / component_size
;
443 if (vec
.regClass() == dst
.regClass()) {
444 assert(offset
.constantValue() == 0);
445 bld
.copy(Definition(dst
), vec
);
446 emit_split_vector(ctx
, dst
, num_components
);
450 emit_split_vector(ctx
, vec
, vec
.bytes() / component_size
);
451 std::array
<Temp
, NIR_MAX_VEC_COMPONENTS
> elems
;
452 RegClass rc
= RegClass(RegType::vgpr
, component_size
).as_subdword();
454 assert(offset
.constantValue() % component_size
== 0);
455 unsigned skip
= offset
.constantValue() / component_size
;
456 for (unsigned i
= 0; i
< num_components
; i
++)
457 elems
[i
] = emit_extract_vector(ctx
, vec
, i
+ skip
, rc
);
459 /* if dst is vgpr - split the src and create a shrunk version according to the mask. */
460 if (dst
.type() == RegType::vgpr
) {
461 aco_ptr
<Pseudo_instruction
> create_vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, num_components
, 1)};
462 for (unsigned i
= 0; i
< num_components
; i
++)
463 create_vec
->operands
[i
] = Operand(elems
[i
]);
464 create_vec
->definitions
[0] = Definition(dst
);
465 bld
.insert(std::move(create_vec
));
467 /* if dst is sgpr - split the src, but move the original to sgpr. */
469 vec
= bld
.pseudo(aco_opcode::p_as_uniform
, bld
.def(RegClass(RegType::sgpr
, vec
.size())), vec
);
470 byte_align_scalar(ctx
, vec
, offset
, dst
);
472 assert(dst
.size() == vec
.size());
473 bld
.pseudo(aco_opcode::p_as_uniform
, Definition(dst
), vec
);
476 ctx
->allocated_vec
.emplace(dst
.id(), elems
);
479 Temp
bool_to_vector_condition(isel_context
*ctx
, Temp val
, Temp dst
= Temp(0, s2
))
481 Builder
bld(ctx
->program
, ctx
->block
);
483 dst
= bld
.tmp(bld
.lm
);
485 assert(val
.regClass() == s1
);
486 assert(dst
.regClass() == bld
.lm
);
488 return bld
.sop2(Builder::s_cselect
, Definition(dst
), Operand((uint32_t) -1), Operand(0u), bld
.scc(val
));
491 Temp
bool_to_scalar_condition(isel_context
*ctx
, Temp val
, Temp dst
= Temp(0, s1
))
493 Builder
bld(ctx
->program
, ctx
->block
);
497 assert(val
.regClass() == bld
.lm
);
498 assert(dst
.regClass() == s1
);
500 /* if we're currently in WQM mode, ensure that the source is also computed in WQM */
501 Temp tmp
= bld
.tmp(s1
);
502 bld
.sop2(Builder::s_and
, bld
.def(bld
.lm
), bld
.scc(Definition(tmp
)), val
, Operand(exec
, bld
.lm
));
503 return emit_wqm(ctx
, tmp
, dst
);
506 Temp
get_alu_src(struct isel_context
*ctx
, nir_alu_src src
, unsigned size
=1)
508 if (src
.src
.ssa
->num_components
== 1 && src
.swizzle
[0] == 0 && size
== 1)
509 return get_ssa_temp(ctx
, src
.src
.ssa
);
511 if (src
.src
.ssa
->num_components
== size
) {
512 bool identity_swizzle
= true;
513 for (unsigned i
= 0; identity_swizzle
&& i
< size
; i
++) {
514 if (src
.swizzle
[i
] != i
)
515 identity_swizzle
= false;
517 if (identity_swizzle
)
518 return get_ssa_temp(ctx
, src
.src
.ssa
);
521 Temp vec
= get_ssa_temp(ctx
, src
.src
.ssa
);
522 unsigned elem_size
= vec
.bytes() / src
.src
.ssa
->num_components
;
523 assert(elem_size
> 0);
524 assert(vec
.bytes() % elem_size
== 0);
526 if (elem_size
< 4 && vec
.type() == RegType::sgpr
) {
527 assert(src
.src
.ssa
->bit_size
== 8 || src
.src
.ssa
->bit_size
== 16);
529 unsigned swizzle
= src
.swizzle
[0];
530 if (vec
.size() > 1) {
531 assert(src
.src
.ssa
->bit_size
== 16);
532 vec
= emit_extract_vector(ctx
, vec
, swizzle
/ 2, s1
);
533 swizzle
= swizzle
& 1;
538 Temp dst
{ctx
->program
->allocateId(), s1
};
539 aco_ptr
<SOP2_instruction
> bfe
{create_instruction
<SOP2_instruction
>(aco_opcode::s_bfe_u32
, Format::SOP2
, 2, 2)};
540 bfe
->operands
[0] = Operand(vec
);
541 bfe
->operands
[1] = Operand(uint32_t((src
.src
.ssa
->bit_size
<< 16) | (src
.src
.ssa
->bit_size
* swizzle
)));
542 bfe
->definitions
[0] = Definition(dst
);
543 bfe
->definitions
[1] = Definition(ctx
->program
->allocateId(), scc
, s1
);
544 ctx
->block
->instructions
.emplace_back(std::move(bfe
));
548 RegClass elem_rc
= elem_size
< 4 ? RegClass(vec
.type(), elem_size
).as_subdword() : RegClass(vec
.type(), elem_size
/ 4);
550 return emit_extract_vector(ctx
, vec
, src
.swizzle
[0], elem_rc
);
553 std::array
<Temp
,NIR_MAX_VEC_COMPONENTS
> elems
;
554 aco_ptr
<Pseudo_instruction
> vec_instr
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, size
, 1)};
555 for (unsigned i
= 0; i
< size
; ++i
) {
556 elems
[i
] = emit_extract_vector(ctx
, vec
, src
.swizzle
[i
], elem_rc
);
557 vec_instr
->operands
[i
] = Operand
{elems
[i
]};
559 Temp dst
{ctx
->program
->allocateId(), RegClass(vec
.type(), elem_size
* size
/ 4)};
560 vec_instr
->definitions
[0] = Definition(dst
);
561 ctx
->block
->instructions
.emplace_back(std::move(vec_instr
));
562 ctx
->allocated_vec
.emplace(dst
.id(), elems
);
567 Temp
convert_pointer_to_64_bit(isel_context
*ctx
, Temp ptr
)
571 Builder
bld(ctx
->program
, ctx
->block
);
572 if (ptr
.type() == RegType::vgpr
)
573 ptr
= bld
.vop1(aco_opcode::v_readfirstlane_b32
, bld
.def(s1
), ptr
);
574 return bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s2
),
575 ptr
, Operand((unsigned)ctx
->options
->address32_hi
));
578 void emit_sop2_instruction(isel_context
*ctx
, nir_alu_instr
*instr
, aco_opcode op
, Temp dst
, bool writes_scc
)
580 aco_ptr
<SOP2_instruction
> sop2
{create_instruction
<SOP2_instruction
>(op
, Format::SOP2
, 2, writes_scc
? 2 : 1)};
581 sop2
->operands
[0] = Operand(get_alu_src(ctx
, instr
->src
[0]));
582 sop2
->operands
[1] = Operand(get_alu_src(ctx
, instr
->src
[1]));
583 sop2
->definitions
[0] = Definition(dst
);
585 sop2
->definitions
[1] = Definition(ctx
->program
->allocateId(), scc
, s1
);
586 ctx
->block
->instructions
.emplace_back(std::move(sop2
));
589 void emit_vop2_instruction(isel_context
*ctx
, nir_alu_instr
*instr
, aco_opcode op
, Temp dst
,
590 bool commutative
, bool swap_srcs
=false, bool flush_denorms
= false)
592 Builder
bld(ctx
->program
, ctx
->block
);
593 bld
.is_precise
= instr
->exact
;
595 Temp src0
= get_alu_src(ctx
, instr
->src
[swap_srcs
? 1 : 0]);
596 Temp src1
= get_alu_src(ctx
, instr
->src
[swap_srcs
? 0 : 1]);
597 if (src1
.type() == RegType::sgpr
) {
598 if (commutative
&& src0
.type() == RegType::vgpr
) {
603 src1
= as_vgpr(ctx
, src1
);
607 if (flush_denorms
&& ctx
->program
->chip_class
< GFX9
) {
608 assert(dst
.size() == 1);
609 Temp tmp
= bld
.vop2(op
, bld
.def(v1
), src0
, src1
);
610 bld
.vop2(aco_opcode::v_mul_f32
, Definition(dst
), Operand(0x3f800000u
), tmp
);
612 bld
.vop2(op
, Definition(dst
), src0
, src1
);
616 void emit_vop2_instruction_logic64(isel_context
*ctx
, nir_alu_instr
*instr
,
617 aco_opcode op
, Temp dst
)
619 Builder
bld(ctx
->program
, ctx
->block
);
620 bld
.is_precise
= instr
->exact
;
622 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
623 Temp src1
= get_alu_src(ctx
, instr
->src
[1]);
625 if (src1
.type() == RegType::sgpr
) {
626 assert(src0
.type() == RegType::vgpr
);
627 std::swap(src0
, src1
);
630 Temp src00
= bld
.tmp(src0
.type(), 1);
631 Temp src01
= bld
.tmp(src0
.type(), 1);
632 bld
.pseudo(aco_opcode::p_split_vector
, Definition(src00
), Definition(src01
), src0
);
633 Temp src10
= bld
.tmp(v1
);
634 Temp src11
= bld
.tmp(v1
);
635 bld
.pseudo(aco_opcode::p_split_vector
, Definition(src10
), Definition(src11
), src1
);
636 Temp lo
= bld
.vop2(op
, bld
.def(v1
), src00
, src10
);
637 Temp hi
= bld
.vop2(op
, bld
.def(v1
), src01
, src11
);
638 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lo
, hi
);
641 void emit_vop3a_instruction(isel_context
*ctx
, nir_alu_instr
*instr
, aco_opcode op
, Temp dst
,
642 bool flush_denorms
= false)
644 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
645 Temp src1
= get_alu_src(ctx
, instr
->src
[1]);
646 Temp src2
= get_alu_src(ctx
, instr
->src
[2]);
648 /* ensure that the instruction has at most 1 sgpr operand
649 * The optimizer will inline constants for us */
650 if (src0
.type() == RegType::sgpr
&& src1
.type() == RegType::sgpr
)
651 src0
= as_vgpr(ctx
, src0
);
652 if (src1
.type() == RegType::sgpr
&& src2
.type() == RegType::sgpr
)
653 src1
= as_vgpr(ctx
, src1
);
654 if (src2
.type() == RegType::sgpr
&& src0
.type() == RegType::sgpr
)
655 src2
= as_vgpr(ctx
, src2
);
657 Builder
bld(ctx
->program
, ctx
->block
);
658 bld
.is_precise
= instr
->exact
;
659 if (flush_denorms
&& ctx
->program
->chip_class
< GFX9
) {
660 assert(dst
.size() == 1);
661 Temp tmp
= bld
.vop3(op
, Definition(dst
), src0
, src1
, src2
);
662 bld
.vop2(aco_opcode::v_mul_f32
, Definition(dst
), Operand(0x3f800000u
), tmp
);
664 bld
.vop3(op
, Definition(dst
), src0
, src1
, src2
);
668 void emit_vop1_instruction(isel_context
*ctx
, nir_alu_instr
*instr
, aco_opcode op
, Temp dst
)
670 Builder
bld(ctx
->program
, ctx
->block
);
671 bld
.is_precise
= instr
->exact
;
672 if (dst
.type() == RegType::sgpr
)
673 bld
.pseudo(aco_opcode::p_as_uniform
, Definition(dst
),
674 bld
.vop1(op
, bld
.def(RegType::vgpr
, dst
.size()), get_alu_src(ctx
, instr
->src
[0])));
676 bld
.vop1(op
, Definition(dst
), get_alu_src(ctx
, instr
->src
[0]));
679 void emit_vopc_instruction(isel_context
*ctx
, nir_alu_instr
*instr
, aco_opcode op
, Temp dst
)
681 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
682 Temp src1
= get_alu_src(ctx
, instr
->src
[1]);
683 assert(src0
.size() == src1
.size());
685 aco_ptr
<Instruction
> vopc
;
686 if (src1
.type() == RegType::sgpr
) {
687 if (src0
.type() == RegType::vgpr
) {
688 /* to swap the operands, we might also have to change the opcode */
690 case aco_opcode::v_cmp_lt_f16
:
691 op
= aco_opcode::v_cmp_gt_f16
;
693 case aco_opcode::v_cmp_ge_f16
:
694 op
= aco_opcode::v_cmp_le_f16
;
696 case aco_opcode::v_cmp_lt_i16
:
697 op
= aco_opcode::v_cmp_gt_i16
;
699 case aco_opcode::v_cmp_ge_i16
:
700 op
= aco_opcode::v_cmp_le_i16
;
702 case aco_opcode::v_cmp_lt_u16
:
703 op
= aco_opcode::v_cmp_gt_u16
;
705 case aco_opcode::v_cmp_ge_u16
:
706 op
= aco_opcode::v_cmp_le_u16
;
708 case aco_opcode::v_cmp_lt_f32
:
709 op
= aco_opcode::v_cmp_gt_f32
;
711 case aco_opcode::v_cmp_ge_f32
:
712 op
= aco_opcode::v_cmp_le_f32
;
714 case aco_opcode::v_cmp_lt_i32
:
715 op
= aco_opcode::v_cmp_gt_i32
;
717 case aco_opcode::v_cmp_ge_i32
:
718 op
= aco_opcode::v_cmp_le_i32
;
720 case aco_opcode::v_cmp_lt_u32
:
721 op
= aco_opcode::v_cmp_gt_u32
;
723 case aco_opcode::v_cmp_ge_u32
:
724 op
= aco_opcode::v_cmp_le_u32
;
726 case aco_opcode::v_cmp_lt_f64
:
727 op
= aco_opcode::v_cmp_gt_f64
;
729 case aco_opcode::v_cmp_ge_f64
:
730 op
= aco_opcode::v_cmp_le_f64
;
732 case aco_opcode::v_cmp_lt_i64
:
733 op
= aco_opcode::v_cmp_gt_i64
;
735 case aco_opcode::v_cmp_ge_i64
:
736 op
= aco_opcode::v_cmp_le_i64
;
738 case aco_opcode::v_cmp_lt_u64
:
739 op
= aco_opcode::v_cmp_gt_u64
;
741 case aco_opcode::v_cmp_ge_u64
:
742 op
= aco_opcode::v_cmp_le_u64
;
744 default: /* eq and ne are commutative */
751 src1
= as_vgpr(ctx
, src1
);
755 Builder
bld(ctx
->program
, ctx
->block
);
756 bld
.vopc(op
, bld
.hint_vcc(Definition(dst
)), src0
, src1
);
759 void emit_sopc_instruction(isel_context
*ctx
, nir_alu_instr
*instr
, aco_opcode op
, Temp dst
)
761 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
762 Temp src1
= get_alu_src(ctx
, instr
->src
[1]);
763 Builder
bld(ctx
->program
, ctx
->block
);
765 assert(dst
.regClass() == bld
.lm
);
766 assert(src0
.type() == RegType::sgpr
);
767 assert(src1
.type() == RegType::sgpr
);
768 assert(src0
.regClass() == src1
.regClass());
770 /* Emit the SALU comparison instruction */
771 Temp cmp
= bld
.sopc(op
, bld
.scc(bld
.def(s1
)), src0
, src1
);
772 /* Turn the result into a per-lane bool */
773 bool_to_vector_condition(ctx
, cmp
, dst
);
776 void emit_comparison(isel_context
*ctx
, nir_alu_instr
*instr
, Temp dst
,
777 aco_opcode v16_op
, aco_opcode v32_op
, aco_opcode v64_op
, aco_opcode s32_op
= aco_opcode::num_opcodes
, aco_opcode s64_op
= aco_opcode::num_opcodes
)
779 aco_opcode s_op
= instr
->src
[0].src
.ssa
->bit_size
== 64 ? s64_op
: instr
->src
[0].src
.ssa
->bit_size
== 32 ? s32_op
: aco_opcode::num_opcodes
;
780 aco_opcode v_op
= instr
->src
[0].src
.ssa
->bit_size
== 64 ? v64_op
: instr
->src
[0].src
.ssa
->bit_size
== 32 ? v32_op
: v16_op
;
781 bool use_valu
= s_op
== aco_opcode::num_opcodes
||
782 nir_dest_is_divergent(instr
->dest
.dest
) ||
783 ctx
->allocated
[instr
->src
[0].src
.ssa
->index
].type() == RegType::vgpr
||
784 ctx
->allocated
[instr
->src
[1].src
.ssa
->index
].type() == RegType::vgpr
;
785 aco_opcode op
= use_valu
? v_op
: s_op
;
786 assert(op
!= aco_opcode::num_opcodes
);
787 assert(dst
.regClass() == ctx
->program
->lane_mask
);
790 emit_vopc_instruction(ctx
, instr
, op
, dst
);
792 emit_sopc_instruction(ctx
, instr
, op
, dst
);
795 void emit_boolean_logic(isel_context
*ctx
, nir_alu_instr
*instr
, Builder::WaveSpecificOpcode op
, Temp dst
)
797 Builder
bld(ctx
->program
, ctx
->block
);
798 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
799 Temp src1
= get_alu_src(ctx
, instr
->src
[1]);
801 assert(dst
.regClass() == bld
.lm
);
802 assert(src0
.regClass() == bld
.lm
);
803 assert(src1
.regClass() == bld
.lm
);
805 bld
.sop2(op
, Definition(dst
), bld
.def(s1
, scc
), src0
, src1
);
808 void emit_bcsel(isel_context
*ctx
, nir_alu_instr
*instr
, Temp dst
)
810 Builder
bld(ctx
->program
, ctx
->block
);
811 Temp cond
= get_alu_src(ctx
, instr
->src
[0]);
812 Temp then
= get_alu_src(ctx
, instr
->src
[1]);
813 Temp els
= get_alu_src(ctx
, instr
->src
[2]);
815 assert(cond
.regClass() == bld
.lm
);
817 if (dst
.type() == RegType::vgpr
) {
818 aco_ptr
<Instruction
> bcsel
;
819 if (dst
.size() == 1) {
820 then
= as_vgpr(ctx
, then
);
821 els
= as_vgpr(ctx
, els
);
823 bld
.vop2(aco_opcode::v_cndmask_b32
, Definition(dst
), els
, then
, cond
);
824 } else if (dst
.size() == 2) {
825 Temp then_lo
= bld
.tmp(v1
), then_hi
= bld
.tmp(v1
);
826 bld
.pseudo(aco_opcode::p_split_vector
, Definition(then_lo
), Definition(then_hi
), then
);
827 Temp else_lo
= bld
.tmp(v1
), else_hi
= bld
.tmp(v1
);
828 bld
.pseudo(aco_opcode::p_split_vector
, Definition(else_lo
), Definition(else_hi
), els
);
830 Temp dst0
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), else_lo
, then_lo
, cond
);
831 Temp dst1
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), else_hi
, then_hi
, cond
);
833 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), dst0
, dst1
);
835 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
836 nir_print_instr(&instr
->instr
, stderr
);
837 fprintf(stderr
, "\n");
842 if (instr
->dest
.dest
.ssa
.bit_size
== 1) {
843 assert(dst
.regClass() == bld
.lm
);
844 assert(then
.regClass() == bld
.lm
);
845 assert(els
.regClass() == bld
.lm
);
848 if (!nir_src_is_divergent(instr
->src
[0].src
)) { /* uniform condition and values in sgpr */
849 if (dst
.regClass() == s1
|| dst
.regClass() == s2
) {
850 assert((then
.regClass() == s1
|| then
.regClass() == s2
) && els
.regClass() == then
.regClass());
851 assert(dst
.size() == then
.size());
852 aco_opcode op
= dst
.regClass() == s1
? aco_opcode::s_cselect_b32
: aco_opcode::s_cselect_b64
;
853 bld
.sop2(op
, Definition(dst
), then
, els
, bld
.scc(bool_to_scalar_condition(ctx
, cond
)));
855 fprintf(stderr
, "Unimplemented uniform bcsel bit size: ");
856 nir_print_instr(&instr
->instr
, stderr
);
857 fprintf(stderr
, "\n");
862 /* divergent boolean bcsel
863 * this implements bcsel on bools: dst = s0 ? s1 : s2
864 * are going to be: dst = (s0 & s1) | (~s0 & s2) */
865 assert(instr
->dest
.dest
.ssa
.bit_size
== 1);
867 if (cond
.id() != then
.id())
868 then
= bld
.sop2(Builder::s_and
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), cond
, then
);
870 if (cond
.id() == els
.id())
871 bld
.sop1(Builder::s_mov
, Definition(dst
), then
);
873 bld
.sop2(Builder::s_or
, Definition(dst
), bld
.def(s1
, scc
), then
,
874 bld
.sop2(Builder::s_andn2
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), els
, cond
));
877 void emit_scaled_op(isel_context
*ctx
, Builder
& bld
, Definition dst
, Temp val
,
878 aco_opcode op
, uint32_t undo
)
880 /* multiply by 16777216 to handle denormals */
881 Temp is_denormal
= bld
.vopc(aco_opcode::v_cmp_class_f32
, bld
.hint_vcc(bld
.def(bld
.lm
)),
882 as_vgpr(ctx
, val
), bld
.copy(bld
.def(v1
), Operand((1u << 7) | (1u << 4))));
883 Temp scaled
= bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), Operand(0x4b800000u
), val
);
884 scaled
= bld
.vop1(op
, bld
.def(v1
), scaled
);
885 scaled
= bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), Operand(undo
), scaled
);
887 Temp not_scaled
= bld
.vop1(op
, bld
.def(v1
), val
);
889 bld
.vop2(aco_opcode::v_cndmask_b32
, dst
, not_scaled
, scaled
, is_denormal
);
892 void emit_rcp(isel_context
*ctx
, Builder
& bld
, Definition dst
, Temp val
)
894 if (ctx
->block
->fp_mode
.denorm32
== 0) {
895 bld
.vop1(aco_opcode::v_rcp_f32
, dst
, val
);
899 emit_scaled_op(ctx
, bld
, dst
, val
, aco_opcode::v_rcp_f32
, 0x4b800000u
);
902 void emit_rsq(isel_context
*ctx
, Builder
& bld
, Definition dst
, Temp val
)
904 if (ctx
->block
->fp_mode
.denorm32
== 0) {
905 bld
.vop1(aco_opcode::v_rsq_f32
, dst
, val
);
909 emit_scaled_op(ctx
, bld
, dst
, val
, aco_opcode::v_rsq_f32
, 0x45800000u
);
912 void emit_sqrt(isel_context
*ctx
, Builder
& bld
, Definition dst
, Temp val
)
914 if (ctx
->block
->fp_mode
.denorm32
== 0) {
915 bld
.vop1(aco_opcode::v_sqrt_f32
, dst
, val
);
919 emit_scaled_op(ctx
, bld
, dst
, val
, aco_opcode::v_sqrt_f32
, 0x39800000u
);
922 void emit_log2(isel_context
*ctx
, Builder
& bld
, Definition dst
, Temp val
)
924 if (ctx
->block
->fp_mode
.denorm32
== 0) {
925 bld
.vop1(aco_opcode::v_log_f32
, dst
, val
);
929 emit_scaled_op(ctx
, bld
, dst
, val
, aco_opcode::v_log_f32
, 0xc1c00000u
);
932 Temp
emit_trunc_f64(isel_context
*ctx
, Builder
& bld
, Definition dst
, Temp val
)
934 if (ctx
->options
->chip_class
>= GFX7
)
935 return bld
.vop1(aco_opcode::v_trunc_f64
, Definition(dst
), val
);
937 /* GFX6 doesn't support V_TRUNC_F64, lower it. */
938 /* TODO: create more efficient code! */
939 if (val
.type() == RegType::sgpr
)
940 val
= as_vgpr(ctx
, val
);
942 /* Split the input value. */
943 Temp val_lo
= bld
.tmp(v1
), val_hi
= bld
.tmp(v1
);
944 bld
.pseudo(aco_opcode::p_split_vector
, Definition(val_lo
), Definition(val_hi
), val
);
946 /* Extract the exponent and compute the unbiased value. */
947 Temp exponent
= bld
.vop3(aco_opcode::v_bfe_u32
, bld
.def(v1
), val_hi
, Operand(20u), Operand(11u));
948 exponent
= bld
.vsub32(bld
.def(v1
), exponent
, Operand(1023u));
950 /* Extract the fractional part. */
951 Temp fract_mask
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), Operand(-1u), Operand(0x000fffffu
));
952 fract_mask
= bld
.vop3(aco_opcode::v_lshr_b64
, bld
.def(v2
), fract_mask
, exponent
);
954 Temp fract_mask_lo
= bld
.tmp(v1
), fract_mask_hi
= bld
.tmp(v1
);
955 bld
.pseudo(aco_opcode::p_split_vector
, Definition(fract_mask_lo
), Definition(fract_mask_hi
), fract_mask
);
957 Temp fract_lo
= bld
.tmp(v1
), fract_hi
= bld
.tmp(v1
);
958 Temp tmp
= bld
.vop1(aco_opcode::v_not_b32
, bld
.def(v1
), fract_mask_lo
);
959 fract_lo
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), val_lo
, tmp
);
960 tmp
= bld
.vop1(aco_opcode::v_not_b32
, bld
.def(v1
), fract_mask_hi
);
961 fract_hi
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), val_hi
, tmp
);
963 /* Get the sign bit. */
964 Temp sign
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(0x80000000u
), val_hi
);
966 /* Decide the operation to apply depending on the unbiased exponent. */
967 Temp exp_lt0
= bld
.vopc_e64(aco_opcode::v_cmp_lt_i32
, bld
.hint_vcc(bld
.def(bld
.lm
)), exponent
, Operand(0u));
968 Temp dst_lo
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), fract_lo
, bld
.copy(bld
.def(v1
), Operand(0u)), exp_lt0
);
969 Temp dst_hi
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), fract_hi
, sign
, exp_lt0
);
970 Temp exp_gt51
= bld
.vopc_e64(aco_opcode::v_cmp_gt_i32
, bld
.def(s2
), exponent
, Operand(51u));
971 dst_lo
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), dst_lo
, val_lo
, exp_gt51
);
972 dst_hi
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), dst_hi
, val_hi
, exp_gt51
);
974 return bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), dst_lo
, dst_hi
);
977 Temp
emit_floor_f64(isel_context
*ctx
, Builder
& bld
, Definition dst
, Temp val
)
979 if (ctx
->options
->chip_class
>= GFX7
)
980 return bld
.vop1(aco_opcode::v_floor_f64
, Definition(dst
), val
);
982 /* GFX6 doesn't support V_FLOOR_F64, lower it. */
983 Temp src0
= as_vgpr(ctx
, val
);
985 Temp mask
= bld
.copy(bld
.def(s1
), Operand(3u)); /* isnan */
986 Temp min_val
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s2
), Operand(-1u), Operand(0x3fefffffu
));
988 Temp isnan
= bld
.vopc_e64(aco_opcode::v_cmp_class_f64
, bld
.hint_vcc(bld
.def(bld
.lm
)), src0
, mask
);
989 Temp fract
= bld
.vop1(aco_opcode::v_fract_f64
, bld
.def(v2
), src0
);
990 Temp min
= bld
.vop3(aco_opcode::v_min_f64
, bld
.def(v2
), fract
, min_val
);
992 Temp then_lo
= bld
.tmp(v1
), then_hi
= bld
.tmp(v1
);
993 bld
.pseudo(aco_opcode::p_split_vector
, Definition(then_lo
), Definition(then_hi
), src0
);
994 Temp else_lo
= bld
.tmp(v1
), else_hi
= bld
.tmp(v1
);
995 bld
.pseudo(aco_opcode::p_split_vector
, Definition(else_lo
), Definition(else_hi
), min
);
997 Temp dst0
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), else_lo
, then_lo
, isnan
);
998 Temp dst1
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), else_hi
, then_hi
, isnan
);
1000 Temp v
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), dst0
, dst1
);
1002 Instruction
* add
= bld
.vop3(aco_opcode::v_add_f64
, Definition(dst
), src0
, v
);
1003 static_cast<VOP3A_instruction
*>(add
)->neg
[1] = true;
1005 return add
->definitions
[0].getTemp();
1008 Temp
convert_int(isel_context
*ctx
, Builder
& bld
, Temp src
, unsigned src_bits
, unsigned dst_bits
, bool is_signed
, Temp dst
=Temp()) {
1010 if (dst_bits
% 32 == 0 || src
.type() == RegType::sgpr
)
1011 dst
= bld
.tmp(src
.type(), DIV_ROUND_UP(dst_bits
, 32u));
1013 dst
= bld
.tmp(RegClass(RegType::vgpr
, dst_bits
/ 8u).as_subdword());
1016 if (dst
.bytes() == src
.bytes() && dst_bits
< src_bits
)
1017 return bld
.copy(Definition(dst
), src
);
1018 else if (dst
.bytes() < src
.bytes())
1019 return bld
.pseudo(aco_opcode::p_extract_vector
, Definition(dst
), src
, Operand(0u));
1023 tmp
= src_bits
== 32 ? src
: bld
.tmp(src
.type(), 1);
1026 } else if (src
.regClass() == s1
) {
1028 bld
.sop1(src_bits
== 8 ? aco_opcode::s_sext_i32_i8
: aco_opcode::s_sext_i32_i16
, Definition(tmp
), src
);
1030 bld
.sop2(aco_opcode::s_and_b32
, Definition(tmp
), bld
.def(s1
, scc
), Operand(src_bits
== 8 ? 0xFFu
: 0xFFFFu
), src
);
1031 } else if (ctx
->options
->chip_class
>= GFX8
) {
1032 assert(src_bits
!= 8 || src
.regClass() == v1b
);
1033 assert(src_bits
!= 16 || src
.regClass() == v2b
);
1034 aco_ptr
<SDWA_instruction
> sdwa
{create_instruction
<SDWA_instruction
>(aco_opcode::v_mov_b32
, asSDWA(Format::VOP1
), 1, 1)};
1035 sdwa
->operands
[0] = Operand(src
);
1036 sdwa
->definitions
[0] = Definition(tmp
);
1038 sdwa
->sel
[0] = src_bits
== 8 ? sdwa_sbyte
: sdwa_sword
;
1040 sdwa
->sel
[0] = src_bits
== 8 ? sdwa_ubyte
: sdwa_uword
;
1041 sdwa
->dst_sel
= tmp
.bytes() == 2 ? sdwa_uword
: sdwa_udword
;
1042 bld
.insert(std::move(sdwa
));
1044 assert(ctx
->options
->chip_class
== GFX6
|| ctx
->options
->chip_class
== GFX7
);
1045 aco_opcode opcode
= is_signed
? aco_opcode::v_bfe_i32
: aco_opcode::v_bfe_u32
;
1046 bld
.vop3(opcode
, Definition(tmp
), src
, Operand(0u), Operand(src_bits
== 8 ? 8u : 16u));
1049 if (dst_bits
== 64) {
1050 if (is_signed
&& dst
.regClass() == s2
) {
1051 Temp high
= bld
.sop2(aco_opcode::s_ashr_i32
, bld
.def(s1
), bld
.def(s1
, scc
), tmp
, Operand(31u));
1052 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), tmp
, high
);
1053 } else if (is_signed
&& dst
.regClass() == v2
) {
1054 Temp high
= bld
.vop2(aco_opcode::v_ashrrev_i32
, bld
.def(v1
), Operand(31u), tmp
);
1055 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), tmp
, high
);
1057 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), tmp
, Operand(0u));
1064 void visit_alu_instr(isel_context
*ctx
, nir_alu_instr
*instr
)
1066 if (!instr
->dest
.dest
.is_ssa
) {
1067 fprintf(stderr
, "nir alu dst not in ssa: ");
1068 nir_print_instr(&instr
->instr
, stderr
);
1069 fprintf(stderr
, "\n");
1072 Builder
bld(ctx
->program
, ctx
->block
);
1073 bld
.is_precise
= instr
->exact
;
1074 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.dest
.ssa
);
1079 std::array
<Temp
,NIR_MAX_VEC_COMPONENTS
> elems
;
1080 unsigned num
= instr
->dest
.dest
.ssa
.num_components
;
1081 for (unsigned i
= 0; i
< num
; ++i
)
1082 elems
[i
] = get_alu_src(ctx
, instr
->src
[i
]);
1084 if (instr
->dest
.dest
.ssa
.bit_size
>= 32 || dst
.type() == RegType::vgpr
) {
1085 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, instr
->dest
.dest
.ssa
.num_components
, 1)};
1086 RegClass elem_rc
= RegClass::get(RegType::vgpr
, instr
->dest
.dest
.ssa
.bit_size
/ 8u);
1087 for (unsigned i
= 0; i
< num
; ++i
) {
1088 if (elems
[i
].type() == RegType::sgpr
&& elem_rc
.is_subdword())
1089 vec
->operands
[i
] = Operand(emit_extract_vector(ctx
, elems
[i
], 0, elem_rc
));
1091 vec
->operands
[i
] = Operand
{elems
[i
]};
1093 vec
->definitions
[0] = Definition(dst
);
1094 ctx
->block
->instructions
.emplace_back(std::move(vec
));
1095 ctx
->allocated_vec
.emplace(dst
.id(), elems
);
1097 // TODO: that is a bit suboptimal..
1098 Temp mask
= bld
.copy(bld
.def(s1
), Operand((1u << instr
->dest
.dest
.ssa
.bit_size
) - 1));
1099 for (unsigned i
= 0; i
< num
- 1; ++i
)
1100 if (((i
+1) * instr
->dest
.dest
.ssa
.bit_size
) % 32)
1101 elems
[i
] = bld
.sop2(aco_opcode::s_and_b32
, bld
.def(s1
), bld
.def(s1
, scc
), elems
[i
], mask
);
1102 for (unsigned i
= 0; i
< num
; ++i
) {
1103 unsigned bit
= i
* instr
->dest
.dest
.ssa
.bit_size
;
1104 if (bit
% 32 == 0) {
1105 elems
[bit
/ 32] = elems
[i
];
1107 elems
[i
] = bld
.sop2(aco_opcode::s_lshl_b32
, bld
.def(s1
), bld
.def(s1
, scc
),
1108 elems
[i
], Operand((i
* instr
->dest
.dest
.ssa
.bit_size
) % 32));
1109 elems
[bit
/ 32] = bld
.sop2(aco_opcode::s_or_b32
, bld
.def(s1
), bld
.def(s1
, scc
), elems
[bit
/ 32], elems
[i
]);
1112 if (dst
.size() == 1)
1113 bld
.copy(Definition(dst
), elems
[0]);
1115 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), elems
[0], elems
[1]);
1120 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
1121 aco_ptr
<Instruction
> mov
;
1122 if (dst
.type() == RegType::sgpr
) {
1123 if (src
.type() == RegType::vgpr
)
1124 bld
.pseudo(aco_opcode::p_as_uniform
, Definition(dst
), src
);
1125 else if (src
.regClass() == s1
)
1126 bld
.sop1(aco_opcode::s_mov_b32
, Definition(dst
), src
);
1127 else if (src
.regClass() == s2
)
1128 bld
.sop1(aco_opcode::s_mov_b64
, Definition(dst
), src
);
1130 unreachable("wrong src register class for nir_op_imov");
1132 if (dst
.regClass() == v1
)
1133 bld
.vop1(aco_opcode::v_mov_b32
, Definition(dst
), src
);
1134 else if (dst
.regClass() == v1b
||
1135 dst
.regClass() == v2b
||
1136 dst
.regClass() == v2
)
1137 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), src
);
1139 unreachable("wrong src register class for nir_op_imov");
1144 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
1145 if (instr
->dest
.dest
.ssa
.bit_size
== 1) {
1146 assert(src
.regClass() == bld
.lm
);
1147 assert(dst
.regClass() == bld
.lm
);
1148 /* Don't use s_andn2 here, this allows the optimizer to make a better decision */
1149 Temp tmp
= bld
.sop1(Builder::s_not
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), src
);
1150 bld
.sop2(Builder::s_and
, Definition(dst
), bld
.def(s1
, scc
), tmp
, Operand(exec
, bld
.lm
));
1151 } else if (dst
.regClass() == v1
) {
1152 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_not_b32
, dst
);
1153 } else if (dst
.regClass() == v2
) {
1154 Temp lo
= bld
.tmp(v1
), hi
= bld
.tmp(v1
);
1155 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lo
), Definition(hi
), src
);
1156 lo
= bld
.vop1(aco_opcode::v_not_b32
, bld
.def(v1
), lo
);
1157 hi
= bld
.vop1(aco_opcode::v_not_b32
, bld
.def(v1
), hi
);
1158 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lo
, hi
);
1159 } else if (dst
.type() == RegType::sgpr
) {
1160 aco_opcode opcode
= dst
.size() == 1 ? aco_opcode::s_not_b32
: aco_opcode::s_not_b64
;
1161 bld
.sop1(opcode
, Definition(dst
), bld
.def(s1
, scc
), src
);
1163 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1164 nir_print_instr(&instr
->instr
, stderr
);
1165 fprintf(stderr
, "\n");
1170 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
1171 if (dst
.regClass() == v1
) {
1172 bld
.vsub32(Definition(dst
), Operand(0u), Operand(src
));
1173 } else if (dst
.regClass() == s1
) {
1174 bld
.sop2(aco_opcode::s_mul_i32
, Definition(dst
), Operand((uint32_t) -1), src
);
1175 } else if (dst
.size() == 2) {
1176 Temp src0
= bld
.tmp(dst
.type(), 1);
1177 Temp src1
= bld
.tmp(dst
.type(), 1);
1178 bld
.pseudo(aco_opcode::p_split_vector
, Definition(src0
), Definition(src1
), src
);
1180 if (dst
.regClass() == s2
) {
1181 Temp carry
= bld
.tmp(s1
);
1182 Temp dst0
= bld
.sop2(aco_opcode::s_sub_u32
, bld
.def(s1
), bld
.scc(Definition(carry
)), Operand(0u), src0
);
1183 Temp dst1
= bld
.sop2(aco_opcode::s_subb_u32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(0u), src1
, carry
);
1184 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), dst0
, dst1
);
1186 Temp lower
= bld
.tmp(v1
);
1187 Temp borrow
= bld
.vsub32(Definition(lower
), Operand(0u), src0
, true).def(1).getTemp();
1188 Temp upper
= bld
.vsub32(bld
.def(v1
), Operand(0u), src1
, false, borrow
);
1189 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lower
, upper
);
1192 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1193 nir_print_instr(&instr
->instr
, stderr
);
1194 fprintf(stderr
, "\n");
1199 if (dst
.regClass() == s1
) {
1200 bld
.sop1(aco_opcode::s_abs_i32
, Definition(dst
), bld
.def(s1
, scc
), get_alu_src(ctx
, instr
->src
[0]));
1201 } else if (dst
.regClass() == v1
) {
1202 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
1203 bld
.vop2(aco_opcode::v_max_i32
, Definition(dst
), src
, bld
.vsub32(bld
.def(v1
), Operand(0u), src
));
1205 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1206 nir_print_instr(&instr
->instr
, stderr
);
1207 fprintf(stderr
, "\n");
1211 case nir_op_isign
: {
1212 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
1213 if (dst
.regClass() == s1
) {
1214 Temp tmp
= bld
.sop2(aco_opcode::s_max_i32
, bld
.def(s1
), bld
.def(s1
, scc
), src
, Operand((uint32_t)-1));
1215 bld
.sop2(aco_opcode::s_min_i32
, Definition(dst
), bld
.def(s1
, scc
), tmp
, Operand(1u));
1216 } else if (dst
.regClass() == s2
) {
1217 Temp neg
= bld
.sop2(aco_opcode::s_ashr_i64
, bld
.def(s2
), bld
.def(s1
, scc
), src
, Operand(63u));
1219 if (ctx
->program
->chip_class
>= GFX8
)
1220 neqz
= bld
.sopc(aco_opcode::s_cmp_lg_u64
, bld
.def(s1
, scc
), src
, Operand(0u));
1222 neqz
= bld
.sop2(aco_opcode::s_or_b64
, bld
.def(s2
), bld
.def(s1
, scc
), src
, Operand(0u)).def(1).getTemp();
1223 /* SCC gets zero-extended to 64 bit */
1224 bld
.sop2(aco_opcode::s_or_b64
, Definition(dst
), bld
.def(s1
, scc
), neg
, bld
.scc(neqz
));
1225 } else if (dst
.regClass() == v1
) {
1226 bld
.vop3(aco_opcode::v_med3_i32
, Definition(dst
), Operand((uint32_t)-1), src
, Operand(1u));
1227 } else if (dst
.regClass() == v2
) {
1228 Temp upper
= emit_extract_vector(ctx
, src
, 1, v1
);
1229 Temp neg
= bld
.vop2(aco_opcode::v_ashrrev_i32
, bld
.def(v1
), Operand(31u), upper
);
1230 Temp gtz
= bld
.vopc(aco_opcode::v_cmp_ge_i64
, bld
.hint_vcc(bld
.def(bld
.lm
)), Operand(0u), src
);
1231 Temp lower
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), Operand(1u), neg
, gtz
);
1232 upper
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), Operand(0u), neg
, gtz
);
1233 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lower
, upper
);
1235 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1236 nir_print_instr(&instr
->instr
, stderr
);
1237 fprintf(stderr
, "\n");
1242 if (dst
.regClass() == v1
) {
1243 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_max_i32
, dst
, true);
1244 } else if (dst
.regClass() == s1
) {
1245 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_max_i32
, dst
, true);
1247 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1248 nir_print_instr(&instr
->instr
, stderr
);
1249 fprintf(stderr
, "\n");
1254 if (dst
.regClass() == v1
) {
1255 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_max_u32
, dst
, true);
1256 } else if (dst
.regClass() == s1
) {
1257 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_max_u32
, dst
, true);
1259 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1260 nir_print_instr(&instr
->instr
, stderr
);
1261 fprintf(stderr
, "\n");
1266 if (dst
.regClass() == v1
) {
1267 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_min_i32
, dst
, true);
1268 } else if (dst
.regClass() == s1
) {
1269 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_min_i32
, dst
, true);
1271 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1272 nir_print_instr(&instr
->instr
, stderr
);
1273 fprintf(stderr
, "\n");
1278 if (dst
.regClass() == v1
) {
1279 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_min_u32
, dst
, true);
1280 } else if (dst
.regClass() == s1
) {
1281 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_min_u32
, dst
, true);
1283 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1284 nir_print_instr(&instr
->instr
, stderr
);
1285 fprintf(stderr
, "\n");
1290 if (instr
->dest
.dest
.ssa
.bit_size
== 1) {
1291 emit_boolean_logic(ctx
, instr
, Builder::s_or
, dst
);
1292 } else if (dst
.regClass() == v1
) {
1293 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_or_b32
, dst
, true);
1294 } else if (dst
.regClass() == v2
) {
1295 emit_vop2_instruction_logic64(ctx
, instr
, aco_opcode::v_or_b32
, dst
);
1296 } else if (dst
.regClass() == s1
) {
1297 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_or_b32
, dst
, true);
1298 } else if (dst
.regClass() == s2
) {
1299 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_or_b64
, dst
, true);
1301 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1302 nir_print_instr(&instr
->instr
, stderr
);
1303 fprintf(stderr
, "\n");
1308 if (instr
->dest
.dest
.ssa
.bit_size
== 1) {
1309 emit_boolean_logic(ctx
, instr
, Builder::s_and
, dst
);
1310 } else if (dst
.regClass() == v1
) {
1311 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_and_b32
, dst
, true);
1312 } else if (dst
.regClass() == v2
) {
1313 emit_vop2_instruction_logic64(ctx
, instr
, aco_opcode::v_and_b32
, dst
);
1314 } else if (dst
.regClass() == s1
) {
1315 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_and_b32
, dst
, true);
1316 } else if (dst
.regClass() == s2
) {
1317 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_and_b64
, dst
, true);
1319 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1320 nir_print_instr(&instr
->instr
, stderr
);
1321 fprintf(stderr
, "\n");
1326 if (instr
->dest
.dest
.ssa
.bit_size
== 1) {
1327 emit_boolean_logic(ctx
, instr
, Builder::s_xor
, dst
);
1328 } else if (dst
.regClass() == v1
) {
1329 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_xor_b32
, dst
, true);
1330 } else if (dst
.regClass() == v2
) {
1331 emit_vop2_instruction_logic64(ctx
, instr
, aco_opcode::v_xor_b32
, dst
);
1332 } else if (dst
.regClass() == s1
) {
1333 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_xor_b32
, dst
, true);
1334 } else if (dst
.regClass() == s2
) {
1335 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_xor_b64
, dst
, true);
1337 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1338 nir_print_instr(&instr
->instr
, stderr
);
1339 fprintf(stderr
, "\n");
1344 if (dst
.regClass() == v1
) {
1345 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_lshrrev_b32
, dst
, false, true);
1346 } else if (dst
.regClass() == v2
&& ctx
->program
->chip_class
>= GFX8
) {
1347 bld
.vop3(aco_opcode::v_lshrrev_b64
, Definition(dst
),
1348 get_alu_src(ctx
, instr
->src
[1]), get_alu_src(ctx
, instr
->src
[0]));
1349 } else if (dst
.regClass() == v2
) {
1350 bld
.vop3(aco_opcode::v_lshr_b64
, Definition(dst
),
1351 get_alu_src(ctx
, instr
->src
[0]), get_alu_src(ctx
, instr
->src
[1]));
1352 } else if (dst
.regClass() == s2
) {
1353 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_lshr_b64
, dst
, true);
1354 } else if (dst
.regClass() == s1
) {
1355 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_lshr_b32
, dst
, true);
1357 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1358 nir_print_instr(&instr
->instr
, stderr
);
1359 fprintf(stderr
, "\n");
1364 if (dst
.regClass() == v1
) {
1365 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_lshlrev_b32
, dst
, false, true);
1366 } else if (dst
.regClass() == v2
&& ctx
->program
->chip_class
>= GFX8
) {
1367 bld
.vop3(aco_opcode::v_lshlrev_b64
, Definition(dst
),
1368 get_alu_src(ctx
, instr
->src
[1]), get_alu_src(ctx
, instr
->src
[0]));
1369 } else if (dst
.regClass() == v2
) {
1370 bld
.vop3(aco_opcode::v_lshl_b64
, Definition(dst
),
1371 get_alu_src(ctx
, instr
->src
[0]), get_alu_src(ctx
, instr
->src
[1]));
1372 } else if (dst
.regClass() == s1
) {
1373 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_lshl_b32
, dst
, true);
1374 } else if (dst
.regClass() == s2
) {
1375 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_lshl_b64
, dst
, true);
1377 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1378 nir_print_instr(&instr
->instr
, stderr
);
1379 fprintf(stderr
, "\n");
1384 if (dst
.regClass() == v1
) {
1385 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_ashrrev_i32
, dst
, false, true);
1386 } else if (dst
.regClass() == v2
&& ctx
->program
->chip_class
>= GFX8
) {
1387 bld
.vop3(aco_opcode::v_ashrrev_i64
, Definition(dst
),
1388 get_alu_src(ctx
, instr
->src
[1]), get_alu_src(ctx
, instr
->src
[0]));
1389 } else if (dst
.regClass() == v2
) {
1390 bld
.vop3(aco_opcode::v_ashr_i64
, Definition(dst
),
1391 get_alu_src(ctx
, instr
->src
[0]), get_alu_src(ctx
, instr
->src
[1]));
1392 } else if (dst
.regClass() == s1
) {
1393 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_ashr_i32
, dst
, true);
1394 } else if (dst
.regClass() == s2
) {
1395 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_ashr_i64
, dst
, true);
1397 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1398 nir_print_instr(&instr
->instr
, stderr
);
1399 fprintf(stderr
, "\n");
1403 case nir_op_find_lsb
: {
1404 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
1405 if (src
.regClass() == s1
) {
1406 bld
.sop1(aco_opcode::s_ff1_i32_b32
, Definition(dst
), src
);
1407 } else if (src
.regClass() == v1
) {
1408 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_ffbl_b32
, dst
);
1409 } else if (src
.regClass() == s2
) {
1410 bld
.sop1(aco_opcode::s_ff1_i32_b64
, Definition(dst
), src
);
1412 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1413 nir_print_instr(&instr
->instr
, stderr
);
1414 fprintf(stderr
, "\n");
1418 case nir_op_ufind_msb
:
1419 case nir_op_ifind_msb
: {
1420 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
1421 if (src
.regClass() == s1
|| src
.regClass() == s2
) {
1422 aco_opcode op
= src
.regClass() == s2
?
1423 (instr
->op
== nir_op_ufind_msb
? aco_opcode::s_flbit_i32_b64
: aco_opcode::s_flbit_i32_i64
) :
1424 (instr
->op
== nir_op_ufind_msb
? aco_opcode::s_flbit_i32_b32
: aco_opcode::s_flbit_i32
);
1425 Temp msb_rev
= bld
.sop1(op
, bld
.def(s1
), src
);
1427 Builder::Result sub
= bld
.sop2(aco_opcode::s_sub_u32
, bld
.def(s1
), bld
.def(s1
, scc
),
1428 Operand(src
.size() * 32u - 1u), msb_rev
);
1429 Temp msb
= sub
.def(0).getTemp();
1430 Temp carry
= sub
.def(1).getTemp();
1432 bld
.sop2(aco_opcode::s_cselect_b32
, Definition(dst
), Operand((uint32_t)-1), msb
, bld
.scc(carry
));
1433 } else if (src
.regClass() == v1
) {
1434 aco_opcode op
= instr
->op
== nir_op_ufind_msb
? aco_opcode::v_ffbh_u32
: aco_opcode::v_ffbh_i32
;
1435 Temp msb_rev
= bld
.tmp(v1
);
1436 emit_vop1_instruction(ctx
, instr
, op
, msb_rev
);
1437 Temp msb
= bld
.tmp(v1
);
1438 Temp carry
= bld
.vsub32(Definition(msb
), Operand(31u), Operand(msb_rev
), true).def(1).getTemp();
1439 bld
.vop2_e64(aco_opcode::v_cndmask_b32
, Definition(dst
), msb
, Operand((uint32_t)-1), carry
);
1441 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1442 nir_print_instr(&instr
->instr
, stderr
);
1443 fprintf(stderr
, "\n");
1447 case nir_op_bitfield_reverse
: {
1448 if (dst
.regClass() == s1
) {
1449 bld
.sop1(aco_opcode::s_brev_b32
, Definition(dst
), get_alu_src(ctx
, instr
->src
[0]));
1450 } else if (dst
.regClass() == v1
) {
1451 bld
.vop1(aco_opcode::v_bfrev_b32
, Definition(dst
), get_alu_src(ctx
, instr
->src
[0]));
1453 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1454 nir_print_instr(&instr
->instr
, stderr
);
1455 fprintf(stderr
, "\n");
1460 if (dst
.regClass() == s1
) {
1461 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_add_u32
, dst
, true);
1465 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
1466 Temp src1
= get_alu_src(ctx
, instr
->src
[1]);
1467 if (dst
.regClass() == v1
) {
1468 bld
.vadd32(Definition(dst
), Operand(src0
), Operand(src1
));
1472 assert(src0
.size() == 2 && src1
.size() == 2);
1473 Temp src00
= bld
.tmp(src0
.type(), 1);
1474 Temp src01
= bld
.tmp(dst
.type(), 1);
1475 bld
.pseudo(aco_opcode::p_split_vector
, Definition(src00
), Definition(src01
), src0
);
1476 Temp src10
= bld
.tmp(src1
.type(), 1);
1477 Temp src11
= bld
.tmp(dst
.type(), 1);
1478 bld
.pseudo(aco_opcode::p_split_vector
, Definition(src10
), Definition(src11
), src1
);
1480 if (dst
.regClass() == s2
) {
1481 Temp carry
= bld
.tmp(s1
);
1482 Temp dst0
= bld
.sop2(aco_opcode::s_add_u32
, bld
.def(s1
), bld
.scc(Definition(carry
)), src00
, src10
);
1483 Temp dst1
= bld
.sop2(aco_opcode::s_addc_u32
, bld
.def(s1
), bld
.def(s1
, scc
), src01
, src11
, bld
.scc(carry
));
1484 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), dst0
, dst1
);
1485 } else if (dst
.regClass() == v2
) {
1486 Temp dst0
= bld
.tmp(v1
);
1487 Temp carry
= bld
.vadd32(Definition(dst0
), src00
, src10
, true).def(1).getTemp();
1488 Temp dst1
= bld
.vadd32(bld
.def(v1
), src01
, src11
, false, carry
);
1489 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), dst0
, dst1
);
1491 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1492 nir_print_instr(&instr
->instr
, stderr
);
1493 fprintf(stderr
, "\n");
1497 case nir_op_uadd_sat
: {
1498 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
1499 Temp src1
= get_alu_src(ctx
, instr
->src
[1]);
1500 if (dst
.regClass() == s1
) {
1501 Temp tmp
= bld
.tmp(s1
), carry
= bld
.tmp(s1
);
1502 bld
.sop2(aco_opcode::s_add_u32
, Definition(tmp
), bld
.scc(Definition(carry
)),
1504 bld
.sop2(aco_opcode::s_cselect_b32
, Definition(dst
), Operand((uint32_t) -1), tmp
, bld
.scc(carry
));
1505 } else if (dst
.regClass() == v1
) {
1506 if (ctx
->options
->chip_class
>= GFX9
) {
1507 aco_ptr
<VOP3A_instruction
> add
{create_instruction
<VOP3A_instruction
>(aco_opcode::v_add_u32
, asVOP3(Format::VOP2
), 2, 1)};
1508 add
->operands
[0] = Operand(src0
);
1509 add
->operands
[1] = Operand(src1
);
1510 add
->definitions
[0] = Definition(dst
);
1512 ctx
->block
->instructions
.emplace_back(std::move(add
));
1514 if (src1
.regClass() != v1
)
1515 std::swap(src0
, src1
);
1516 assert(src1
.regClass() == v1
);
1517 Temp tmp
= bld
.tmp(v1
);
1518 Temp carry
= bld
.vadd32(Definition(tmp
), src0
, src1
, true).def(1).getTemp();
1519 bld
.vop2_e64(aco_opcode::v_cndmask_b32
, Definition(dst
), tmp
, Operand((uint32_t) -1), carry
);
1522 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1523 nir_print_instr(&instr
->instr
, stderr
);
1524 fprintf(stderr
, "\n");
1528 case nir_op_uadd_carry
: {
1529 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
1530 Temp src1
= get_alu_src(ctx
, instr
->src
[1]);
1531 if (dst
.regClass() == s1
) {
1532 bld
.sop2(aco_opcode::s_add_u32
, bld
.def(s1
), bld
.scc(Definition(dst
)), src0
, src1
);
1535 if (dst
.regClass() == v1
) {
1536 Temp carry
= bld
.vadd32(bld
.def(v1
), src0
, src1
, true).def(1).getTemp();
1537 bld
.vop2_e64(aco_opcode::v_cndmask_b32
, Definition(dst
), Operand(0u), Operand(1u), carry
);
1541 Temp src00
= bld
.tmp(src0
.type(), 1);
1542 Temp src01
= bld
.tmp(dst
.type(), 1);
1543 bld
.pseudo(aco_opcode::p_split_vector
, Definition(src00
), Definition(src01
), src0
);
1544 Temp src10
= bld
.tmp(src1
.type(), 1);
1545 Temp src11
= bld
.tmp(dst
.type(), 1);
1546 bld
.pseudo(aco_opcode::p_split_vector
, Definition(src10
), Definition(src11
), src1
);
1547 if (dst
.regClass() == s2
) {
1548 Temp carry
= bld
.tmp(s1
);
1549 bld
.sop2(aco_opcode::s_add_u32
, bld
.def(s1
), bld
.scc(Definition(carry
)), src00
, src10
);
1550 carry
= bld
.sop2(aco_opcode::s_addc_u32
, bld
.def(s1
), bld
.scc(bld
.def(s1
)), src01
, src11
, bld
.scc(carry
)).def(1).getTemp();
1551 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), carry
, Operand(0u));
1552 } else if (dst
.regClass() == v2
) {
1553 Temp carry
= bld
.vadd32(bld
.def(v1
), src00
, src10
, true).def(1).getTemp();
1554 carry
= bld
.vadd32(bld
.def(v1
), src01
, src11
, true, carry
).def(1).getTemp();
1555 carry
= bld
.vop2_e64(aco_opcode::v_cndmask_b32
, bld
.def(v1
), Operand(0u), Operand(1u), carry
);
1556 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), carry
, Operand(0u));
1558 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1559 nir_print_instr(&instr
->instr
, stderr
);
1560 fprintf(stderr
, "\n");
1565 if (dst
.regClass() == s1
) {
1566 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_sub_i32
, dst
, true);
1570 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
1571 Temp src1
= get_alu_src(ctx
, instr
->src
[1]);
1572 if (dst
.regClass() == v1
) {
1573 bld
.vsub32(Definition(dst
), src0
, src1
);
1577 Temp src00
= bld
.tmp(src0
.type(), 1);
1578 Temp src01
= bld
.tmp(dst
.type(), 1);
1579 bld
.pseudo(aco_opcode::p_split_vector
, Definition(src00
), Definition(src01
), src0
);
1580 Temp src10
= bld
.tmp(src1
.type(), 1);
1581 Temp src11
= bld
.tmp(dst
.type(), 1);
1582 bld
.pseudo(aco_opcode::p_split_vector
, Definition(src10
), Definition(src11
), src1
);
1583 if (dst
.regClass() == s2
) {
1584 Temp carry
= bld
.tmp(s1
);
1585 Temp dst0
= bld
.sop2(aco_opcode::s_sub_u32
, bld
.def(s1
), bld
.scc(Definition(carry
)), src00
, src10
);
1586 Temp dst1
= bld
.sop2(aco_opcode::s_subb_u32
, bld
.def(s1
), bld
.def(s1
, scc
), src01
, src11
, carry
);
1587 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), dst0
, dst1
);
1588 } else if (dst
.regClass() == v2
) {
1589 Temp lower
= bld
.tmp(v1
);
1590 Temp borrow
= bld
.vsub32(Definition(lower
), src00
, src10
, true).def(1).getTemp();
1591 Temp upper
= bld
.vsub32(bld
.def(v1
), src01
, src11
, false, borrow
);
1592 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lower
, upper
);
1594 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1595 nir_print_instr(&instr
->instr
, stderr
);
1596 fprintf(stderr
, "\n");
1600 case nir_op_usub_borrow
: {
1601 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
1602 Temp src1
= get_alu_src(ctx
, instr
->src
[1]);
1603 if (dst
.regClass() == s1
) {
1604 bld
.sop2(aco_opcode::s_sub_u32
, bld
.def(s1
), bld
.scc(Definition(dst
)), src0
, src1
);
1606 } else if (dst
.regClass() == v1
) {
1607 Temp borrow
= bld
.vsub32(bld
.def(v1
), src0
, src1
, true).def(1).getTemp();
1608 bld
.vop2_e64(aco_opcode::v_cndmask_b32
, Definition(dst
), Operand(0u), Operand(1u), borrow
);
1612 Temp src00
= bld
.tmp(src0
.type(), 1);
1613 Temp src01
= bld
.tmp(dst
.type(), 1);
1614 bld
.pseudo(aco_opcode::p_split_vector
, Definition(src00
), Definition(src01
), src0
);
1615 Temp src10
= bld
.tmp(src1
.type(), 1);
1616 Temp src11
= bld
.tmp(dst
.type(), 1);
1617 bld
.pseudo(aco_opcode::p_split_vector
, Definition(src10
), Definition(src11
), src1
);
1618 if (dst
.regClass() == s2
) {
1619 Temp borrow
= bld
.tmp(s1
);
1620 bld
.sop2(aco_opcode::s_sub_u32
, bld
.def(s1
), bld
.scc(Definition(borrow
)), src00
, src10
);
1621 borrow
= bld
.sop2(aco_opcode::s_subb_u32
, bld
.def(s1
), bld
.scc(bld
.def(s1
)), src01
, src11
, bld
.scc(borrow
)).def(1).getTemp();
1622 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), borrow
, Operand(0u));
1623 } else if (dst
.regClass() == v2
) {
1624 Temp borrow
= bld
.vsub32(bld
.def(v1
), src00
, src10
, true).def(1).getTemp();
1625 borrow
= bld
.vsub32(bld
.def(v1
), src01
, src11
, true, Operand(borrow
)).def(1).getTemp();
1626 borrow
= bld
.vop2_e64(aco_opcode::v_cndmask_b32
, bld
.def(v1
), Operand(0u), Operand(1u), borrow
);
1627 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), borrow
, Operand(0u));
1629 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1630 nir_print_instr(&instr
->instr
, stderr
);
1631 fprintf(stderr
, "\n");
1636 if (dst
.regClass() == v1
) {
1637 bld
.vop3(aco_opcode::v_mul_lo_u32
, Definition(dst
),
1638 get_alu_src(ctx
, instr
->src
[0]), get_alu_src(ctx
, instr
->src
[1]));
1639 } else if (dst
.regClass() == s1
) {
1640 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_mul_i32
, dst
, false);
1642 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1643 nir_print_instr(&instr
->instr
, stderr
);
1644 fprintf(stderr
, "\n");
1648 case nir_op_umul_high
: {
1649 if (dst
.regClass() == v1
) {
1650 bld
.vop3(aco_opcode::v_mul_hi_u32
, Definition(dst
), get_alu_src(ctx
, instr
->src
[0]), get_alu_src(ctx
, instr
->src
[1]));
1651 } else if (dst
.regClass() == s1
&& ctx
->options
->chip_class
>= GFX9
) {
1652 bld
.sop2(aco_opcode::s_mul_hi_u32
, Definition(dst
), get_alu_src(ctx
, instr
->src
[0]), get_alu_src(ctx
, instr
->src
[1]));
1653 } else if (dst
.regClass() == s1
) {
1654 Temp tmp
= bld
.vop3(aco_opcode::v_mul_hi_u32
, bld
.def(v1
), get_alu_src(ctx
, instr
->src
[0]),
1655 as_vgpr(ctx
, get_alu_src(ctx
, instr
->src
[1])));
1656 bld
.pseudo(aco_opcode::p_as_uniform
, Definition(dst
), tmp
);
1658 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1659 nir_print_instr(&instr
->instr
, stderr
);
1660 fprintf(stderr
, "\n");
1664 case nir_op_imul_high
: {
1665 if (dst
.regClass() == v1
) {
1666 bld
.vop3(aco_opcode::v_mul_hi_i32
, Definition(dst
), get_alu_src(ctx
, instr
->src
[0]), get_alu_src(ctx
, instr
->src
[1]));
1667 } else if (dst
.regClass() == s1
&& ctx
->options
->chip_class
>= GFX9
) {
1668 bld
.sop2(aco_opcode::s_mul_hi_i32
, Definition(dst
), get_alu_src(ctx
, instr
->src
[0]), get_alu_src(ctx
, instr
->src
[1]));
1669 } else if (dst
.regClass() == s1
) {
1670 Temp tmp
= bld
.vop3(aco_opcode::v_mul_hi_i32
, bld
.def(v1
), get_alu_src(ctx
, instr
->src
[0]),
1671 as_vgpr(ctx
, get_alu_src(ctx
, instr
->src
[1])));
1672 bld
.pseudo(aco_opcode::p_as_uniform
, Definition(dst
), tmp
);
1674 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1675 nir_print_instr(&instr
->instr
, stderr
);
1676 fprintf(stderr
, "\n");
1681 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
1682 Temp src1
= as_vgpr(ctx
, get_alu_src(ctx
, instr
->src
[1]));
1683 if (dst
.regClass() == v2b
) {
1684 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_mul_f16
, dst
, true);
1685 } else if (dst
.regClass() == v1
) {
1686 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_mul_f32
, dst
, true);
1687 } else if (dst
.regClass() == v2
) {
1688 bld
.vop3(aco_opcode::v_mul_f64
, Definition(dst
), src0
, src1
);
1690 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1691 nir_print_instr(&instr
->instr
, stderr
);
1692 fprintf(stderr
, "\n");
1697 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
1698 Temp src1
= as_vgpr(ctx
, get_alu_src(ctx
, instr
->src
[1]));
1699 if (dst
.regClass() == v2b
) {
1700 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_add_f16
, dst
, true);
1701 } else if (dst
.regClass() == v1
) {
1702 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_add_f32
, dst
, true);
1703 } else if (dst
.regClass() == v2
) {
1704 bld
.vop3(aco_opcode::v_add_f64
, Definition(dst
), src0
, src1
);
1706 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1707 nir_print_instr(&instr
->instr
, stderr
);
1708 fprintf(stderr
, "\n");
1713 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
1714 Temp src1
= get_alu_src(ctx
, instr
->src
[1]);
1715 if (dst
.regClass() == v2b
) {
1716 if (src1
.type() == RegType::vgpr
|| src0
.type() != RegType::vgpr
)
1717 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_sub_f16
, dst
, false);
1719 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_subrev_f16
, dst
, true);
1720 } else if (dst
.regClass() == v1
) {
1721 if (src1
.type() == RegType::vgpr
|| src0
.type() != RegType::vgpr
)
1722 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_sub_f32
, dst
, false);
1724 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_subrev_f32
, dst
, true);
1725 } else if (dst
.regClass() == v2
) {
1726 Instruction
* add
= bld
.vop3(aco_opcode::v_add_f64
, Definition(dst
),
1727 as_vgpr(ctx
, src0
), as_vgpr(ctx
, src1
));
1728 VOP3A_instruction
* sub
= static_cast<VOP3A_instruction
*>(add
);
1731 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1732 nir_print_instr(&instr
->instr
, stderr
);
1733 fprintf(stderr
, "\n");
1738 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
1739 Temp src1
= as_vgpr(ctx
, get_alu_src(ctx
, instr
->src
[1]));
1740 if (dst
.regClass() == v2b
) {
1741 // TODO: check fp_mode.must_flush_denorms16_64
1742 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_max_f16
, dst
, true);
1743 } else if (dst
.regClass() == v1
) {
1744 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_max_f32
, dst
, true, false, ctx
->block
->fp_mode
.must_flush_denorms32
);
1745 } else if (dst
.regClass() == v2
) {
1746 if (ctx
->block
->fp_mode
.must_flush_denorms16_64
&& ctx
->program
->chip_class
< GFX9
) {
1747 Temp tmp
= bld
.vop3(aco_opcode::v_max_f64
, bld
.def(v2
), src0
, src1
);
1748 bld
.vop3(aco_opcode::v_mul_f64
, Definition(dst
), Operand(0x3FF0000000000000lu
), tmp
);
1750 bld
.vop3(aco_opcode::v_max_f64
, Definition(dst
), src0
, src1
);
1753 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1754 nir_print_instr(&instr
->instr
, stderr
);
1755 fprintf(stderr
, "\n");
1760 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
1761 Temp src1
= as_vgpr(ctx
, get_alu_src(ctx
, instr
->src
[1]));
1762 if (dst
.regClass() == v2b
) {
1763 // TODO: check fp_mode.must_flush_denorms16_64
1764 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_min_f16
, dst
, true);
1765 } else if (dst
.regClass() == v1
) {
1766 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_min_f32
, dst
, true, false, ctx
->block
->fp_mode
.must_flush_denorms32
);
1767 } else if (dst
.regClass() == v2
) {
1768 if (ctx
->block
->fp_mode
.must_flush_denorms16_64
&& ctx
->program
->chip_class
< GFX9
) {
1769 Temp tmp
= bld
.vop3(aco_opcode::v_min_f64
, bld
.def(v2
), src0
, src1
);
1770 bld
.vop3(aco_opcode::v_mul_f64
, Definition(dst
), Operand(0x3FF0000000000000lu
), tmp
);
1772 bld
.vop3(aco_opcode::v_min_f64
, Definition(dst
), src0
, src1
);
1775 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1776 nir_print_instr(&instr
->instr
, stderr
);
1777 fprintf(stderr
, "\n");
1781 case nir_op_fmax3
: {
1782 if (dst
.regClass() == v2b
) {
1783 emit_vop3a_instruction(ctx
, instr
, aco_opcode::v_max3_f16
, dst
, false);
1784 } else if (dst
.regClass() == v1
) {
1785 emit_vop3a_instruction(ctx
, instr
, aco_opcode::v_max3_f32
, dst
, ctx
->block
->fp_mode
.must_flush_denorms32
);
1787 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1788 nir_print_instr(&instr
->instr
, stderr
);
1789 fprintf(stderr
, "\n");
1793 case nir_op_fmin3
: {
1794 if (dst
.regClass() == v2b
) {
1795 emit_vop3a_instruction(ctx
, instr
, aco_opcode::v_min3_f16
, dst
, false);
1796 } else if (dst
.regClass() == v1
) {
1797 emit_vop3a_instruction(ctx
, instr
, aco_opcode::v_min3_f32
, dst
, ctx
->block
->fp_mode
.must_flush_denorms32
);
1799 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1800 nir_print_instr(&instr
->instr
, stderr
);
1801 fprintf(stderr
, "\n");
1805 case nir_op_fmed3
: {
1806 if (dst
.regClass() == v2b
) {
1807 emit_vop3a_instruction(ctx
, instr
, aco_opcode::v_med3_f16
, dst
, false);
1808 } else if (dst
.regClass() == v1
) {
1809 emit_vop3a_instruction(ctx
, instr
, aco_opcode::v_med3_f32
, dst
, ctx
->block
->fp_mode
.must_flush_denorms32
);
1811 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1812 nir_print_instr(&instr
->instr
, stderr
);
1813 fprintf(stderr
, "\n");
1817 case nir_op_umax3
: {
1818 if (dst
.size() == 1) {
1819 emit_vop3a_instruction(ctx
, instr
, aco_opcode::v_max3_u32
, dst
);
1821 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1822 nir_print_instr(&instr
->instr
, stderr
);
1823 fprintf(stderr
, "\n");
1827 case nir_op_umin3
: {
1828 if (dst
.size() == 1) {
1829 emit_vop3a_instruction(ctx
, instr
, aco_opcode::v_min3_u32
, dst
);
1831 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1832 nir_print_instr(&instr
->instr
, stderr
);
1833 fprintf(stderr
, "\n");
1837 case nir_op_umed3
: {
1838 if (dst
.size() == 1) {
1839 emit_vop3a_instruction(ctx
, instr
, aco_opcode::v_med3_u32
, dst
);
1841 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1842 nir_print_instr(&instr
->instr
, stderr
);
1843 fprintf(stderr
, "\n");
1847 case nir_op_imax3
: {
1848 if (dst
.size() == 1) {
1849 emit_vop3a_instruction(ctx
, instr
, aco_opcode::v_max3_i32
, dst
);
1851 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1852 nir_print_instr(&instr
->instr
, stderr
);
1853 fprintf(stderr
, "\n");
1857 case nir_op_imin3
: {
1858 if (dst
.size() == 1) {
1859 emit_vop3a_instruction(ctx
, instr
, aco_opcode::v_min3_i32
, dst
);
1861 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1862 nir_print_instr(&instr
->instr
, stderr
);
1863 fprintf(stderr
, "\n");
1867 case nir_op_imed3
: {
1868 if (dst
.size() == 1) {
1869 emit_vop3a_instruction(ctx
, instr
, aco_opcode::v_med3_i32
, dst
);
1871 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1872 nir_print_instr(&instr
->instr
, stderr
);
1873 fprintf(stderr
, "\n");
1877 case nir_op_cube_face_coord
: {
1878 Temp in
= get_alu_src(ctx
, instr
->src
[0], 3);
1879 Temp src
[3] = { emit_extract_vector(ctx
, in
, 0, v1
),
1880 emit_extract_vector(ctx
, in
, 1, v1
),
1881 emit_extract_vector(ctx
, in
, 2, v1
) };
1882 Temp ma
= bld
.vop3(aco_opcode::v_cubema_f32
, bld
.def(v1
), src
[0], src
[1], src
[2]);
1883 ma
= bld
.vop1(aco_opcode::v_rcp_f32
, bld
.def(v1
), ma
);
1884 Temp sc
= bld
.vop3(aco_opcode::v_cubesc_f32
, bld
.def(v1
), src
[0], src
[1], src
[2]);
1885 Temp tc
= bld
.vop3(aco_opcode::v_cubetc_f32
, bld
.def(v1
), src
[0], src
[1], src
[2]);
1886 sc
= bld
.vop2(aco_opcode::v_madak_f32
, bld
.def(v1
), sc
, ma
, Operand(0x3f000000u
/*0.5*/));
1887 tc
= bld
.vop2(aco_opcode::v_madak_f32
, bld
.def(v1
), tc
, ma
, Operand(0x3f000000u
/*0.5*/));
1888 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), sc
, tc
);
1891 case nir_op_cube_face_index
: {
1892 Temp in
= get_alu_src(ctx
, instr
->src
[0], 3);
1893 Temp src
[3] = { emit_extract_vector(ctx
, in
, 0, v1
),
1894 emit_extract_vector(ctx
, in
, 1, v1
),
1895 emit_extract_vector(ctx
, in
, 2, v1
) };
1896 bld
.vop3(aco_opcode::v_cubeid_f32
, Definition(dst
), src
[0], src
[1], src
[2]);
1899 case nir_op_bcsel
: {
1900 emit_bcsel(ctx
, instr
, dst
);
1904 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
1905 if (dst
.regClass() == v2b
) {
1906 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_rsq_f16
, dst
);
1907 } else if (dst
.regClass() == v1
) {
1908 emit_rsq(ctx
, bld
, Definition(dst
), src
);
1909 } else if (dst
.regClass() == v2
) {
1910 /* Lowered at NIR level for precision reasons. */
1911 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_rsq_f64
, dst
);
1913 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1914 nir_print_instr(&instr
->instr
, stderr
);
1915 fprintf(stderr
, "\n");
1920 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
1921 if (dst
.regClass() == v2b
) {
1922 bld
.vop2(aco_opcode::v_xor_b32
, Definition(dst
), Operand(0x8000u
), as_vgpr(ctx
, src
));
1923 } else if (dst
.regClass() == v1
) {
1924 if (ctx
->block
->fp_mode
.must_flush_denorms32
)
1925 src
= bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), Operand(0x3f800000u
), as_vgpr(ctx
, src
));
1926 bld
.vop2(aco_opcode::v_xor_b32
, Definition(dst
), Operand(0x80000000u
), as_vgpr(ctx
, src
));
1927 } else if (dst
.regClass() == v2
) {
1928 if (ctx
->block
->fp_mode
.must_flush_denorms16_64
)
1929 src
= bld
.vop3(aco_opcode::v_mul_f64
, bld
.def(v2
), Operand(0x3FF0000000000000lu
), as_vgpr(ctx
, src
));
1930 Temp upper
= bld
.tmp(v1
), lower
= bld
.tmp(v1
);
1931 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lower
), Definition(upper
), src
);
1932 upper
= bld
.vop2(aco_opcode::v_xor_b32
, bld
.def(v1
), Operand(0x80000000u
), upper
);
1933 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lower
, upper
);
1935 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1936 nir_print_instr(&instr
->instr
, stderr
);
1937 fprintf(stderr
, "\n");
1942 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
1943 if (dst
.regClass() == v2b
) {
1944 bld
.vop2(aco_opcode::v_and_b32
, Definition(dst
), Operand(0x7FFFu
), as_vgpr(ctx
, src
));
1945 } else if (dst
.regClass() == v1
) {
1946 if (ctx
->block
->fp_mode
.must_flush_denorms32
)
1947 src
= bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), Operand(0x3f800000u
), as_vgpr(ctx
, src
));
1948 bld
.vop2(aco_opcode::v_and_b32
, Definition(dst
), Operand(0x7FFFFFFFu
), as_vgpr(ctx
, src
));
1949 } else if (dst
.regClass() == v2
) {
1950 if (ctx
->block
->fp_mode
.must_flush_denorms16_64
)
1951 src
= bld
.vop3(aco_opcode::v_mul_f64
, bld
.def(v2
), Operand(0x3FF0000000000000lu
), as_vgpr(ctx
, src
));
1952 Temp upper
= bld
.tmp(v1
), lower
= bld
.tmp(v1
);
1953 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lower
), Definition(upper
), src
);
1954 upper
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(0x7FFFFFFFu
), upper
);
1955 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lower
, upper
);
1957 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1958 nir_print_instr(&instr
->instr
, stderr
);
1959 fprintf(stderr
, "\n");
1964 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
1965 if (dst
.regClass() == v2b
) {
1966 bld
.vop3(aco_opcode::v_med3_f16
, Definition(dst
), Operand((uint16_t)0u), Operand((uint16_t)0x3c00), src
);
1967 } else if (dst
.regClass() == v1
) {
1968 bld
.vop3(aco_opcode::v_med3_f32
, Definition(dst
), Operand(0u), Operand(0x3f800000u
), src
);
1969 /* apparently, it is not necessary to flush denorms if this instruction is used with these operands */
1970 // TODO: confirm that this holds under any circumstances
1971 } else if (dst
.regClass() == v2
) {
1972 Instruction
* add
= bld
.vop3(aco_opcode::v_add_f64
, Definition(dst
), src
, Operand(0u));
1973 VOP3A_instruction
* vop3
= static_cast<VOP3A_instruction
*>(add
);
1976 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1977 nir_print_instr(&instr
->instr
, stderr
);
1978 fprintf(stderr
, "\n");
1982 case nir_op_flog2
: {
1983 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
1984 if (dst
.regClass() == v2b
) {
1985 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_log_f16
, dst
);
1986 } else if (dst
.regClass() == v1
) {
1987 emit_log2(ctx
, bld
, Definition(dst
), src
);
1989 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1990 nir_print_instr(&instr
->instr
, stderr
);
1991 fprintf(stderr
, "\n");
1996 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
1997 if (dst
.regClass() == v2b
) {
1998 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_rcp_f16
, dst
);
1999 } else if (dst
.regClass() == v1
) {
2000 emit_rcp(ctx
, bld
, Definition(dst
), src
);
2001 } else if (dst
.regClass() == v2
) {
2002 /* Lowered at NIR level for precision reasons. */
2003 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_rcp_f64
, dst
);
2005 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2006 nir_print_instr(&instr
->instr
, stderr
);
2007 fprintf(stderr
, "\n");
2011 case nir_op_fexp2
: {
2012 if (dst
.regClass() == v2b
) {
2013 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_exp_f16
, dst
);
2014 } else if (dst
.regClass() == v1
) {
2015 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_exp_f32
, dst
);
2017 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2018 nir_print_instr(&instr
->instr
, stderr
);
2019 fprintf(stderr
, "\n");
2023 case nir_op_fsqrt
: {
2024 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2025 if (dst
.regClass() == v2b
) {
2026 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_sqrt_f16
, dst
);
2027 } else if (dst
.regClass() == v1
) {
2028 emit_sqrt(ctx
, bld
, Definition(dst
), src
);
2029 } else if (dst
.regClass() == v2
) {
2030 /* Lowered at NIR level for precision reasons. */
2031 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_sqrt_f64
, dst
);
2033 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2034 nir_print_instr(&instr
->instr
, stderr
);
2035 fprintf(stderr
, "\n");
2039 case nir_op_ffract
: {
2040 if (dst
.regClass() == v2b
) {
2041 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_fract_f16
, dst
);
2042 } else if (dst
.regClass() == v1
) {
2043 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_fract_f32
, dst
);
2044 } else if (dst
.regClass() == v2
) {
2045 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_fract_f64
, dst
);
2047 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2048 nir_print_instr(&instr
->instr
, stderr
);
2049 fprintf(stderr
, "\n");
2053 case nir_op_ffloor
: {
2054 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2055 if (dst
.regClass() == v2b
) {
2056 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_floor_f16
, dst
);
2057 } else if (dst
.regClass() == v1
) {
2058 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_floor_f32
, dst
);
2059 } else if (dst
.regClass() == v2
) {
2060 emit_floor_f64(ctx
, bld
, Definition(dst
), src
);
2062 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2063 nir_print_instr(&instr
->instr
, stderr
);
2064 fprintf(stderr
, "\n");
2068 case nir_op_fceil
: {
2069 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
2070 if (dst
.regClass() == v2b
) {
2071 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_ceil_f16
, dst
);
2072 } else if (dst
.regClass() == v1
) {
2073 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_ceil_f32
, dst
);
2074 } else if (dst
.regClass() == v2
) {
2075 if (ctx
->options
->chip_class
>= GFX7
) {
2076 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_ceil_f64
, dst
);
2078 /* GFX6 doesn't support V_CEIL_F64, lower it. */
2079 /* trunc = trunc(src0)
2080 * if (src0 > 0.0 && src0 != trunc)
2083 Temp trunc
= emit_trunc_f64(ctx
, bld
, bld
.def(v2
), src0
);
2084 Temp tmp0
= bld
.vopc_e64(aco_opcode::v_cmp_gt_f64
, bld
.def(bld
.lm
), src0
, Operand(0u));
2085 Temp tmp1
= bld
.vopc(aco_opcode::v_cmp_lg_f64
, bld
.hint_vcc(bld
.def(bld
.lm
)), src0
, trunc
);
2086 Temp cond
= bld
.sop2(aco_opcode::s_and_b64
, bld
.hint_vcc(bld
.def(s2
)), bld
.def(s1
, scc
), tmp0
, tmp1
);
2087 Temp add
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), bld
.copy(bld
.def(v1
), Operand(0u)), bld
.copy(bld
.def(v1
), Operand(0x3ff00000u
)), cond
);
2088 add
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), bld
.copy(bld
.def(v1
), Operand(0u)), add
);
2089 bld
.vop3(aco_opcode::v_add_f64
, Definition(dst
), trunc
, add
);
2092 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2093 nir_print_instr(&instr
->instr
, stderr
);
2094 fprintf(stderr
, "\n");
2098 case nir_op_ftrunc
: {
2099 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2100 if (dst
.regClass() == v2b
) {
2101 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_trunc_f16
, dst
);
2102 } else if (dst
.regClass() == v1
) {
2103 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_trunc_f32
, dst
);
2104 } else if (dst
.regClass() == v2
) {
2105 emit_trunc_f64(ctx
, bld
, Definition(dst
), src
);
2107 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2108 nir_print_instr(&instr
->instr
, stderr
);
2109 fprintf(stderr
, "\n");
2113 case nir_op_fround_even
: {
2114 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
2115 if (dst
.regClass() == v2b
) {
2116 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_rndne_f16
, dst
);
2117 } else if (dst
.regClass() == v1
) {
2118 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_rndne_f32
, dst
);
2119 } else if (dst
.regClass() == v2
) {
2120 if (ctx
->options
->chip_class
>= GFX7
) {
2121 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_rndne_f64
, dst
);
2123 /* GFX6 doesn't support V_RNDNE_F64, lower it. */
2124 Temp src0_lo
= bld
.tmp(v1
), src0_hi
= bld
.tmp(v1
);
2125 bld
.pseudo(aco_opcode::p_split_vector
, Definition(src0_lo
), Definition(src0_hi
), src0
);
2127 Temp bitmask
= bld
.sop1(aco_opcode::s_brev_b32
, bld
.def(s1
), bld
.copy(bld
.def(s1
), Operand(-2u)));
2128 Temp bfi
= bld
.vop3(aco_opcode::v_bfi_b32
, bld
.def(v1
), bitmask
, bld
.copy(bld
.def(v1
), Operand(0x43300000u
)), as_vgpr(ctx
, src0_hi
));
2129 Temp tmp
= bld
.vop3(aco_opcode::v_add_f64
, bld
.def(v2
), src0
, bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), Operand(0u), bfi
));
2130 Instruction
*sub
= bld
.vop3(aco_opcode::v_add_f64
, bld
.def(v2
), tmp
, bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), Operand(0u), bfi
));
2131 static_cast<VOP3A_instruction
*>(sub
)->neg
[1] = true;
2132 tmp
= sub
->definitions
[0].getTemp();
2134 Temp v
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), Operand(-1u), Operand(0x432fffffu
));
2135 Instruction
* vop3
= bld
.vopc_e64(aco_opcode::v_cmp_gt_f64
, bld
.hint_vcc(bld
.def(bld
.lm
)), src0
, v
);
2136 static_cast<VOP3A_instruction
*>(vop3
)->abs
[0] = true;
2137 Temp cond
= vop3
->definitions
[0].getTemp();
2139 Temp tmp_lo
= bld
.tmp(v1
), tmp_hi
= bld
.tmp(v1
);
2140 bld
.pseudo(aco_opcode::p_split_vector
, Definition(tmp_lo
), Definition(tmp_hi
), tmp
);
2141 Temp dst0
= bld
.vop2_e64(aco_opcode::v_cndmask_b32
, bld
.def(v1
), tmp_lo
, as_vgpr(ctx
, src0_lo
), cond
);
2142 Temp dst1
= bld
.vop2_e64(aco_opcode::v_cndmask_b32
, bld
.def(v1
), tmp_hi
, as_vgpr(ctx
, src0_hi
), cond
);
2144 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), dst0
, dst1
);
2147 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2148 nir_print_instr(&instr
->instr
, stderr
);
2149 fprintf(stderr
, "\n");
2155 Temp src
= as_vgpr(ctx
, get_alu_src(ctx
, instr
->src
[0]));
2156 aco_ptr
<Instruction
> norm
;
2157 if (dst
.regClass() == v2b
) {
2158 Temp half_pi
= bld
.copy(bld
.def(s1
), Operand(0x3118u
));
2159 Temp tmp
= bld
.vop2(aco_opcode::v_mul_f16
, bld
.def(v1
), half_pi
, src
);
2160 aco_opcode opcode
= instr
->op
== nir_op_fsin
? aco_opcode::v_sin_f16
: aco_opcode::v_cos_f16
;
2161 bld
.vop1(opcode
, Definition(dst
), tmp
);
2162 } else if (dst
.regClass() == v1
) {
2163 Temp half_pi
= bld
.copy(bld
.def(s1
), Operand(0x3e22f983u
));
2164 Temp tmp
= bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), half_pi
, src
);
2166 /* before GFX9, v_sin_f32 and v_cos_f32 had a valid input domain of [-256, +256] */
2167 if (ctx
->options
->chip_class
< GFX9
)
2168 tmp
= bld
.vop1(aco_opcode::v_fract_f32
, bld
.def(v1
), tmp
);
2170 aco_opcode opcode
= instr
->op
== nir_op_fsin
? aco_opcode::v_sin_f32
: aco_opcode::v_cos_f32
;
2171 bld
.vop1(opcode
, Definition(dst
), tmp
);
2173 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2174 nir_print_instr(&instr
->instr
, stderr
);
2175 fprintf(stderr
, "\n");
2179 case nir_op_ldexp
: {
2180 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
2181 Temp src1
= get_alu_src(ctx
, instr
->src
[1]);
2182 if (dst
.regClass() == v2b
) {
2183 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_ldexp_f16
, dst
, false);
2184 } else if (dst
.regClass() == v1
) {
2185 bld
.vop3(aco_opcode::v_ldexp_f32
, Definition(dst
), as_vgpr(ctx
, src0
), src1
);
2186 } else if (dst
.regClass() == v2
) {
2187 bld
.vop3(aco_opcode::v_ldexp_f64
, Definition(dst
), as_vgpr(ctx
, src0
), src1
);
2189 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2190 nir_print_instr(&instr
->instr
, stderr
);
2191 fprintf(stderr
, "\n");
2195 case nir_op_frexp_sig
: {
2196 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2197 if (dst
.regClass() == v2b
) {
2198 bld
.vop1(aco_opcode::v_frexp_mant_f16
, Definition(dst
), src
);
2199 } else if (dst
.regClass() == v1
) {
2200 bld
.vop1(aco_opcode::v_frexp_mant_f32
, Definition(dst
), src
);
2201 } else if (dst
.regClass() == v2
) {
2202 bld
.vop1(aco_opcode::v_frexp_mant_f64
, Definition(dst
), src
);
2204 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2205 nir_print_instr(&instr
->instr
, stderr
);
2206 fprintf(stderr
, "\n");
2210 case nir_op_frexp_exp
: {
2211 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2212 if (instr
->src
[0].src
.ssa
->bit_size
== 16) {
2213 Temp tmp
= bld
.vop1(aco_opcode::v_frexp_exp_i16_f16
, bld
.def(v1
), src
);
2214 tmp
= bld
.pseudo(aco_opcode::p_extract_vector
, bld
.def(v1b
), tmp
, Operand(0u));
2215 convert_int(ctx
, bld
, tmp
, 8, 32, true, dst
);
2216 } else if (instr
->src
[0].src
.ssa
->bit_size
== 32) {
2217 bld
.vop1(aco_opcode::v_frexp_exp_i32_f32
, Definition(dst
), src
);
2218 } else if (instr
->src
[0].src
.ssa
->bit_size
== 64) {
2219 bld
.vop1(aco_opcode::v_frexp_exp_i32_f64
, Definition(dst
), src
);
2221 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2222 nir_print_instr(&instr
->instr
, stderr
);
2223 fprintf(stderr
, "\n");
2227 case nir_op_fsign
: {
2228 Temp src
= as_vgpr(ctx
, get_alu_src(ctx
, instr
->src
[0]));
2229 if (dst
.regClass() == v2b
) {
2230 Temp one
= bld
.copy(bld
.def(v1
), Operand(0x3c00u
));
2231 Temp minus_one
= bld
.copy(bld
.def(v1
), Operand(0xbc00u
));
2232 Temp cond
= bld
.vopc(aco_opcode::v_cmp_nlt_f16
, bld
.hint_vcc(bld
.def(bld
.lm
)), Operand(0u), src
);
2233 src
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), one
, src
, cond
);
2234 cond
= bld
.vopc(aco_opcode::v_cmp_le_f16
, bld
.hint_vcc(bld
.def(bld
.lm
)), Operand(0u), src
);
2235 bld
.vop2(aco_opcode::v_cndmask_b32
, Definition(dst
), minus_one
, src
, cond
);
2236 } else if (dst
.regClass() == v1
) {
2237 Temp cond
= bld
.vopc(aco_opcode::v_cmp_nlt_f32
, bld
.hint_vcc(bld
.def(bld
.lm
)), Operand(0u), src
);
2238 src
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), Operand(0x3f800000u
), src
, cond
);
2239 cond
= bld
.vopc(aco_opcode::v_cmp_le_f32
, bld
.hint_vcc(bld
.def(bld
.lm
)), Operand(0u), src
);
2240 bld
.vop2(aco_opcode::v_cndmask_b32
, Definition(dst
), Operand(0xbf800000u
), src
, cond
);
2241 } else if (dst
.regClass() == v2
) {
2242 Temp cond
= bld
.vopc(aco_opcode::v_cmp_nlt_f64
, bld
.hint_vcc(bld
.def(bld
.lm
)), Operand(0u), src
);
2243 Temp tmp
= bld
.vop1(aco_opcode::v_mov_b32
, bld
.def(v1
), Operand(0x3FF00000u
));
2244 Temp upper
= bld
.vop2_e64(aco_opcode::v_cndmask_b32
, bld
.def(v1
), tmp
, emit_extract_vector(ctx
, src
, 1, v1
), cond
);
2246 cond
= bld
.vopc(aco_opcode::v_cmp_le_f64
, bld
.hint_vcc(bld
.def(bld
.lm
)), Operand(0u), src
);
2247 tmp
= bld
.vop1(aco_opcode::v_mov_b32
, bld
.def(v1
), Operand(0xBFF00000u
));
2248 upper
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), tmp
, upper
, cond
);
2250 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), Operand(0u), upper
);
2252 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2253 nir_print_instr(&instr
->instr
, stderr
);
2254 fprintf(stderr
, "\n");
2259 case nir_op_f2f16_rtne
: {
2260 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2261 if (instr
->src
[0].src
.ssa
->bit_size
== 64)
2262 src
= bld
.vop1(aco_opcode::v_cvt_f32_f64
, bld
.def(v1
), src
);
2263 bld
.vop1(aco_opcode::v_cvt_f16_f32
, Definition(dst
), src
);
2266 case nir_op_f2f16_rtz
: {
2267 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2268 if (instr
->src
[0].src
.ssa
->bit_size
== 64)
2269 src
= bld
.vop1(aco_opcode::v_cvt_f32_f64
, bld
.def(v1
), src
);
2270 bld
.vop3(aco_opcode::v_cvt_pkrtz_f16_f32
, Definition(dst
), src
, Operand(0u));
2273 case nir_op_f2f32
: {
2274 if (instr
->src
[0].src
.ssa
->bit_size
== 16) {
2275 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_cvt_f32_f16
, dst
);
2276 } else if (instr
->src
[0].src
.ssa
->bit_size
== 64) {
2277 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_cvt_f32_f64
, dst
);
2279 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2280 nir_print_instr(&instr
->instr
, stderr
);
2281 fprintf(stderr
, "\n");
2285 case nir_op_f2f64
: {
2286 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2287 if (instr
->src
[0].src
.ssa
->bit_size
== 16)
2288 src
= bld
.vop1(aco_opcode::v_cvt_f32_f16
, bld
.def(v1
), src
);
2289 bld
.vop1(aco_opcode::v_cvt_f64_f32
, Definition(dst
), src
);
2292 case nir_op_i2f16
: {
2293 assert(dst
.regClass() == v2b
);
2294 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2295 if (instr
->src
[0].src
.ssa
->bit_size
== 8)
2296 src
= convert_int(ctx
, bld
, src
, 8, 16, true);
2297 else if (instr
->src
[0].src
.ssa
->bit_size
== 64)
2298 src
= convert_int(ctx
, bld
, src
, 64, 32, false);
2299 bld
.vop1(aco_opcode::v_cvt_f16_i16
, Definition(dst
), src
);
2302 case nir_op_i2f32
: {
2303 assert(dst
.size() == 1);
2304 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2305 if (instr
->src
[0].src
.ssa
->bit_size
<= 16)
2306 src
= convert_int(ctx
, bld
, src
, instr
->src
[0].src
.ssa
->bit_size
, 32, true);
2307 bld
.vop1(aco_opcode::v_cvt_f32_i32
, Definition(dst
), src
);
2310 case nir_op_i2f64
: {
2311 if (instr
->src
[0].src
.ssa
->bit_size
<= 32) {
2312 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2313 if (instr
->src
[0].src
.ssa
->bit_size
<= 16)
2314 src
= convert_int(ctx
, bld
, src
, instr
->src
[0].src
.ssa
->bit_size
, 32, true);
2315 bld
.vop1(aco_opcode::v_cvt_f64_i32
, Definition(dst
), src
);
2316 } else if (instr
->src
[0].src
.ssa
->bit_size
== 64) {
2317 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2318 RegClass rc
= RegClass(src
.type(), 1);
2319 Temp lower
= bld
.tmp(rc
), upper
= bld
.tmp(rc
);
2320 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lower
), Definition(upper
), src
);
2321 lower
= bld
.vop1(aco_opcode::v_cvt_f64_u32
, bld
.def(v2
), lower
);
2322 upper
= bld
.vop1(aco_opcode::v_cvt_f64_i32
, bld
.def(v2
), upper
);
2323 upper
= bld
.vop3(aco_opcode::v_ldexp_f64
, bld
.def(v2
), upper
, Operand(32u));
2324 bld
.vop3(aco_opcode::v_add_f64
, Definition(dst
), lower
, upper
);
2327 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2328 nir_print_instr(&instr
->instr
, stderr
);
2329 fprintf(stderr
, "\n");
2333 case nir_op_u2f16
: {
2334 assert(dst
.regClass() == v2b
);
2335 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2336 if (instr
->src
[0].src
.ssa
->bit_size
== 8)
2337 src
= convert_int(ctx
, bld
, src
, 8, 16, false);
2338 else if (instr
->src
[0].src
.ssa
->bit_size
== 64)
2339 src
= convert_int(ctx
, bld
, src
, 64, 32, false);
2340 bld
.vop1(aco_opcode::v_cvt_f16_u16
, Definition(dst
), src
);
2343 case nir_op_u2f32
: {
2344 assert(dst
.size() == 1);
2345 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2346 if (instr
->src
[0].src
.ssa
->bit_size
== 8) {
2347 bld
.vop1(aco_opcode::v_cvt_f32_ubyte0
, Definition(dst
), src
);
2349 if (instr
->src
[0].src
.ssa
->bit_size
== 16)
2350 src
= convert_int(ctx
, bld
, src
, instr
->src
[0].src
.ssa
->bit_size
, 32, true);
2351 bld
.vop1(aco_opcode::v_cvt_f32_u32
, Definition(dst
), src
);
2355 case nir_op_u2f64
: {
2356 if (instr
->src
[0].src
.ssa
->bit_size
<= 32) {
2357 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2358 if (instr
->src
[0].src
.ssa
->bit_size
<= 16)
2359 src
= convert_int(ctx
, bld
, src
, instr
->src
[0].src
.ssa
->bit_size
, 32, false);
2360 bld
.vop1(aco_opcode::v_cvt_f64_u32
, Definition(dst
), src
);
2361 } else if (instr
->src
[0].src
.ssa
->bit_size
== 64) {
2362 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2363 RegClass rc
= RegClass(src
.type(), 1);
2364 Temp lower
= bld
.tmp(rc
), upper
= bld
.tmp(rc
);
2365 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lower
), Definition(upper
), src
);
2366 lower
= bld
.vop1(aco_opcode::v_cvt_f64_u32
, bld
.def(v2
), lower
);
2367 upper
= bld
.vop1(aco_opcode::v_cvt_f64_u32
, bld
.def(v2
), upper
);
2368 upper
= bld
.vop3(aco_opcode::v_ldexp_f64
, bld
.def(v2
), upper
, Operand(32u));
2369 bld
.vop3(aco_opcode::v_add_f64
, Definition(dst
), lower
, upper
);
2371 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2372 nir_print_instr(&instr
->instr
, stderr
);
2373 fprintf(stderr
, "\n");
2378 case nir_op_f2i16
: {
2379 if (instr
->src
[0].src
.ssa
->bit_size
== 16)
2380 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_cvt_i16_f16
, dst
);
2381 else if (instr
->src
[0].src
.ssa
->bit_size
== 32)
2382 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_cvt_i32_f32
, dst
);
2384 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_cvt_i32_f64
, dst
);
2388 case nir_op_f2u16
: {
2389 if (instr
->src
[0].src
.ssa
->bit_size
== 16)
2390 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_cvt_u16_f16
, dst
);
2391 else if (instr
->src
[0].src
.ssa
->bit_size
== 32)
2392 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_cvt_u32_f32
, dst
);
2394 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_cvt_u32_f64
, dst
);
2397 case nir_op_f2i32
: {
2398 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2399 if (instr
->src
[0].src
.ssa
->bit_size
== 16) {
2400 Temp tmp
= bld
.vop1(aco_opcode::v_cvt_f32_f16
, bld
.def(v1
), src
);
2401 if (dst
.type() == RegType::vgpr
) {
2402 bld
.vop1(aco_opcode::v_cvt_i32_f32
, Definition(dst
), tmp
);
2404 bld
.pseudo(aco_opcode::p_as_uniform
, Definition(dst
),
2405 bld
.vop1(aco_opcode::v_cvt_i32_f32
, bld
.def(v1
), tmp
));
2407 } else if (instr
->src
[0].src
.ssa
->bit_size
== 32) {
2408 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_cvt_i32_f32
, dst
);
2409 } else if (instr
->src
[0].src
.ssa
->bit_size
== 64) {
2410 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_cvt_i32_f64
, dst
);
2412 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2413 nir_print_instr(&instr
->instr
, stderr
);
2414 fprintf(stderr
, "\n");
2418 case nir_op_f2u32
: {
2419 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2420 if (instr
->src
[0].src
.ssa
->bit_size
== 16) {
2421 Temp tmp
= bld
.vop1(aco_opcode::v_cvt_f32_f16
, bld
.def(v1
), src
);
2422 if (dst
.type() == RegType::vgpr
) {
2423 bld
.vop1(aco_opcode::v_cvt_u32_f32
, Definition(dst
), tmp
);
2425 bld
.pseudo(aco_opcode::p_as_uniform
, Definition(dst
),
2426 bld
.vop1(aco_opcode::v_cvt_u32_f32
, bld
.def(v1
), tmp
));
2428 } else if (instr
->src
[0].src
.ssa
->bit_size
== 32) {
2429 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_cvt_u32_f32
, dst
);
2430 } else if (instr
->src
[0].src
.ssa
->bit_size
== 64) {
2431 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_cvt_u32_f64
, dst
);
2433 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2434 nir_print_instr(&instr
->instr
, stderr
);
2435 fprintf(stderr
, "\n");
2439 case nir_op_f2i64
: {
2440 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2441 if (instr
->src
[0].src
.ssa
->bit_size
== 16)
2442 src
= bld
.vop1(aco_opcode::v_cvt_f32_f16
, bld
.def(v1
), src
);
2444 if (instr
->src
[0].src
.ssa
->bit_size
<= 32 && dst
.type() == RegType::vgpr
) {
2445 Temp exponent
= bld
.vop1(aco_opcode::v_frexp_exp_i32_f32
, bld
.def(v1
), src
);
2446 exponent
= bld
.vop3(aco_opcode::v_med3_i32
, bld
.def(v1
), Operand(0x0u
), exponent
, Operand(64u));
2447 Temp mantissa
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(0x7fffffu
), src
);
2448 Temp sign
= bld
.vop2(aco_opcode::v_ashrrev_i32
, bld
.def(v1
), Operand(31u), src
);
2449 mantissa
= bld
.vop2(aco_opcode::v_or_b32
, bld
.def(v1
), Operand(0x800000u
), mantissa
);
2450 mantissa
= bld
.vop2(aco_opcode::v_lshlrev_b32
, bld
.def(v1
), Operand(7u), mantissa
);
2451 mantissa
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), Operand(0u), mantissa
);
2452 Temp new_exponent
= bld
.tmp(v1
);
2453 Temp borrow
= bld
.vsub32(Definition(new_exponent
), Operand(63u), exponent
, true).def(1).getTemp();
2454 if (ctx
->program
->chip_class
>= GFX8
)
2455 mantissa
= bld
.vop3(aco_opcode::v_lshrrev_b64
, bld
.def(v2
), new_exponent
, mantissa
);
2457 mantissa
= bld
.vop3(aco_opcode::v_lshr_b64
, bld
.def(v2
), mantissa
, new_exponent
);
2458 Temp saturate
= bld
.vop1(aco_opcode::v_bfrev_b32
, bld
.def(v1
), Operand(0xfffffffeu
));
2459 Temp lower
= bld
.tmp(v1
), upper
= bld
.tmp(v1
);
2460 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lower
), Definition(upper
), mantissa
);
2461 lower
= bld
.vop2_e64(aco_opcode::v_cndmask_b32
, bld
.def(v1
), lower
, Operand(0xffffffffu
), borrow
);
2462 upper
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), upper
, saturate
, borrow
);
2463 lower
= bld
.vop2(aco_opcode::v_xor_b32
, bld
.def(v1
), sign
, lower
);
2464 upper
= bld
.vop2(aco_opcode::v_xor_b32
, bld
.def(v1
), sign
, upper
);
2465 Temp new_lower
= bld
.tmp(v1
);
2466 borrow
= bld
.vsub32(Definition(new_lower
), lower
, sign
, true).def(1).getTemp();
2467 Temp new_upper
= bld
.vsub32(bld
.def(v1
), upper
, sign
, false, borrow
);
2468 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), new_lower
, new_upper
);
2470 } else if (instr
->src
[0].src
.ssa
->bit_size
<= 32 && dst
.type() == RegType::sgpr
) {
2471 if (src
.type() == RegType::vgpr
)
2472 src
= bld
.as_uniform(src
);
2473 Temp exponent
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
), src
, Operand(0x80017u
));
2474 exponent
= bld
.sop2(aco_opcode::s_sub_i32
, bld
.def(s1
), bld
.def(s1
, scc
), exponent
, Operand(126u));
2475 exponent
= bld
.sop2(aco_opcode::s_max_i32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(0u), exponent
);
2476 exponent
= bld
.sop2(aco_opcode::s_min_i32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(64u), exponent
);
2477 Temp mantissa
= bld
.sop2(aco_opcode::s_and_b32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(0x7fffffu
), src
);
2478 Temp sign
= bld
.sop2(aco_opcode::s_ashr_i32
, bld
.def(s1
), bld
.def(s1
, scc
), src
, Operand(31u));
2479 mantissa
= bld
.sop2(aco_opcode::s_or_b32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(0x800000u
), mantissa
);
2480 mantissa
= bld
.sop2(aco_opcode::s_lshl_b32
, bld
.def(s1
), bld
.def(s1
, scc
), mantissa
, Operand(7u));
2481 mantissa
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s2
), Operand(0u), mantissa
);
2482 exponent
= bld
.sop2(aco_opcode::s_sub_u32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(63u), exponent
);
2483 mantissa
= bld
.sop2(aco_opcode::s_lshr_b64
, bld
.def(s2
), bld
.def(s1
, scc
), mantissa
, exponent
);
2484 Temp cond
= bld
.sopc(aco_opcode::s_cmp_eq_u32
, bld
.def(s1
, scc
), exponent
, Operand(0xffffffffu
)); // exp >= 64
2485 Temp saturate
= bld
.sop1(aco_opcode::s_brev_b64
, bld
.def(s2
), Operand(0xfffffffeu
));
2486 mantissa
= bld
.sop2(aco_opcode::s_cselect_b64
, bld
.def(s2
), saturate
, mantissa
, cond
);
2487 Temp lower
= bld
.tmp(s1
), upper
= bld
.tmp(s1
);
2488 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lower
), Definition(upper
), mantissa
);
2489 lower
= bld
.sop2(aco_opcode::s_xor_b32
, bld
.def(s1
), bld
.def(s1
, scc
), sign
, lower
);
2490 upper
= bld
.sop2(aco_opcode::s_xor_b32
, bld
.def(s1
), bld
.def(s1
, scc
), sign
, upper
);
2491 Temp borrow
= bld
.tmp(s1
);
2492 lower
= bld
.sop2(aco_opcode::s_sub_u32
, bld
.def(s1
), bld
.scc(Definition(borrow
)), lower
, sign
);
2493 upper
= bld
.sop2(aco_opcode::s_subb_u32
, bld
.def(s1
), bld
.def(s1
, scc
), upper
, sign
, borrow
);
2494 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lower
, upper
);
2496 } else if (instr
->src
[0].src
.ssa
->bit_size
== 64) {
2497 Temp vec
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s2
), Operand(0u), Operand(0x3df00000u
));
2498 Temp trunc
= emit_trunc_f64(ctx
, bld
, bld
.def(v2
), src
);
2499 Temp mul
= bld
.vop3(aco_opcode::v_mul_f64
, bld
.def(v2
), trunc
, vec
);
2500 vec
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s2
), Operand(0u), Operand(0xc1f00000u
));
2501 Temp floor
= emit_floor_f64(ctx
, bld
, bld
.def(v2
), mul
);
2502 Temp fma
= bld
.vop3(aco_opcode::v_fma_f64
, bld
.def(v2
), floor
, vec
, trunc
);
2503 Temp lower
= bld
.vop1(aco_opcode::v_cvt_u32_f64
, bld
.def(v1
), fma
);
2504 Temp upper
= bld
.vop1(aco_opcode::v_cvt_i32_f64
, bld
.def(v1
), floor
);
2505 if (dst
.type() == RegType::sgpr
) {
2506 lower
= bld
.as_uniform(lower
);
2507 upper
= bld
.as_uniform(upper
);
2509 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lower
, upper
);
2512 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2513 nir_print_instr(&instr
->instr
, stderr
);
2514 fprintf(stderr
, "\n");
2518 case nir_op_f2u64
: {
2519 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2520 if (instr
->src
[0].src
.ssa
->bit_size
== 16)
2521 src
= bld
.vop1(aco_opcode::v_cvt_f32_f16
, bld
.def(v1
), src
);
2523 if (instr
->src
[0].src
.ssa
->bit_size
<= 32 && dst
.type() == RegType::vgpr
) {
2524 Temp exponent
= bld
.vop1(aco_opcode::v_frexp_exp_i32_f32
, bld
.def(v1
), src
);
2525 Temp exponent_in_range
= bld
.vopc(aco_opcode::v_cmp_ge_i32
, bld
.hint_vcc(bld
.def(bld
.lm
)), Operand(64u), exponent
);
2526 exponent
= bld
.vop2(aco_opcode::v_max_i32
, bld
.def(v1
), Operand(0x0u
), exponent
);
2527 Temp mantissa
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(0x7fffffu
), src
);
2528 mantissa
= bld
.vop2(aco_opcode::v_or_b32
, bld
.def(v1
), Operand(0x800000u
), mantissa
);
2529 Temp exponent_small
= bld
.vsub32(bld
.def(v1
), Operand(24u), exponent
);
2530 Temp small
= bld
.vop2(aco_opcode::v_lshrrev_b32
, bld
.def(v1
), exponent_small
, mantissa
);
2531 mantissa
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), Operand(0u), mantissa
);
2532 Temp new_exponent
= bld
.tmp(v1
);
2533 Temp cond_small
= bld
.vsub32(Definition(new_exponent
), exponent
, Operand(24u), true).def(1).getTemp();
2534 if (ctx
->program
->chip_class
>= GFX8
)
2535 mantissa
= bld
.vop3(aco_opcode::v_lshlrev_b64
, bld
.def(v2
), new_exponent
, mantissa
);
2537 mantissa
= bld
.vop3(aco_opcode::v_lshl_b64
, bld
.def(v2
), mantissa
, new_exponent
);
2538 Temp lower
= bld
.tmp(v1
), upper
= bld
.tmp(v1
);
2539 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lower
), Definition(upper
), mantissa
);
2540 lower
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), lower
, small
, cond_small
);
2541 upper
= bld
.vop2_e64(aco_opcode::v_cndmask_b32
, bld
.def(v1
), upper
, Operand(0u), cond_small
);
2542 lower
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), Operand(0xffffffffu
), lower
, exponent_in_range
);
2543 upper
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), Operand(0xffffffffu
), upper
, exponent_in_range
);
2544 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lower
, upper
);
2546 } else if (instr
->src
[0].src
.ssa
->bit_size
<= 32 && dst
.type() == RegType::sgpr
) {
2547 if (src
.type() == RegType::vgpr
)
2548 src
= bld
.as_uniform(src
);
2549 Temp exponent
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
), src
, Operand(0x80017u
));
2550 exponent
= bld
.sop2(aco_opcode::s_sub_i32
, bld
.def(s1
), bld
.def(s1
, scc
), exponent
, Operand(126u));
2551 exponent
= bld
.sop2(aco_opcode::s_max_i32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(0u), exponent
);
2552 Temp mantissa
= bld
.sop2(aco_opcode::s_and_b32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(0x7fffffu
), src
);
2553 mantissa
= bld
.sop2(aco_opcode::s_or_b32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(0x800000u
), mantissa
);
2554 Temp exponent_small
= bld
.sop2(aco_opcode::s_sub_u32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(24u), exponent
);
2555 Temp small
= bld
.sop2(aco_opcode::s_lshr_b32
, bld
.def(s1
), bld
.def(s1
, scc
), mantissa
, exponent_small
);
2556 mantissa
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s2
), Operand(0u), mantissa
);
2557 Temp exponent_large
= bld
.sop2(aco_opcode::s_sub_u32
, bld
.def(s1
), bld
.def(s1
, scc
), exponent
, Operand(24u));
2558 mantissa
= bld
.sop2(aco_opcode::s_lshl_b64
, bld
.def(s2
), bld
.def(s1
, scc
), mantissa
, exponent_large
);
2559 Temp cond
= bld
.sopc(aco_opcode::s_cmp_ge_i32
, bld
.def(s1
, scc
), Operand(64u), exponent
);
2560 mantissa
= bld
.sop2(aco_opcode::s_cselect_b64
, bld
.def(s2
), mantissa
, Operand(0xffffffffu
), cond
);
2561 Temp lower
= bld
.tmp(s1
), upper
= bld
.tmp(s1
);
2562 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lower
), Definition(upper
), mantissa
);
2563 Temp cond_small
= bld
.sopc(aco_opcode::s_cmp_le_i32
, bld
.def(s1
, scc
), exponent
, Operand(24u));
2564 lower
= bld
.sop2(aco_opcode::s_cselect_b32
, bld
.def(s1
), small
, lower
, cond_small
);
2565 upper
= bld
.sop2(aco_opcode::s_cselect_b32
, bld
.def(s1
), Operand(0u), upper
, cond_small
);
2566 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lower
, upper
);
2568 } else if (instr
->src
[0].src
.ssa
->bit_size
== 64) {
2569 Temp vec
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s2
), Operand(0u), Operand(0x3df00000u
));
2570 Temp trunc
= emit_trunc_f64(ctx
, bld
, bld
.def(v2
), src
);
2571 Temp mul
= bld
.vop3(aco_opcode::v_mul_f64
, bld
.def(v2
), trunc
, vec
);
2572 vec
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s2
), Operand(0u), Operand(0xc1f00000u
));
2573 Temp floor
= emit_floor_f64(ctx
, bld
, bld
.def(v2
), mul
);
2574 Temp fma
= bld
.vop3(aco_opcode::v_fma_f64
, bld
.def(v2
), floor
, vec
, trunc
);
2575 Temp lower
= bld
.vop1(aco_opcode::v_cvt_u32_f64
, bld
.def(v1
), fma
);
2576 Temp upper
= bld
.vop1(aco_opcode::v_cvt_u32_f64
, bld
.def(v1
), floor
);
2577 if (dst
.type() == RegType::sgpr
) {
2578 lower
= bld
.as_uniform(lower
);
2579 upper
= bld
.as_uniform(upper
);
2581 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lower
, upper
);
2584 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2585 nir_print_instr(&instr
->instr
, stderr
);
2586 fprintf(stderr
, "\n");
2590 case nir_op_b2f16
: {
2591 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2592 assert(src
.regClass() == bld
.lm
);
2594 if (dst
.regClass() == s1
) {
2595 src
= bool_to_scalar_condition(ctx
, src
);
2596 bld
.sop2(aco_opcode::s_mul_i32
, Definition(dst
), Operand(0x3c00u
), src
);
2597 } else if (dst
.regClass() == v2b
) {
2598 Temp one
= bld
.copy(bld
.def(v1
), Operand(0x3c00u
));
2599 bld
.vop2(aco_opcode::v_cndmask_b32
, Definition(dst
), Operand(0u), one
, src
);
2601 unreachable("Wrong destination register class for nir_op_b2f16.");
2605 case nir_op_b2f32
: {
2606 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2607 assert(src
.regClass() == bld
.lm
);
2609 if (dst
.regClass() == s1
) {
2610 src
= bool_to_scalar_condition(ctx
, src
);
2611 bld
.sop2(aco_opcode::s_mul_i32
, Definition(dst
), Operand(0x3f800000u
), src
);
2612 } else if (dst
.regClass() == v1
) {
2613 bld
.vop2_e64(aco_opcode::v_cndmask_b32
, Definition(dst
), Operand(0u), Operand(0x3f800000u
), src
);
2615 unreachable("Wrong destination register class for nir_op_b2f32.");
2619 case nir_op_b2f64
: {
2620 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2621 assert(src
.regClass() == bld
.lm
);
2623 if (dst
.regClass() == s2
) {
2624 src
= bool_to_scalar_condition(ctx
, src
);
2625 bld
.sop2(aco_opcode::s_cselect_b64
, Definition(dst
), Operand(0x3f800000u
), Operand(0u), bld
.scc(src
));
2626 } else if (dst
.regClass() == v2
) {
2627 Temp one
= bld
.vop1(aco_opcode::v_mov_b32
, bld
.def(v2
), Operand(0x3FF00000u
));
2628 Temp upper
= bld
.vop2_e64(aco_opcode::v_cndmask_b32
, bld
.def(v1
), Operand(0u), one
, src
);
2629 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), Operand(0u), upper
);
2631 unreachable("Wrong destination register class for nir_op_b2f64.");
2638 case nir_op_i2i64
: {
2639 convert_int(ctx
, bld
, get_alu_src(ctx
, instr
->src
[0]),
2640 instr
->src
[0].src
.ssa
->bit_size
, instr
->dest
.dest
.ssa
.bit_size
, true, dst
);
2646 case nir_op_u2u64
: {
2647 convert_int(ctx
, bld
, get_alu_src(ctx
, instr
->src
[0]),
2648 instr
->src
[0].src
.ssa
->bit_size
, instr
->dest
.dest
.ssa
.bit_size
, false, dst
);
2652 case nir_op_b2i32
: {
2653 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2654 assert(src
.regClass() == bld
.lm
);
2656 if (dst
.regClass() == s1
) {
2657 // TODO: in a post-RA optimization, we can check if src is in VCC, and directly use VCCNZ
2658 bool_to_scalar_condition(ctx
, src
, dst
);
2659 } else if (dst
.regClass() == v1
) {
2660 bld
.vop2_e64(aco_opcode::v_cndmask_b32
, Definition(dst
), Operand(0u), Operand(1u), src
);
2662 unreachable("Invalid register class for b2i32");
2668 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2669 assert(dst
.regClass() == bld
.lm
);
2671 if (src
.type() == RegType::vgpr
) {
2672 assert(src
.regClass() == v1
|| src
.regClass() == v2
);
2673 assert(dst
.regClass() == bld
.lm
);
2674 bld
.vopc(src
.size() == 2 ? aco_opcode::v_cmp_lg_u64
: aco_opcode::v_cmp_lg_u32
,
2675 Definition(dst
), Operand(0u), src
).def(0).setHint(vcc
);
2677 assert(src
.regClass() == s1
|| src
.regClass() == s2
);
2679 if (src
.regClass() == s2
&& ctx
->program
->chip_class
<= GFX7
) {
2680 tmp
= bld
.sop2(aco_opcode::s_or_b64
, bld
.def(s2
), bld
.def(s1
, scc
), Operand(0u), src
).def(1).getTemp();
2682 tmp
= bld
.sopc(src
.size() == 2 ? aco_opcode::s_cmp_lg_u64
: aco_opcode::s_cmp_lg_u32
,
2683 bld
.scc(bld
.def(s1
)), Operand(0u), src
);
2685 bool_to_vector_condition(ctx
, tmp
, dst
);
2689 case nir_op_pack_64_2x32_split
: {
2690 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
2691 Temp src1
= get_alu_src(ctx
, instr
->src
[1]);
2693 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), src0
, src1
);
2696 case nir_op_unpack_64_2x32_split_x
:
2697 bld
.pseudo(aco_opcode::p_split_vector
, Definition(dst
), bld
.def(dst
.regClass()), get_alu_src(ctx
, instr
->src
[0]));
2699 case nir_op_unpack_64_2x32_split_y
:
2700 bld
.pseudo(aco_opcode::p_split_vector
, bld
.def(dst
.regClass()), Definition(dst
), get_alu_src(ctx
, instr
->src
[0]));
2702 case nir_op_unpack_32_2x16_split_x
:
2703 if (dst
.type() == RegType::vgpr
) {
2704 bld
.pseudo(aco_opcode::p_split_vector
, Definition(dst
), bld
.def(dst
.regClass()), get_alu_src(ctx
, instr
->src
[0]));
2706 bld
.copy(Definition(dst
), get_alu_src(ctx
, instr
->src
[0]));
2709 case nir_op_unpack_32_2x16_split_y
:
2710 if (dst
.type() == RegType::vgpr
) {
2711 bld
.pseudo(aco_opcode::p_split_vector
, bld
.def(dst
.regClass()), Definition(dst
), get_alu_src(ctx
, instr
->src
[0]));
2713 bld
.sop2(aco_opcode::s_bfe_u32
, Definition(dst
), bld
.def(s1
, scc
), get_alu_src(ctx
, instr
->src
[0]), Operand(uint32_t(16 << 16 | 16)));
2716 case nir_op_pack_32_2x16_split
: {
2717 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
2718 Temp src1
= get_alu_src(ctx
, instr
->src
[1]);
2719 if (dst
.regClass() == v1
) {
2720 src0
= emit_extract_vector(ctx
, src0
, 0, v2b
);
2721 src1
= emit_extract_vector(ctx
, src1
, 0, v2b
);
2722 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), src0
, src1
);
2724 src0
= bld
.sop2(aco_opcode::s_and_b32
, bld
.def(s1
), bld
.def(s1
, scc
), src0
, Operand(0xFFFFu
));
2725 src1
= bld
.sop2(aco_opcode::s_lshl_b32
, bld
.def(s1
), bld
.def(s1
, scc
), src1
, Operand(16u));
2726 bld
.sop2(aco_opcode::s_or_b32
, Definition(dst
), bld
.def(s1
, scc
), src0
, src1
);
2730 case nir_op_pack_half_2x16
: {
2731 Temp src
= get_alu_src(ctx
, instr
->src
[0], 2);
2733 if (dst
.regClass() == v1
) {
2734 Temp src0
= bld
.tmp(v1
);
2735 Temp src1
= bld
.tmp(v1
);
2736 bld
.pseudo(aco_opcode::p_split_vector
, Definition(src0
), Definition(src1
), src
);
2737 if (!ctx
->block
->fp_mode
.care_about_round32
|| ctx
->block
->fp_mode
.round32
== fp_round_tz
)
2738 bld
.vop3(aco_opcode::v_cvt_pkrtz_f16_f32
, Definition(dst
), src0
, src1
);
2740 bld
.vop3(aco_opcode::v_cvt_pk_u16_u32
, Definition(dst
),
2741 bld
.vop1(aco_opcode::v_cvt_f32_f16
, bld
.def(v1
), src0
),
2742 bld
.vop1(aco_opcode::v_cvt_f32_f16
, bld
.def(v1
), src1
));
2744 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2745 nir_print_instr(&instr
->instr
, stderr
);
2746 fprintf(stderr
, "\n");
2750 case nir_op_unpack_half_2x16_split_x
: {
2751 if (dst
.regClass() == v1
) {
2752 bld
.vop1(aco_opcode::v_cvt_f32_f16
, Definition(dst
), get_alu_src(ctx
, instr
->src
[0]));
2754 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2755 nir_print_instr(&instr
->instr
, stderr
);
2756 fprintf(stderr
, "\n");
2760 case nir_op_unpack_half_2x16_split_y
: {
2761 if (dst
.regClass() == v1
) {
2762 /* TODO: use SDWA here */
2763 bld
.vop1(aco_opcode::v_cvt_f32_f16
, Definition(dst
),
2764 bld
.vop2(aco_opcode::v_lshrrev_b32
, bld
.def(v1
), Operand(16u), as_vgpr(ctx
, get_alu_src(ctx
, instr
->src
[0]))));
2766 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2767 nir_print_instr(&instr
->instr
, stderr
);
2768 fprintf(stderr
, "\n");
2772 case nir_op_fquantize2f16
: {
2773 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2774 Temp f16
= bld
.vop1(aco_opcode::v_cvt_f16_f32
, bld
.def(v1
), src
);
2777 if (ctx
->program
->chip_class
>= GFX8
) {
2778 Temp mask
= bld
.copy(bld
.def(s1
), Operand(0x36Fu
)); /* value is NOT negative/positive denormal value */
2779 cmp_res
= bld
.vopc_e64(aco_opcode::v_cmp_class_f16
, bld
.hint_vcc(bld
.def(bld
.lm
)), f16
, mask
);
2780 f32
= bld
.vop1(aco_opcode::v_cvt_f32_f16
, bld
.def(v1
), f16
);
2782 /* 0x38800000 is smallest half float value (2^-14) in 32-bit float,
2783 * so compare the result and flush to 0 if it's smaller.
2785 f32
= bld
.vop1(aco_opcode::v_cvt_f32_f16
, bld
.def(v1
), f16
);
2786 Temp smallest
= bld
.copy(bld
.def(s1
), Operand(0x38800000u
));
2787 Instruction
* vop3
= bld
.vopc_e64(aco_opcode::v_cmp_nlt_f32
, bld
.hint_vcc(bld
.def(bld
.lm
)), f32
, smallest
);
2788 static_cast<VOP3A_instruction
*>(vop3
)->abs
[0] = true;
2789 cmp_res
= vop3
->definitions
[0].getTemp();
2792 if (ctx
->block
->fp_mode
.preserve_signed_zero_inf_nan32
|| ctx
->program
->chip_class
< GFX8
) {
2793 Temp copysign_0
= bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), Operand(0u), as_vgpr(ctx
, src
));
2794 bld
.vop2(aco_opcode::v_cndmask_b32
, Definition(dst
), copysign_0
, f32
, cmp_res
);
2796 bld
.vop2(aco_opcode::v_cndmask_b32
, Definition(dst
), Operand(0u), f32
, cmp_res
);
2801 Temp bits
= get_alu_src(ctx
, instr
->src
[0]);
2802 Temp offset
= get_alu_src(ctx
, instr
->src
[1]);
2804 if (dst
.regClass() == s1
) {
2805 bld
.sop2(aco_opcode::s_bfm_b32
, Definition(dst
), bits
, offset
);
2806 } else if (dst
.regClass() == v1
) {
2807 bld
.vop3(aco_opcode::v_bfm_b32
, Definition(dst
), bits
, offset
);
2809 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2810 nir_print_instr(&instr
->instr
, stderr
);
2811 fprintf(stderr
, "\n");
2815 case nir_op_bitfield_select
: {
2816 /* (mask & insert) | (~mask & base) */
2817 Temp bitmask
= get_alu_src(ctx
, instr
->src
[0]);
2818 Temp insert
= get_alu_src(ctx
, instr
->src
[1]);
2819 Temp base
= get_alu_src(ctx
, instr
->src
[2]);
2821 /* dst = (insert & bitmask) | (base & ~bitmask) */
2822 if (dst
.regClass() == s1
) {
2823 aco_ptr
<Instruction
> sop2
;
2824 nir_const_value
* const_bitmask
= nir_src_as_const_value(instr
->src
[0].src
);
2825 nir_const_value
* const_insert
= nir_src_as_const_value(instr
->src
[1].src
);
2827 if (const_insert
&& const_bitmask
) {
2828 lhs
= Operand(const_insert
->u32
& const_bitmask
->u32
);
2830 insert
= bld
.sop2(aco_opcode::s_and_b32
, bld
.def(s1
), bld
.def(s1
, scc
), insert
, bitmask
);
2831 lhs
= Operand(insert
);
2835 nir_const_value
* const_base
= nir_src_as_const_value(instr
->src
[2].src
);
2836 if (const_base
&& const_bitmask
) {
2837 rhs
= Operand(const_base
->u32
& ~const_bitmask
->u32
);
2839 base
= bld
.sop2(aco_opcode::s_andn2_b32
, bld
.def(s1
), bld
.def(s1
, scc
), base
, bitmask
);
2840 rhs
= Operand(base
);
2843 bld
.sop2(aco_opcode::s_or_b32
, Definition(dst
), bld
.def(s1
, scc
), rhs
, lhs
);
2845 } else if (dst
.regClass() == v1
) {
2846 if (base
.type() == RegType::sgpr
&& (bitmask
.type() == RegType::sgpr
|| (insert
.type() == RegType::sgpr
)))
2847 base
= as_vgpr(ctx
, base
);
2848 if (insert
.type() == RegType::sgpr
&& bitmask
.type() == RegType::sgpr
)
2849 insert
= as_vgpr(ctx
, insert
);
2851 bld
.vop3(aco_opcode::v_bfi_b32
, Definition(dst
), bitmask
, insert
, base
);
2854 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2855 nir_print_instr(&instr
->instr
, stderr
);
2856 fprintf(stderr
, "\n");
2862 Temp base
= get_alu_src(ctx
, instr
->src
[0]);
2863 Temp offset
= get_alu_src(ctx
, instr
->src
[1]);
2864 Temp bits
= get_alu_src(ctx
, instr
->src
[2]);
2866 if (dst
.type() == RegType::sgpr
) {
2868 nir_const_value
* const_offset
= nir_src_as_const_value(instr
->src
[1].src
);
2869 nir_const_value
* const_bits
= nir_src_as_const_value(instr
->src
[2].src
);
2870 if (const_offset
&& const_bits
) {
2871 uint32_t const_extract
= (const_bits
->u32
<< 16) | const_offset
->u32
;
2872 extract
= Operand(const_extract
);
2876 width
= Operand(const_bits
->u32
<< 16);
2878 width
= bld
.sop2(aco_opcode::s_lshl_b32
, bld
.def(s1
), bld
.def(s1
, scc
), bits
, Operand(16u));
2880 extract
= bld
.sop2(aco_opcode::s_or_b32
, bld
.def(s1
), bld
.def(s1
, scc
), offset
, width
);
2884 if (dst
.regClass() == s1
) {
2885 if (instr
->op
== nir_op_ubfe
)
2886 opcode
= aco_opcode::s_bfe_u32
;
2888 opcode
= aco_opcode::s_bfe_i32
;
2889 } else if (dst
.regClass() == s2
) {
2890 if (instr
->op
== nir_op_ubfe
)
2891 opcode
= aco_opcode::s_bfe_u64
;
2893 opcode
= aco_opcode::s_bfe_i64
;
2895 unreachable("Unsupported BFE bit size");
2898 bld
.sop2(opcode
, Definition(dst
), bld
.def(s1
, scc
), base
, extract
);
2902 if (dst
.regClass() == v1
) {
2903 if (instr
->op
== nir_op_ubfe
)
2904 opcode
= aco_opcode::v_bfe_u32
;
2906 opcode
= aco_opcode::v_bfe_i32
;
2908 unreachable("Unsupported BFE bit size");
2911 emit_vop3a_instruction(ctx
, instr
, opcode
, dst
);
2915 case nir_op_bit_count
: {
2916 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2917 if (src
.regClass() == s1
) {
2918 bld
.sop1(aco_opcode::s_bcnt1_i32_b32
, Definition(dst
), bld
.def(s1
, scc
), src
);
2919 } else if (src
.regClass() == v1
) {
2920 bld
.vop3(aco_opcode::v_bcnt_u32_b32
, Definition(dst
), src
, Operand(0u));
2921 } else if (src
.regClass() == v2
) {
2922 bld
.vop3(aco_opcode::v_bcnt_u32_b32
, Definition(dst
),
2923 emit_extract_vector(ctx
, src
, 1, v1
),
2924 bld
.vop3(aco_opcode::v_bcnt_u32_b32
, bld
.def(v1
),
2925 emit_extract_vector(ctx
, src
, 0, v1
), Operand(0u)));
2926 } else if (src
.regClass() == s2
) {
2927 bld
.sop1(aco_opcode::s_bcnt1_i32_b64
, Definition(dst
), bld
.def(s1
, scc
), src
);
2929 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2930 nir_print_instr(&instr
->instr
, stderr
);
2931 fprintf(stderr
, "\n");
2936 emit_comparison(ctx
, instr
, dst
, aco_opcode::v_cmp_lt_f16
, aco_opcode::v_cmp_lt_f32
, aco_opcode::v_cmp_lt_f64
);
2940 emit_comparison(ctx
, instr
, dst
, aco_opcode::v_cmp_ge_f16
, aco_opcode::v_cmp_ge_f32
, aco_opcode::v_cmp_ge_f64
);
2944 emit_comparison(ctx
, instr
, dst
, aco_opcode::v_cmp_eq_f16
, aco_opcode::v_cmp_eq_f32
, aco_opcode::v_cmp_eq_f64
);
2948 emit_comparison(ctx
, instr
, dst
, aco_opcode::v_cmp_neq_f16
, aco_opcode::v_cmp_neq_f32
, aco_opcode::v_cmp_neq_f64
);
2952 emit_comparison(ctx
, instr
, dst
, aco_opcode::v_cmp_lt_i16
, aco_opcode::v_cmp_lt_i32
, aco_opcode::v_cmp_lt_i64
, aco_opcode::s_cmp_lt_i32
);
2956 emit_comparison(ctx
, instr
, dst
, aco_opcode::v_cmp_ge_i16
, aco_opcode::v_cmp_ge_i32
, aco_opcode::v_cmp_ge_i64
, aco_opcode::s_cmp_ge_i32
);
2960 if (instr
->src
[0].src
.ssa
->bit_size
== 1)
2961 emit_boolean_logic(ctx
, instr
, Builder::s_xnor
, dst
);
2963 emit_comparison(ctx
, instr
, dst
, aco_opcode::v_cmp_eq_i16
, aco_opcode::v_cmp_eq_i32
, aco_opcode::v_cmp_eq_i64
, aco_opcode::s_cmp_eq_i32
,
2964 ctx
->program
->chip_class
>= GFX8
? aco_opcode::s_cmp_eq_u64
: aco_opcode::num_opcodes
);
2968 if (instr
->src
[0].src
.ssa
->bit_size
== 1)
2969 emit_boolean_logic(ctx
, instr
, Builder::s_xor
, dst
);
2971 emit_comparison(ctx
, instr
, dst
, aco_opcode::v_cmp_lg_i16
, aco_opcode::v_cmp_lg_i32
, aco_opcode::v_cmp_lg_i64
, aco_opcode::s_cmp_lg_i32
,
2972 ctx
->program
->chip_class
>= GFX8
? aco_opcode::s_cmp_lg_u64
: aco_opcode::num_opcodes
);
2976 emit_comparison(ctx
, instr
, dst
, aco_opcode::v_cmp_lt_u16
, aco_opcode::v_cmp_lt_u32
, aco_opcode::v_cmp_lt_u64
, aco_opcode::s_cmp_lt_u32
);
2980 emit_comparison(ctx
, instr
, dst
, aco_opcode::v_cmp_ge_u16
, aco_opcode::v_cmp_ge_u32
, aco_opcode::v_cmp_ge_u64
, aco_opcode::s_cmp_ge_u32
);
2985 case nir_op_fddx_fine
:
2986 case nir_op_fddy_fine
:
2987 case nir_op_fddx_coarse
:
2988 case nir_op_fddy_coarse
: {
2989 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2990 uint16_t dpp_ctrl1
, dpp_ctrl2
;
2991 if (instr
->op
== nir_op_fddx_fine
) {
2992 dpp_ctrl1
= dpp_quad_perm(0, 0, 2, 2);
2993 dpp_ctrl2
= dpp_quad_perm(1, 1, 3, 3);
2994 } else if (instr
->op
== nir_op_fddy_fine
) {
2995 dpp_ctrl1
= dpp_quad_perm(0, 1, 0, 1);
2996 dpp_ctrl2
= dpp_quad_perm(2, 3, 2, 3);
2998 dpp_ctrl1
= dpp_quad_perm(0, 0, 0, 0);
2999 if (instr
->op
== nir_op_fddx
|| instr
->op
== nir_op_fddx_coarse
)
3000 dpp_ctrl2
= dpp_quad_perm(1, 1, 1, 1);
3002 dpp_ctrl2
= dpp_quad_perm(2, 2, 2, 2);
3006 if (ctx
->program
->chip_class
>= GFX8
) {
3007 Temp tl
= bld
.vop1_dpp(aco_opcode::v_mov_b32
, bld
.def(v1
), src
, dpp_ctrl1
);
3008 tmp
= bld
.vop2_dpp(aco_opcode::v_sub_f32
, bld
.def(v1
), src
, tl
, dpp_ctrl2
);
3010 Temp tl
= bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), src
, (1 << 15) | dpp_ctrl1
);
3011 Temp tr
= bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), src
, (1 << 15) | dpp_ctrl2
);
3012 tmp
= bld
.vop2(aco_opcode::v_sub_f32
, bld
.def(v1
), tr
, tl
);
3014 emit_wqm(ctx
, tmp
, dst
, true);
3018 fprintf(stderr
, "Unknown NIR ALU instr: ");
3019 nir_print_instr(&instr
->instr
, stderr
);
3020 fprintf(stderr
, "\n");
3024 void visit_load_const(isel_context
*ctx
, nir_load_const_instr
*instr
)
3026 Temp dst
= get_ssa_temp(ctx
, &instr
->def
);
3028 // TODO: we really want to have the resulting type as this would allow for 64bit literals
3029 // which get truncated the lsb if double and msb if int
3030 // for now, we only use s_mov_b64 with 64bit inline constants
3031 assert(instr
->def
.num_components
== 1 && "Vector load_const should be lowered to scalar.");
3032 assert(dst
.type() == RegType::sgpr
);
3034 Builder
bld(ctx
->program
, ctx
->block
);
3036 if (instr
->def
.bit_size
== 1) {
3037 assert(dst
.regClass() == bld
.lm
);
3038 int val
= instr
->value
[0].b
? -1 : 0;
3039 Operand op
= bld
.lm
.size() == 1 ? Operand((uint32_t) val
) : Operand((uint64_t) val
);
3040 bld
.sop1(Builder::s_mov
, Definition(dst
), op
);
3041 } else if (instr
->def
.bit_size
== 8) {
3042 /* ensure that the value is correctly represented in the low byte of the register */
3043 bld
.sopk(aco_opcode::s_movk_i32
, Definition(dst
), instr
->value
[0].u8
);
3044 } else if (instr
->def
.bit_size
== 16) {
3045 /* ensure that the value is correctly represented in the low half of the register */
3046 bld
.sopk(aco_opcode::s_movk_i32
, Definition(dst
), instr
->value
[0].u16
);
3047 } else if (dst
.size() == 1) {
3048 bld
.copy(Definition(dst
), Operand(instr
->value
[0].u32
));
3050 assert(dst
.size() != 1);
3051 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, dst
.size(), 1)};
3052 if (instr
->def
.bit_size
== 64)
3053 for (unsigned i
= 0; i
< dst
.size(); i
++)
3054 vec
->operands
[i
] = Operand
{(uint32_t)(instr
->value
[0].u64
>> i
* 32)};
3056 for (unsigned i
= 0; i
< dst
.size(); i
++)
3057 vec
->operands
[i
] = Operand
{instr
->value
[i
].u32
};
3059 vec
->definitions
[0] = Definition(dst
);
3060 ctx
->block
->instructions
.emplace_back(std::move(vec
));
3064 uint32_t widen_mask(uint32_t mask
, unsigned multiplier
)
3066 uint32_t new_mask
= 0;
3067 for(unsigned i
= 0; i
< 32 && (1u << i
) <= mask
; ++i
)
3068 if (mask
& (1u << i
))
3069 new_mask
|= ((1u << multiplier
) - 1u) << (i
* multiplier
);
3073 struct LoadEmitInfo
{
3076 unsigned num_components
;
3077 unsigned component_size
;
3078 Temp resource
= Temp(0, s1
);
3079 unsigned component_stride
= 0;
3080 unsigned const_offset
= 0;
3081 unsigned align_mul
= 0;
3082 unsigned align_offset
= 0;
3085 unsigned swizzle_component_size
= 0;
3086 barrier_interaction barrier
= barrier_none
;
3087 bool can_reorder
= true;
3088 Temp soffset
= Temp(0, s1
);
3091 using LoadCallback
= Temp(*)(
3092 Builder
& bld
, const LoadEmitInfo
* info
, Temp offset
, unsigned bytes_needed
,
3093 unsigned align
, unsigned const_offset
, Temp dst_hint
);
3095 template <LoadCallback callback
, bool byte_align_loads
, bool supports_8bit_16bit_loads
, unsigned max_const_offset_plus_one
>
3096 void emit_load(isel_context
*ctx
, Builder
& bld
, const LoadEmitInfo
*info
)
3098 unsigned load_size
= info
->num_components
* info
->component_size
;
3099 unsigned component_size
= info
->component_size
;
3101 unsigned num_vals
= 0;
3102 Temp vals
[info
->dst
.bytes()];
3104 unsigned const_offset
= info
->const_offset
;
3106 unsigned align_mul
= info
->align_mul
? info
->align_mul
: component_size
;
3107 unsigned align_offset
= (info
->align_offset
+ const_offset
) % align_mul
;
3109 unsigned bytes_read
= 0;
3110 while (bytes_read
< load_size
) {
3111 unsigned bytes_needed
= load_size
- bytes_read
;
3113 /* add buffer for unaligned loads */
3114 int byte_align
= align_mul
% 4 == 0 ? align_offset
% 4 : -1;
3117 if ((bytes_needed
> 2 ||
3118 (bytes_needed
== 2 && (align_mul
% 2 || align_offset
% 2)) ||
3119 !supports_8bit_16bit_loads
) && byte_align_loads
) {
3120 if (info
->component_stride
) {
3121 assert(supports_8bit_16bit_loads
&& "unimplemented");
3125 bytes_needed
+= byte_align
== -1 ? 4 - info
->align_mul
: byte_align
;
3126 bytes_needed
= align(bytes_needed
, 4);
3133 if (info
->swizzle_component_size
)
3134 bytes_needed
= MIN2(bytes_needed
, info
->swizzle_component_size
);
3135 if (info
->component_stride
)
3136 bytes_needed
= MIN2(bytes_needed
, info
->component_size
);
3138 bool need_to_align_offset
= byte_align
&& (align_mul
% 4 || align_offset
% 4);
3140 /* reduce constant offset */
3141 Operand offset
= info
->offset
;
3142 unsigned reduced_const_offset
= const_offset
;
3143 bool remove_const_offset_completely
= need_to_align_offset
;
3144 if (const_offset
&& (remove_const_offset_completely
|| const_offset
>= max_const_offset_plus_one
)) {
3145 unsigned to_add
= const_offset
;
3146 if (remove_const_offset_completely
) {
3147 reduced_const_offset
= 0;
3149 to_add
= const_offset
/ max_const_offset_plus_one
* max_const_offset_plus_one
;
3150 reduced_const_offset
%= max_const_offset_plus_one
;
3152 Temp offset_tmp
= offset
.isTemp() ? offset
.getTemp() : Temp();
3153 if (offset
.isConstant()) {
3154 offset
= Operand(offset
.constantValue() + to_add
);
3155 } else if (offset_tmp
.regClass() == s1
) {
3156 offset
= bld
.sop2(aco_opcode::s_add_i32
, bld
.def(s1
), bld
.def(s1
, scc
),
3157 offset_tmp
, Operand(to_add
));
3158 } else if (offset_tmp
.regClass() == v1
) {
3159 offset
= bld
.vadd32(bld
.def(v1
), offset_tmp
, Operand(to_add
));
3161 Temp lo
= bld
.tmp(offset_tmp
.type(), 1);
3162 Temp hi
= bld
.tmp(offset_tmp
.type(), 1);
3163 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lo
), Definition(hi
), offset_tmp
);
3165 if (offset_tmp
.regClass() == s2
) {
3166 Temp carry
= bld
.tmp(s1
);
3167 lo
= bld
.sop2(aco_opcode::s_add_u32
, bld
.def(s1
), bld
.scc(Definition(carry
)), lo
, Operand(to_add
));
3168 hi
= bld
.sop2(aco_opcode::s_add_u32
, bld
.def(s1
), bld
.def(s1
, scc
), hi
, carry
);
3169 offset
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s2
), lo
, hi
);
3171 Temp new_lo
= bld
.tmp(v1
);
3172 Temp carry
= bld
.vadd32(Definition(new_lo
), lo
, Operand(to_add
), true).def(1).getTemp();
3173 hi
= bld
.vadd32(bld
.def(v1
), hi
, Operand(0u), false, carry
);
3174 offset
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), new_lo
, hi
);
3179 /* align offset down if needed */
3180 Operand aligned_offset
= offset
;
3181 if (need_to_align_offset
) {
3182 Temp offset_tmp
= offset
.isTemp() ? offset
.getTemp() : Temp();
3183 if (offset
.isConstant()) {
3184 aligned_offset
= Operand(offset
.constantValue() & 0xfffffffcu
);
3185 } else if (offset_tmp
.regClass() == s1
) {
3186 aligned_offset
= bld
.sop2(aco_opcode::s_and_b32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(0xfffffffcu
), offset_tmp
);
3187 } else if (offset_tmp
.regClass() == s2
) {
3188 aligned_offset
= bld
.sop2(aco_opcode::s_and_b64
, bld
.def(s2
), bld
.def(s1
, scc
), Operand((uint64_t)0xfffffffffffffffcllu
), offset_tmp
);
3189 } else if (offset_tmp
.regClass() == v1
) {
3190 aligned_offset
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(0xfffffffcu
), offset_tmp
);
3191 } else if (offset_tmp
.regClass() == v2
) {
3192 Temp hi
= bld
.tmp(v1
), lo
= bld
.tmp(v1
);
3193 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lo
), Definition(hi
), offset_tmp
);
3194 lo
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(0xfffffffcu
), lo
);
3195 aligned_offset
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), lo
, hi
);
3198 Temp aligned_offset_tmp
= aligned_offset
.isTemp() ? aligned_offset
.getTemp() :
3199 bld
.copy(bld
.def(s1
), aligned_offset
);
3201 unsigned align
= align_offset
? 1 << (ffs(align_offset
) - 1) : align_mul
;
3202 Temp val
= callback(bld
, info
, aligned_offset_tmp
, bytes_needed
, align
,
3203 reduced_const_offset
, byte_align
? Temp() : info
->dst
);
3205 /* the callback wrote directly to dst */
3206 if (val
== info
->dst
) {
3207 assert(num_vals
== 0);
3208 emit_split_vector(ctx
, info
->dst
, info
->num_components
);
3212 /* shift result right if needed */
3213 if (info
->component_size
< 4 && byte_align_loads
) {
3214 Operand
align((uint32_t)byte_align
);
3215 if (byte_align
== -1) {
3216 if (offset
.isConstant())
3217 align
= Operand(offset
.constantValue() % 4u);
3218 else if (offset
.size() == 2)
3219 align
= Operand(emit_extract_vector(ctx
, offset
.getTemp(), 0, RegClass(offset
.getTemp().type(), 1)));
3224 assert(val
.bytes() >= load_size
&& "unimplemented");
3225 if (val
.type() == RegType::sgpr
)
3226 byte_align_scalar(ctx
, val
, align
, info
->dst
);
3228 byte_align_vector(ctx
, val
, align
, info
->dst
, component_size
);
3232 /* add result to list and advance */
3233 if (info
->component_stride
) {
3234 assert(val
.bytes() == info
->component_size
&& "unimplemented");
3235 const_offset
+= info
->component_stride
;
3236 align_offset
= (align_offset
+ info
->component_stride
) % align_mul
;
3238 const_offset
+= val
.bytes();
3239 align_offset
= (align_offset
+ val
.bytes()) % align_mul
;
3241 bytes_read
+= val
.bytes();
3242 vals
[num_vals
++] = val
;
3245 /* create array of components */
3246 unsigned components_split
= 0;
3247 std::array
<Temp
, NIR_MAX_VEC_COMPONENTS
> allocated_vec
;
3248 bool has_vgprs
= false;
3249 for (unsigned i
= 0; i
< num_vals
;) {
3251 unsigned num_tmps
= 0;
3252 unsigned tmp_size
= 0;
3253 RegType reg_type
= RegType::sgpr
;
3254 while ((!tmp_size
|| (tmp_size
% component_size
)) && i
< num_vals
) {
3255 if (vals
[i
].type() == RegType::vgpr
)
3256 reg_type
= RegType::vgpr
;
3257 tmp_size
+= vals
[i
].bytes();
3258 tmp
[num_tmps
++] = vals
[i
++];
3261 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(
3262 aco_opcode::p_create_vector
, Format::PSEUDO
, num_tmps
, 1)};
3263 for (unsigned i
= 0; i
< num_vals
; i
++)
3264 vec
->operands
[i
] = Operand(tmp
[i
]);
3265 tmp
[0] = bld
.tmp(RegClass::get(reg_type
, tmp_size
));
3266 vec
->definitions
[0] = Definition(tmp
[0]);
3267 bld
.insert(std::move(vec
));
3270 if (tmp
[0].bytes() % component_size
) {
3272 assert(i
== num_vals
);
3273 RegClass new_rc
= RegClass::get(reg_type
, tmp
[0].bytes() / component_size
* component_size
);
3274 tmp
[0] = bld
.pseudo(aco_opcode::p_extract_vector
, bld
.def(new_rc
), tmp
[0], Operand(0u));
3277 RegClass elem_rc
= RegClass::get(reg_type
, component_size
);
3279 unsigned start
= components_split
;
3281 if (tmp_size
== elem_rc
.bytes()) {
3282 allocated_vec
[components_split
++] = tmp
[0];
3284 assert(tmp_size
% elem_rc
.bytes() == 0);
3285 aco_ptr
<Pseudo_instruction
> split
{create_instruction
<Pseudo_instruction
>(
3286 aco_opcode::p_split_vector
, Format::PSEUDO
, 1, tmp_size
/ elem_rc
.bytes())};
3287 for (unsigned i
= 0; i
< split
->definitions
.size(); i
++) {
3288 Temp component
= bld
.tmp(elem_rc
);
3289 allocated_vec
[components_split
++] = component
;
3290 split
->definitions
[i
] = Definition(component
);
3292 split
->operands
[0] = Operand(tmp
[0]);
3293 bld
.insert(std::move(split
));
3296 /* try to p_as_uniform early so we can create more optimizable code and
3297 * also update allocated_vec */
3298 for (unsigned j
= start
; j
< components_split
; j
++) {
3299 if (allocated_vec
[j
].bytes() % 4 == 0 && info
->dst
.type() == RegType::sgpr
)
3300 allocated_vec
[j
] = bld
.as_uniform(allocated_vec
[j
]);
3301 has_vgprs
|= allocated_vec
[j
].type() == RegType::vgpr
;
3305 /* concatenate components and p_as_uniform() result if needed */
3306 if (info
->dst
.type() == RegType::vgpr
|| !has_vgprs
)
3307 ctx
->allocated_vec
.emplace(info
->dst
.id(), allocated_vec
);
3309 int padding_bytes
= MAX2((int)info
->dst
.bytes() - int(allocated_vec
[0].bytes() * info
->num_components
), 0);
3311 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(
3312 aco_opcode::p_create_vector
, Format::PSEUDO
, info
->num_components
+ !!padding_bytes
, 1)};
3313 for (unsigned i
= 0; i
< info
->num_components
; i
++)
3314 vec
->operands
[i
] = Operand(allocated_vec
[i
]);
3316 vec
->operands
[info
->num_components
] = Operand(RegClass::get(RegType::vgpr
, padding_bytes
));
3317 if (info
->dst
.type() == RegType::sgpr
&& has_vgprs
) {
3318 Temp tmp
= bld
.tmp(RegType::vgpr
, info
->dst
.size());
3319 vec
->definitions
[0] = Definition(tmp
);
3320 bld
.insert(std::move(vec
));
3321 bld
.pseudo(aco_opcode::p_as_uniform
, Definition(info
->dst
), tmp
);
3323 vec
->definitions
[0] = Definition(info
->dst
);
3324 bld
.insert(std::move(vec
));
3328 Operand
load_lds_size_m0(Builder
& bld
)
3330 /* TODO: m0 does not need to be initialized on GFX9+ */
3331 return bld
.m0((Temp
)bld
.sopk(aco_opcode::s_movk_i32
, bld
.def(s1
, m0
), 0xffff));
3334 Temp
lds_load_callback(Builder
& bld
, const LoadEmitInfo
*info
,
3335 Temp offset
, unsigned bytes_needed
,
3336 unsigned align
, unsigned const_offset
,
3339 offset
= offset
.regClass() == s1
? bld
.copy(bld
.def(v1
), offset
) : offset
;
3341 Operand m
= load_lds_size_m0(bld
);
3343 bool large_ds_read
= bld
.program
->chip_class
>= GFX7
;
3344 bool usable_read2
= bld
.program
->chip_class
>= GFX7
;
3349 //TODO: use ds_read_u8_d16_hi/ds_read_u16_d16_hi if beneficial
3350 if (bytes_needed
>= 16 && align
% 16 == 0 && large_ds_read
) {
3352 op
= aco_opcode::ds_read_b128
;
3353 } else if (bytes_needed
>= 16 && align
% 8 == 0 && const_offset
% 8 == 0 && usable_read2
) {
3356 op
= aco_opcode::ds_read2_b64
;
3357 } else if (bytes_needed
>= 12 && align
% 16 == 0 && large_ds_read
) {
3359 op
= aco_opcode::ds_read_b96
;
3360 } else if (bytes_needed
>= 8 && align
% 8 == 0) {
3362 op
= aco_opcode::ds_read_b64
;
3363 } else if (bytes_needed
>= 8 && align
% 4 == 0 && const_offset
% 4 == 0) {
3366 op
= aco_opcode::ds_read2_b32
;
3367 } else if (bytes_needed
>= 4 && align
% 4 == 0) {
3369 op
= aco_opcode::ds_read_b32
;
3370 } else if (bytes_needed
>= 2 && align
% 2 == 0) {
3372 op
= aco_opcode::ds_read_u16
;
3375 op
= aco_opcode::ds_read_u8
;
3378 unsigned max_offset_plus_one
= read2
? 254 * (size
/ 2u) + 1 : 65536;
3379 if (const_offset
>= max_offset_plus_one
) {
3380 offset
= bld
.vadd32(bld
.def(v1
), offset
, Operand(const_offset
/ max_offset_plus_one
));
3381 const_offset
%= max_offset_plus_one
;
3385 const_offset
/= (size
/ 2u);
3387 RegClass rc
= RegClass(RegType::vgpr
, DIV_ROUND_UP(size
, 4));
3388 Temp val
= rc
== info
->dst
.regClass() && dst_hint
.id() ? dst_hint
: bld
.tmp(rc
);
3390 bld
.ds(op
, Definition(val
), offset
, m
, const_offset
, const_offset
+ 1);
3392 bld
.ds(op
, Definition(val
), offset
, m
, const_offset
);
3395 val
= bld
.pseudo(aco_opcode::p_extract_vector
, bld
.def(RegClass::get(RegType::vgpr
, size
)), val
, Operand(0u));
3400 static auto emit_lds_load
= emit_load
<lds_load_callback
, false, true, UINT32_MAX
>;
3402 Temp
smem_load_callback(Builder
& bld
, const LoadEmitInfo
*info
,
3403 Temp offset
, unsigned bytes_needed
,
3404 unsigned align
, unsigned const_offset
,
3409 if (bytes_needed
<= 4) {
3411 op
= info
->resource
.id() ? aco_opcode::s_buffer_load_dword
: aco_opcode::s_load_dword
;
3412 } else if (bytes_needed
<= 8) {
3414 op
= info
->resource
.id() ? aco_opcode::s_buffer_load_dwordx2
: aco_opcode::s_load_dwordx2
;
3415 } else if (bytes_needed
<= 16) {
3417 op
= info
->resource
.id() ? aco_opcode::s_buffer_load_dwordx4
: aco_opcode::s_load_dwordx4
;
3418 } else if (bytes_needed
<= 32) {
3420 op
= info
->resource
.id() ? aco_opcode::s_buffer_load_dwordx8
: aco_opcode::s_load_dwordx8
;
3423 op
= info
->resource
.id() ? aco_opcode::s_buffer_load_dwordx16
: aco_opcode::s_load_dwordx16
;
3425 aco_ptr
<SMEM_instruction
> load
{create_instruction
<SMEM_instruction
>(op
, Format::SMEM
, 2, 1)};
3426 if (info
->resource
.id()) {
3427 load
->operands
[0] = Operand(info
->resource
);
3428 load
->operands
[1] = Operand(offset
);
3430 load
->operands
[0] = Operand(offset
);
3431 load
->operands
[1] = Operand(0u);
3433 RegClass
rc(RegType::sgpr
, size
);
3434 Temp val
= dst_hint
.id() && dst_hint
.regClass() == rc
? dst_hint
: bld
.tmp(rc
);
3435 load
->definitions
[0] = Definition(val
);
3436 load
->glc
= info
->glc
;
3437 load
->dlc
= info
->glc
&& bld
.program
->chip_class
>= GFX10
;
3438 load
->barrier
= info
->barrier
;
3439 load
->can_reorder
= false; // FIXME: currently, it doesn't seem beneficial due to how our scheduler works
3440 bld
.insert(std::move(load
));
3444 static auto emit_smem_load
= emit_load
<smem_load_callback
, true, false, 1024>;
3446 Temp
mubuf_load_callback(Builder
& bld
, const LoadEmitInfo
*info
,
3447 Temp offset
, unsigned bytes_needed
,
3448 unsigned align_
, unsigned const_offset
,
3451 Operand vaddr
= offset
.type() == RegType::vgpr
? Operand(offset
) : Operand(v1
);
3452 Operand soffset
= offset
.type() == RegType::sgpr
? Operand(offset
) : Operand((uint32_t) 0);
3454 if (info
->soffset
.id()) {
3455 if (soffset
.isTemp())
3456 vaddr
= bld
.copy(bld
.def(v1
), soffset
);
3457 soffset
= Operand(info
->soffset
);
3460 unsigned bytes_size
= 0;
3462 if (bytes_needed
== 1) {
3464 op
= aco_opcode::buffer_load_ubyte
;
3465 } else if (bytes_needed
== 2) {
3467 op
= aco_opcode::buffer_load_ushort
;
3468 } else if (bytes_needed
<= 4) {
3470 op
= aco_opcode::buffer_load_dword
;
3471 } else if (bytes_needed
<= 8) {
3473 op
= aco_opcode::buffer_load_dwordx2
;
3474 } else if (bytes_needed
<= 12 && bld
.program
->chip_class
> GFX6
) {
3476 op
= aco_opcode::buffer_load_dwordx3
;
3479 op
= aco_opcode::buffer_load_dwordx4
;
3481 aco_ptr
<MUBUF_instruction
> mubuf
{create_instruction
<MUBUF_instruction
>(op
, Format::MUBUF
, 3, 1)};
3482 mubuf
->operands
[0] = Operand(info
->resource
);
3483 mubuf
->operands
[1] = vaddr
;
3484 mubuf
->operands
[2] = soffset
;
3485 mubuf
->offen
= (offset
.type() == RegType::vgpr
);
3486 mubuf
->glc
= info
->glc
;
3487 mubuf
->dlc
= info
->glc
&& bld
.program
->chip_class
>= GFX10
;
3488 mubuf
->barrier
= info
->barrier
;
3489 mubuf
->can_reorder
= info
->can_reorder
;
3490 mubuf
->offset
= const_offset
;
3491 RegClass rc
= RegClass::get(RegType::vgpr
, align(bytes_size
, 4));
3492 Temp val
= dst_hint
.id() && rc
== dst_hint
.regClass() ? dst_hint
: bld
.tmp(rc
);
3493 mubuf
->definitions
[0] = Definition(val
);
3494 bld
.insert(std::move(mubuf
));
3499 static auto emit_mubuf_load
= emit_load
<mubuf_load_callback
, true, true, 4096>;
3501 Temp
get_gfx6_global_rsrc(Builder
& bld
, Temp addr
)
3503 uint32_t rsrc_conf
= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT
) |
3504 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32
);
3506 if (addr
.type() == RegType::vgpr
)
3507 return bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s4
), Operand(0u), Operand(0u), Operand(-1u), Operand(rsrc_conf
));
3508 return bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s4
), addr
, Operand(-1u), Operand(rsrc_conf
));
3511 Temp
global_load_callback(Builder
& bld
, const LoadEmitInfo
*info
,
3512 Temp offset
, unsigned bytes_needed
,
3513 unsigned align_
, unsigned const_offset
,
3516 unsigned bytes_size
= 0;
3517 bool mubuf
= bld
.program
->chip_class
== GFX6
;
3518 bool global
= bld
.program
->chip_class
>= GFX9
;
3520 if (bytes_needed
== 1) {
3522 op
= mubuf
? aco_opcode::buffer_load_ubyte
: global
? aco_opcode::global_load_ubyte
: aco_opcode::flat_load_ubyte
;
3523 } else if (bytes_needed
== 2) {
3525 op
= mubuf
? aco_opcode::buffer_load_ushort
: global
? aco_opcode::global_load_ushort
: aco_opcode::flat_load_ushort
;
3526 } else if (bytes_needed
<= 4) {
3528 op
= mubuf
? aco_opcode::buffer_load_dword
: global
? aco_opcode::global_load_dword
: aco_opcode::flat_load_dword
;
3529 } else if (bytes_needed
<= 8) {
3531 op
= mubuf
? aco_opcode::buffer_load_dwordx2
: global
? aco_opcode::global_load_dwordx2
: aco_opcode::flat_load_dwordx2
;
3532 } else if (bytes_needed
<= 12 && !mubuf
) {
3534 op
= global
? aco_opcode::global_load_dwordx3
: aco_opcode::flat_load_dwordx3
;
3537 op
= mubuf
? aco_opcode::buffer_load_dwordx4
: global
? aco_opcode::global_load_dwordx4
: aco_opcode::flat_load_dwordx4
;
3539 RegClass rc
= RegClass::get(RegType::vgpr
, align(bytes_size
, 4));
3540 Temp val
= dst_hint
.id() && rc
== dst_hint
.regClass() ? dst_hint
: bld
.tmp(rc
);
3542 aco_ptr
<MUBUF_instruction
> mubuf
{create_instruction
<MUBUF_instruction
>(op
, Format::MUBUF
, 3, 1)};
3543 mubuf
->operands
[0] = Operand(get_gfx6_global_rsrc(bld
, offset
));
3544 mubuf
->operands
[1] = offset
.type() == RegType::vgpr
? Operand(offset
) : Operand(v1
);
3545 mubuf
->operands
[2] = Operand(0u);
3546 mubuf
->glc
= info
->glc
;
3549 mubuf
->addr64
= offset
.type() == RegType::vgpr
;
3550 mubuf
->disable_wqm
= false;
3551 mubuf
->barrier
= info
->barrier
;
3552 mubuf
->definitions
[0] = Definition(val
);
3553 bld
.insert(std::move(mubuf
));
3555 offset
= offset
.regClass() == s2
? bld
.copy(bld
.def(v2
), offset
) : offset
;
3557 aco_ptr
<FLAT_instruction
> flat
{create_instruction
<FLAT_instruction
>(op
, global
? Format::GLOBAL
: Format::FLAT
, 2, 1)};
3558 flat
->operands
[0] = Operand(offset
);
3559 flat
->operands
[1] = Operand(s1
);
3560 flat
->glc
= info
->glc
;
3561 flat
->dlc
= info
->glc
&& bld
.program
->chip_class
>= GFX10
;
3562 flat
->barrier
= info
->barrier
;
3564 flat
->definitions
[0] = Definition(val
);
3565 bld
.insert(std::move(flat
));
3571 static auto emit_global_load
= emit_load
<global_load_callback
, true, true, 1>;
3573 Temp
load_lds(isel_context
*ctx
, unsigned elem_size_bytes
, Temp dst
,
3574 Temp address
, unsigned base_offset
, unsigned align
)
3576 assert(util_is_power_of_two_nonzero(align
));
3578 Builder
bld(ctx
->program
, ctx
->block
);
3580 unsigned num_components
= dst
.bytes() / elem_size_bytes
;
3581 LoadEmitInfo info
= {Operand(as_vgpr(ctx
, address
)), dst
, num_components
, elem_size_bytes
};
3582 info
.align_mul
= align
;
3583 info
.align_offset
= 0;
3584 info
.barrier
= barrier_shared
;
3585 info
.can_reorder
= false;
3586 info
.const_offset
= base_offset
;
3587 emit_lds_load(ctx
, bld
, &info
);
3592 void split_store_data(isel_context
*ctx
, RegType dst_type
, unsigned count
, Temp
*dst
, unsigned *offsets
, Temp src
)
3597 Builder
bld(ctx
->program
, ctx
->block
);
3599 ASSERTED
bool is_subdword
= false;
3600 for (unsigned i
= 0; i
< count
; i
++)
3601 is_subdword
|= offsets
[i
] % 4;
3602 is_subdword
|= (src
.bytes() - offsets
[count
- 1]) % 4;
3603 assert(!is_subdword
|| dst_type
== RegType::vgpr
);
3605 /* count == 1 fast path */
3607 if (dst_type
== RegType::sgpr
)
3608 dst
[0] = bld
.as_uniform(src
);
3610 dst
[0] = as_vgpr(ctx
, src
);
3614 for (unsigned i
= 0; i
< count
- 1; i
++)
3615 dst
[i
] = bld
.tmp(RegClass::get(dst_type
, offsets
[i
+ 1] - offsets
[i
]));
3616 dst
[count
- 1] = bld
.tmp(RegClass::get(dst_type
, src
.bytes() - offsets
[count
- 1]));
3618 if (is_subdword
&& src
.type() == RegType::sgpr
) {
3619 src
= as_vgpr(ctx
, src
);
3621 /* use allocated_vec if possible */
3622 auto it
= ctx
->allocated_vec
.find(src
.id());
3623 if (it
!= ctx
->allocated_vec
.end()) {
3624 unsigned total_size
= 0;
3625 for (unsigned i
= 0; it
->second
[i
].bytes() && (i
< NIR_MAX_VEC_COMPONENTS
); i
++)
3626 total_size
+= it
->second
[i
].bytes();
3627 if (total_size
!= src
.bytes())
3630 unsigned elem_size
= it
->second
[0].bytes();
3632 for (unsigned i
= 0; i
< count
; i
++) {
3633 if (offsets
[i
] % elem_size
|| dst
[i
].bytes() % elem_size
)
3637 for (unsigned i
= 0; i
< count
; i
++) {
3638 unsigned start_idx
= offsets
[i
] / elem_size
;
3639 unsigned op_count
= dst
[i
].bytes() / elem_size
;
3640 if (op_count
== 1) {
3641 if (dst_type
== RegType::sgpr
)
3642 dst
[i
] = bld
.as_uniform(it
->second
[start_idx
]);
3644 dst
[i
] = as_vgpr(ctx
, it
->second
[start_idx
]);
3648 aco_ptr
<Instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, op_count
, 1)};
3649 for (unsigned j
= 0; j
< op_count
; j
++) {
3650 Temp tmp
= it
->second
[start_idx
+ j
];
3651 if (dst_type
== RegType::sgpr
)
3652 tmp
= bld
.as_uniform(tmp
);
3653 vec
->operands
[j
] = Operand(tmp
);
3655 vec
->definitions
[0] = Definition(dst
[i
]);
3656 bld
.insert(std::move(vec
));
3662 if (dst_type
== RegType::sgpr
)
3663 src
= bld
.as_uniform(src
);
3667 aco_ptr
<Instruction
> split
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_split_vector
, Format::PSEUDO
, 1, count
)};
3668 split
->operands
[0] = Operand(src
);
3669 for (unsigned i
= 0; i
< count
; i
++)
3670 split
->definitions
[i
] = Definition(dst
[i
]);
3671 bld
.insert(std::move(split
));
3674 bool scan_write_mask(uint32_t mask
, uint32_t todo_mask
,
3675 int *start
, int *count
)
3677 unsigned start_elem
= ffs(todo_mask
) - 1;
3678 bool skip
= !(mask
& (1 << start_elem
));
3680 mask
= ~mask
& todo_mask
;
3684 u_bit_scan_consecutive_range(&mask
, start
, count
);
3689 void advance_write_mask(uint32_t *todo_mask
, int start
, int count
)
3691 *todo_mask
&= ~u_bit_consecutive(0, count
) << start
;
3694 void store_lds(isel_context
*ctx
, unsigned elem_size_bytes
, Temp data
, uint32_t wrmask
,
3695 Temp address
, unsigned base_offset
, unsigned align
)
3697 assert(util_is_power_of_two_nonzero(align
));
3698 assert(util_is_power_of_two_nonzero(elem_size_bytes
) && elem_size_bytes
<= 8);
3700 Builder
bld(ctx
->program
, ctx
->block
);
3701 bool large_ds_write
= ctx
->options
->chip_class
>= GFX7
;
3702 bool usable_write2
= ctx
->options
->chip_class
>= GFX7
;
3704 unsigned write_count
= 0;
3705 Temp write_datas
[32];
3706 unsigned offsets
[32];
3707 aco_opcode opcodes
[32];
3709 wrmask
= widen_mask(wrmask
, elem_size_bytes
);
3711 uint32_t todo
= u_bit_consecutive(0, data
.bytes());
3714 if (!scan_write_mask(wrmask
, todo
, &offset
, &bytes
)) {
3715 offsets
[write_count
] = offset
;
3716 opcodes
[write_count
] = aco_opcode::num_opcodes
;
3718 advance_write_mask(&todo
, offset
, bytes
);
3722 bool aligned2
= offset
% 2 == 0 && align
% 2 == 0;
3723 bool aligned4
= offset
% 4 == 0 && align
% 4 == 0;
3724 bool aligned8
= offset
% 8 == 0 && align
% 8 == 0;
3725 bool aligned16
= offset
% 16 == 0 && align
% 16 == 0;
3727 //TODO: use ds_write_b8_d16_hi/ds_write_b16_d16_hi if beneficial
3728 aco_opcode op
= aco_opcode::num_opcodes
;
3729 if (bytes
>= 16 && aligned16
&& large_ds_write
) {
3730 op
= aco_opcode::ds_write_b128
;
3732 } else if (bytes
>= 12 && aligned16
&& large_ds_write
) {
3733 op
= aco_opcode::ds_write_b96
;
3735 } else if (bytes
>= 8 && aligned8
) {
3736 op
= aco_opcode::ds_write_b64
;
3738 } else if (bytes
>= 4 && aligned4
) {
3739 op
= aco_opcode::ds_write_b32
;
3741 } else if (bytes
>= 2 && aligned2
) {
3742 op
= aco_opcode::ds_write_b16
;
3744 } else if (bytes
>= 1) {
3745 op
= aco_opcode::ds_write_b8
;
3751 offsets
[write_count
] = offset
;
3752 opcodes
[write_count
] = op
;
3754 advance_write_mask(&todo
, offset
, bytes
);
3757 Operand m
= load_lds_size_m0(bld
);
3759 split_store_data(ctx
, RegType::vgpr
, write_count
, write_datas
, offsets
, data
);
3761 for (unsigned i
= 0; i
< write_count
; i
++) {
3762 aco_opcode op
= opcodes
[i
];
3763 if (op
== aco_opcode::num_opcodes
)
3766 Temp data
= write_datas
[i
];
3768 unsigned second
= write_count
;
3769 if (usable_write2
&& (op
== aco_opcode::ds_write_b32
|| op
== aco_opcode::ds_write_b64
)) {
3770 for (second
= i
+ 1; second
< write_count
; second
++) {
3771 if (opcodes
[second
] == op
&& (offsets
[second
] - offsets
[i
]) % data
.bytes() == 0) {
3772 op
= data
.bytes() == 4 ? aco_opcode::ds_write2_b32
: aco_opcode::ds_write2_b64
;
3773 opcodes
[second
] = aco_opcode::num_opcodes
;
3779 bool write2
= op
== aco_opcode::ds_write2_b32
|| op
== aco_opcode::ds_write2_b64
;
3780 unsigned write2_off
= (offsets
[second
] - offsets
[i
]) / data
.bytes();
3782 unsigned inline_offset
= base_offset
+ offsets
[i
];
3783 unsigned max_offset
= write2
? (255 - write2_off
) * data
.bytes() : 65535;
3784 Temp address_offset
= address
;
3785 if (inline_offset
> max_offset
) {
3786 address_offset
= bld
.vadd32(bld
.def(v1
), Operand(base_offset
), address_offset
);
3787 inline_offset
= offsets
[i
];
3789 assert(inline_offset
<= max_offset
); /* offsets[i] shouldn't be large enough for this to happen */
3792 Temp second_data
= write_datas
[second
];
3793 inline_offset
/= data
.bytes();
3794 bld
.ds(op
, address_offset
, data
, second_data
, m
, inline_offset
, inline_offset
+ write2_off
);
3796 bld
.ds(op
, address_offset
, data
, m
, inline_offset
);
3801 unsigned calculate_lds_alignment(isel_context
*ctx
, unsigned const_offset
)
3803 unsigned align
= 16;
3805 align
= std::min(align
, 1u << (ffs(const_offset
) - 1));
3811 aco_opcode
get_buffer_store_op(bool smem
, unsigned bytes
)
3816 return aco_opcode::buffer_store_byte
;
3819 return aco_opcode::buffer_store_short
;
3821 return smem
? aco_opcode::s_buffer_store_dword
: aco_opcode::buffer_store_dword
;
3823 return smem
? aco_opcode::s_buffer_store_dwordx2
: aco_opcode::buffer_store_dwordx2
;
3826 return aco_opcode::buffer_store_dwordx3
;
3828 return smem
? aco_opcode::s_buffer_store_dwordx4
: aco_opcode::buffer_store_dwordx4
;
3830 unreachable("Unexpected store size");
3831 return aco_opcode::num_opcodes
;
3834 void split_buffer_store(isel_context
*ctx
, nir_intrinsic_instr
*instr
, bool smem
, RegType dst_type
,
3835 Temp data
, unsigned writemask
, int swizzle_element_size
,
3836 unsigned *write_count
, Temp
*write_datas
, unsigned *offsets
)
3838 unsigned write_count_with_skips
= 0;
3841 /* determine how to split the data */
3842 unsigned todo
= u_bit_consecutive(0, data
.bytes());
3845 skips
[write_count_with_skips
] = !scan_write_mask(writemask
, todo
, &offset
, &bytes
);
3846 offsets
[write_count_with_skips
] = offset
;
3847 if (skips
[write_count_with_skips
]) {
3848 advance_write_mask(&todo
, offset
, bytes
);
3849 write_count_with_skips
++;
3853 /* only supported sizes are 1, 2, 4, 8, 12 and 16 bytes and can't be
3854 * larger than swizzle_element_size */
3855 bytes
= MIN2(bytes
, swizzle_element_size
);
3857 bytes
= bytes
> 4 ? bytes
& ~0x3 : MIN2(bytes
, 2);
3859 /* SMEM and GFX6 VMEM can't emit 12-byte stores */
3860 if ((ctx
->program
->chip_class
== GFX6
|| smem
) && bytes
== 12)
3863 /* dword or larger stores have to be dword-aligned */
3864 unsigned align_mul
= instr
? nir_intrinsic_align_mul(instr
) : 4;
3865 unsigned align_offset
= (instr
? nir_intrinsic_align_offset(instr
) : 0) + offset
;
3866 bool dword_aligned
= align_offset
% 4 == 0 && align_mul
% 4 == 0;
3868 bytes
= MIN2(bytes
, (align_offset
% 2 == 0 && align_mul
% 2 == 0) ? 2 : 1);
3870 advance_write_mask(&todo
, offset
, bytes
);
3871 write_count_with_skips
++;
3874 /* actually split data */
3875 split_store_data(ctx
, dst_type
, write_count_with_skips
, write_datas
, offsets
, data
);
3878 for (unsigned i
= 0; i
< write_count_with_skips
; i
++) {
3881 write_datas
[*write_count
] = write_datas
[i
];
3882 offsets
[*write_count
] = offsets
[i
];
3887 Temp
create_vec_from_array(isel_context
*ctx
, Temp arr
[], unsigned cnt
, RegType reg_type
, unsigned elem_size_bytes
,
3888 unsigned split_cnt
= 0u, Temp dst
= Temp())
3890 Builder
bld(ctx
->program
, ctx
->block
);
3891 unsigned dword_size
= elem_size_bytes
/ 4;
3894 dst
= bld
.tmp(RegClass(reg_type
, cnt
* dword_size
));
3896 std::array
<Temp
, NIR_MAX_VEC_COMPONENTS
> allocated_vec
;
3897 aco_ptr
<Pseudo_instruction
> instr
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, cnt
, 1)};
3898 instr
->definitions
[0] = Definition(dst
);
3900 for (unsigned i
= 0; i
< cnt
; ++i
) {
3902 assert(arr
[i
].size() == dword_size
);
3903 allocated_vec
[i
] = arr
[i
];
3904 instr
->operands
[i
] = Operand(arr
[i
]);
3906 Temp zero
= bld
.copy(bld
.def(RegClass(reg_type
, dword_size
)), Operand(0u, dword_size
== 2));
3907 allocated_vec
[i
] = zero
;
3908 instr
->operands
[i
] = Operand(zero
);
3912 bld
.insert(std::move(instr
));
3915 emit_split_vector(ctx
, dst
, split_cnt
);
3917 ctx
->allocated_vec
.emplace(dst
.id(), allocated_vec
); /* emit_split_vector already does this */
3922 inline unsigned resolve_excess_vmem_const_offset(Builder
&bld
, Temp
&voffset
, unsigned const_offset
)
3924 if (const_offset
>= 4096) {
3925 unsigned excess_const_offset
= const_offset
/ 4096u * 4096u;
3926 const_offset
%= 4096u;
3929 voffset
= bld
.copy(bld
.def(v1
), Operand(excess_const_offset
));
3930 else if (unlikely(voffset
.regClass() == s1
))
3931 voffset
= bld
.sop2(aco_opcode::s_add_u32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(excess_const_offset
), Operand(voffset
));
3932 else if (likely(voffset
.regClass() == v1
))
3933 voffset
= bld
.vadd32(bld
.def(v1
), Operand(voffset
), Operand(excess_const_offset
));
3935 unreachable("Unsupported register class of voffset");
3938 return const_offset
;
3941 void emit_single_mubuf_store(isel_context
*ctx
, Temp descriptor
, Temp voffset
, Temp soffset
, Temp vdata
,
3942 unsigned const_offset
= 0u, bool allow_reorder
= true, bool slc
= false)
3945 assert(vdata
.size() != 3 || ctx
->program
->chip_class
!= GFX6
);
3946 assert(vdata
.size() >= 1 && vdata
.size() <= 4);
3948 Builder
bld(ctx
->program
, ctx
->block
);
3949 aco_opcode op
= get_buffer_store_op(false, vdata
.bytes());
3950 const_offset
= resolve_excess_vmem_const_offset(bld
, voffset
, const_offset
);
3952 Operand voffset_op
= voffset
.id() ? Operand(as_vgpr(ctx
, voffset
)) : Operand(v1
);
3953 Operand soffset_op
= soffset
.id() ? Operand(soffset
) : Operand(0u);
3954 Builder::Result r
= bld
.mubuf(op
, Operand(descriptor
), voffset_op
, soffset_op
, Operand(vdata
), const_offset
,
3955 /* offen */ !voffset_op
.isUndefined(), /* idxen*/ false, /* addr64 */ false,
3956 /* disable_wqm */ false, /* glc */ true, /* dlc*/ false, /* slc */ slc
);
3958 static_cast<MUBUF_instruction
*>(r
.instr
)->can_reorder
= allow_reorder
;
3961 void store_vmem_mubuf(isel_context
*ctx
, Temp src
, Temp descriptor
, Temp voffset
, Temp soffset
,
3962 unsigned base_const_offset
, unsigned elem_size_bytes
, unsigned write_mask
,
3963 bool allow_combining
= true, bool reorder
= true, bool slc
= false)
3965 Builder
bld(ctx
->program
, ctx
->block
);
3966 assert(elem_size_bytes
== 2 || elem_size_bytes
== 4 || elem_size_bytes
== 8);
3968 write_mask
= widen_mask(write_mask
, elem_size_bytes
);
3970 unsigned write_count
= 0;
3971 Temp write_datas
[32];
3972 unsigned offsets
[32];
3973 split_buffer_store(ctx
, NULL
, false, RegType::vgpr
, src
, write_mask
,
3974 allow_combining
? 16 : 4, &write_count
, write_datas
, offsets
);
3976 for (unsigned i
= 0; i
< write_count
; i
++) {
3977 unsigned const_offset
= offsets
[i
] + base_const_offset
;
3978 emit_single_mubuf_store(ctx
, descriptor
, voffset
, soffset
, write_datas
[i
], const_offset
, reorder
, slc
);
3982 void load_vmem_mubuf(isel_context
*ctx
, Temp dst
, Temp descriptor
, Temp voffset
, Temp soffset
,
3983 unsigned base_const_offset
, unsigned elem_size_bytes
, unsigned num_components
,
3984 unsigned stride
= 0u, bool allow_combining
= true, bool allow_reorder
= true)
3986 assert(elem_size_bytes
== 2 || elem_size_bytes
== 4 || elem_size_bytes
== 8);
3987 assert((num_components
* elem_size_bytes
) == dst
.bytes());
3988 assert(!!stride
!= allow_combining
);
3990 Builder
bld(ctx
->program
, ctx
->block
);
3992 LoadEmitInfo info
= {Operand(voffset
), dst
, num_components
, elem_size_bytes
, descriptor
};
3993 info
.component_stride
= allow_combining
? 0 : stride
;
3995 info
.swizzle_component_size
= allow_combining
? 0 : 4;
3996 info
.align_mul
= MIN2(elem_size_bytes
, 4);
3997 info
.align_offset
= 0;
3998 info
.soffset
= soffset
;
3999 info
.const_offset
= base_const_offset
;
4000 emit_mubuf_load(ctx
, bld
, &info
);
4003 std::pair
<Temp
, unsigned> offset_add_from_nir(isel_context
*ctx
, const std::pair
<Temp
, unsigned> &base_offset
, nir_src
*off_src
, unsigned stride
= 1u)
4005 Builder
bld(ctx
->program
, ctx
->block
);
4006 Temp offset
= base_offset
.first
;
4007 unsigned const_offset
= base_offset
.second
;
4009 if (!nir_src_is_const(*off_src
)) {
4010 Temp indirect_offset_arg
= get_ssa_temp(ctx
, off_src
->ssa
);
4013 /* Calculate indirect offset with stride */
4014 if (likely(indirect_offset_arg
.regClass() == v1
))
4015 with_stride
= bld
.v_mul24_imm(bld
.def(v1
), indirect_offset_arg
, stride
);
4016 else if (indirect_offset_arg
.regClass() == s1
)
4017 with_stride
= bld
.sop2(aco_opcode::s_mul_i32
, bld
.def(s1
), Operand(stride
), indirect_offset_arg
);
4019 unreachable("Unsupported register class of indirect offset");
4021 /* Add to the supplied base offset */
4022 if (offset
.id() == 0)
4023 offset
= with_stride
;
4024 else if (unlikely(offset
.regClass() == s1
&& with_stride
.regClass() == s1
))
4025 offset
= bld
.sop2(aco_opcode::s_add_u32
, bld
.def(s1
), bld
.def(s1
, scc
), with_stride
, offset
);
4026 else if (offset
.size() == 1 && with_stride
.size() == 1)
4027 offset
= bld
.vadd32(bld
.def(v1
), with_stride
, offset
);
4029 unreachable("Unsupported register class of indirect offset");
4031 unsigned const_offset_arg
= nir_src_as_uint(*off_src
);
4032 const_offset
+= const_offset_arg
* stride
;
4035 return std::make_pair(offset
, const_offset
);
4038 std::pair
<Temp
, unsigned> offset_add(isel_context
*ctx
, const std::pair
<Temp
, unsigned> &off1
, const std::pair
<Temp
, unsigned> &off2
)
4040 Builder
bld(ctx
->program
, ctx
->block
);
4043 if (off1
.first
.id() && off2
.first
.id()) {
4044 if (unlikely(off1
.first
.regClass() == s1
&& off2
.first
.regClass() == s1
))
4045 offset
= bld
.sop2(aco_opcode::s_add_u32
, bld
.def(s1
), bld
.def(s1
, scc
), off1
.first
, off2
.first
);
4046 else if (off1
.first
.size() == 1 && off2
.first
.size() == 1)
4047 offset
= bld
.vadd32(bld
.def(v1
), off1
.first
, off2
.first
);
4049 unreachable("Unsupported register class of indirect offset");
4051 offset
= off1
.first
.id() ? off1
.first
: off2
.first
;
4054 return std::make_pair(offset
, off1
.second
+ off2
.second
);
4057 std::pair
<Temp
, unsigned> offset_mul(isel_context
*ctx
, const std::pair
<Temp
, unsigned> &offs
, unsigned multiplier
)
4059 Builder
bld(ctx
->program
, ctx
->block
);
4060 unsigned const_offset
= offs
.second
* multiplier
;
4062 if (!offs
.first
.id())
4063 return std::make_pair(offs
.first
, const_offset
);
4065 Temp offset
= unlikely(offs
.first
.regClass() == s1
)
4066 ? bld
.sop2(aco_opcode::s_mul_i32
, bld
.def(s1
), Operand(multiplier
), offs
.first
)
4067 : bld
.v_mul24_imm(bld
.def(v1
), offs
.first
, multiplier
);
4069 return std::make_pair(offset
, const_offset
);
4072 std::pair
<Temp
, unsigned> get_intrinsic_io_basic_offset(isel_context
*ctx
, nir_intrinsic_instr
*instr
, unsigned base_stride
, unsigned component_stride
)
4074 Builder
bld(ctx
->program
, ctx
->block
);
4076 /* base is the driver_location, which is already multiplied by 4, so is in dwords */
4077 unsigned const_offset
= nir_intrinsic_base(instr
) * base_stride
;
4078 /* component is in bytes */
4079 const_offset
+= nir_intrinsic_component(instr
) * component_stride
;
4081 /* offset should be interpreted in relation to the base, so the instruction effectively reads/writes another input/output when it has an offset */
4082 nir_src
*off_src
= nir_get_io_offset_src(instr
);
4083 return offset_add_from_nir(ctx
, std::make_pair(Temp(), const_offset
), off_src
, 4u * base_stride
);
4086 std::pair
<Temp
, unsigned> get_intrinsic_io_basic_offset(isel_context
*ctx
, nir_intrinsic_instr
*instr
, unsigned stride
= 1u)
4088 return get_intrinsic_io_basic_offset(ctx
, instr
, stride
, stride
);
4091 Temp
get_tess_rel_patch_id(isel_context
*ctx
)
4093 Builder
bld(ctx
->program
, ctx
->block
);
4095 switch (ctx
->shader
->info
.stage
) {
4096 case MESA_SHADER_TESS_CTRL
:
4097 return bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(0xffu
),
4098 get_arg(ctx
, ctx
->args
->ac
.tcs_rel_ids
));
4099 case MESA_SHADER_TESS_EVAL
:
4100 return get_arg(ctx
, ctx
->args
->tes_rel_patch_id
);
4102 unreachable("Unsupported stage in get_tess_rel_patch_id");
4106 std::pair
<Temp
, unsigned> get_tcs_per_vertex_input_lds_offset(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
4108 assert(ctx
->shader
->info
.stage
== MESA_SHADER_TESS_CTRL
);
4109 Builder
bld(ctx
->program
, ctx
->block
);
4111 uint32_t tcs_in_patch_stride
= ctx
->args
->options
->key
.tcs
.input_vertices
* ctx
->tcs_num_inputs
* 4;
4112 uint32_t tcs_in_vertex_stride
= ctx
->tcs_num_inputs
* 4;
4114 std::pair
<Temp
, unsigned> offs
= get_intrinsic_io_basic_offset(ctx
, instr
);
4116 nir_src
*vertex_index_src
= nir_get_io_vertex_index_src(instr
);
4117 offs
= offset_add_from_nir(ctx
, offs
, vertex_index_src
, tcs_in_vertex_stride
);
4119 Temp rel_patch_id
= get_tess_rel_patch_id(ctx
);
4120 Temp tcs_in_current_patch_offset
= bld
.v_mul24_imm(bld
.def(v1
), rel_patch_id
, tcs_in_patch_stride
);
4121 offs
= offset_add(ctx
, offs
, std::make_pair(tcs_in_current_patch_offset
, 0));
4123 return offset_mul(ctx
, offs
, 4u);
4126 std::pair
<Temp
, unsigned> get_tcs_output_lds_offset(isel_context
*ctx
, nir_intrinsic_instr
*instr
= nullptr, bool per_vertex
= false)
4128 assert(ctx
->shader
->info
.stage
== MESA_SHADER_TESS_CTRL
);
4129 Builder
bld(ctx
->program
, ctx
->block
);
4131 uint32_t input_patch_size
= ctx
->args
->options
->key
.tcs
.input_vertices
* ctx
->tcs_num_inputs
* 16;
4132 uint32_t output_vertex_size
= ctx
->tcs_num_outputs
* 16;
4133 uint32_t pervertex_output_patch_size
= ctx
->shader
->info
.tess
.tcs_vertices_out
* output_vertex_size
;
4134 uint32_t output_patch_stride
= pervertex_output_patch_size
+ ctx
->tcs_num_patch_outputs
* 16;
4136 std::pair
<Temp
, unsigned> offs
= instr
4137 ? get_intrinsic_io_basic_offset(ctx
, instr
, 4u)
4138 : std::make_pair(Temp(), 0u);
4140 Temp rel_patch_id
= get_tess_rel_patch_id(ctx
);
4141 Temp patch_off
= bld
.v_mul24_imm(bld
.def(v1
), rel_patch_id
, output_patch_stride
);
4146 nir_src
*vertex_index_src
= nir_get_io_vertex_index_src(instr
);
4147 offs
= offset_add_from_nir(ctx
, offs
, vertex_index_src
, output_vertex_size
);
4149 uint32_t output_patch0_offset
= (input_patch_size
* ctx
->tcs_num_patches
);
4150 offs
= offset_add(ctx
, offs
, std::make_pair(patch_off
, output_patch0_offset
));
4152 uint32_t output_patch0_patch_data_offset
= (input_patch_size
* ctx
->tcs_num_patches
+ pervertex_output_patch_size
);
4153 offs
= offset_add(ctx
, offs
, std::make_pair(patch_off
, output_patch0_patch_data_offset
));
4159 std::pair
<Temp
, unsigned> get_tcs_per_vertex_output_vmem_offset(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
4161 Builder
bld(ctx
->program
, ctx
->block
);
4163 unsigned vertices_per_patch
= ctx
->shader
->info
.tess
.tcs_vertices_out
;
4164 unsigned attr_stride
= vertices_per_patch
* ctx
->tcs_num_patches
;
4166 std::pair
<Temp
, unsigned> offs
= get_intrinsic_io_basic_offset(ctx
, instr
, attr_stride
* 4u, 4u);
4168 Temp rel_patch_id
= get_tess_rel_patch_id(ctx
);
4169 Temp patch_off
= bld
.v_mul24_imm(bld
.def(v1
), rel_patch_id
, vertices_per_patch
* 16u);
4170 offs
= offset_add(ctx
, offs
, std::make_pair(patch_off
, 0u));
4172 nir_src
*vertex_index_src
= nir_get_io_vertex_index_src(instr
);
4173 offs
= offset_add_from_nir(ctx
, offs
, vertex_index_src
, 16u);
4178 std::pair
<Temp
, unsigned> get_tcs_per_patch_output_vmem_offset(isel_context
*ctx
, nir_intrinsic_instr
*instr
= nullptr, unsigned const_base_offset
= 0u)
4180 Builder
bld(ctx
->program
, ctx
->block
);
4182 unsigned output_vertex_size
= ctx
->tcs_num_outputs
* 16;
4183 unsigned per_vertex_output_patch_size
= ctx
->shader
->info
.tess
.tcs_vertices_out
* output_vertex_size
;
4184 unsigned per_patch_data_offset
= per_vertex_output_patch_size
* ctx
->tcs_num_patches
;
4185 unsigned attr_stride
= ctx
->tcs_num_patches
;
4187 std::pair
<Temp
, unsigned> offs
= instr
4188 ? get_intrinsic_io_basic_offset(ctx
, instr
, attr_stride
* 4u, 4u)
4189 : std::make_pair(Temp(), 0u);
4191 if (const_base_offset
)
4192 offs
.second
+= const_base_offset
* attr_stride
;
4194 Temp rel_patch_id
= get_tess_rel_patch_id(ctx
);
4195 Temp patch_off
= bld
.v_mul24_imm(bld
.def(v1
), rel_patch_id
, 16u);
4196 offs
= offset_add(ctx
, offs
, std::make_pair(patch_off
, per_patch_data_offset
));
4201 bool tcs_driver_location_matches_api_mask(isel_context
*ctx
, nir_intrinsic_instr
*instr
, bool per_vertex
, uint64_t mask
, bool *indirect
)
4203 assert(per_vertex
|| ctx
->shader
->info
.stage
== MESA_SHADER_TESS_CTRL
);
4208 unsigned drv_loc
= nir_intrinsic_base(instr
);
4209 nir_src
*off_src
= nir_get_io_offset_src(instr
);
4211 if (!nir_src_is_const(*off_src
)) {
4217 uint64_t slot
= per_vertex
4218 ? ctx
->output_drv_loc_to_var_slot
[ctx
->shader
->info
.stage
][drv_loc
/ 4]
4219 : (ctx
->output_tcs_patch_drv_loc_to_var_slot
[drv_loc
/ 4] - VARYING_SLOT_PATCH0
);
4220 return (((uint64_t) 1) << slot
) & mask
;
4223 bool store_output_to_temps(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
4225 unsigned write_mask
= nir_intrinsic_write_mask(instr
);
4226 unsigned component
= nir_intrinsic_component(instr
);
4227 unsigned idx
= nir_intrinsic_base(instr
) + component
;
4229 nir_instr
*off_instr
= instr
->src
[1].ssa
->parent_instr
;
4230 if (off_instr
->type
!= nir_instr_type_load_const
)
4233 Temp src
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
4234 idx
+= nir_src_as_uint(instr
->src
[1]) * 4u;
4236 if (instr
->src
[0].ssa
->bit_size
== 64)
4237 write_mask
= widen_mask(write_mask
, 2);
4239 RegClass rc
= instr
->src
[0].ssa
->bit_size
== 16 ? v2b
: v1
;
4241 for (unsigned i
= 0; i
< 8; ++i
) {
4242 if (write_mask
& (1 << i
)) {
4243 ctx
->outputs
.mask
[idx
/ 4u] |= 1 << (idx
% 4u);
4244 ctx
->outputs
.temps
[idx
] = emit_extract_vector(ctx
, src
, i
, rc
);
4252 bool load_input_from_temps(isel_context
*ctx
, nir_intrinsic_instr
*instr
, Temp dst
)
4254 /* Only TCS per-vertex inputs are supported by this function.
4255 * Per-vertex inputs only match between the VS/TCS invocation id when the number of invocations is the same.
4257 if (ctx
->shader
->info
.stage
!= MESA_SHADER_TESS_CTRL
|| !ctx
->tcs_in_out_eq
)
4260 nir_src
*off_src
= nir_get_io_offset_src(instr
);
4261 nir_src
*vertex_index_src
= nir_get_io_vertex_index_src(instr
);
4262 nir_instr
*vertex_index_instr
= vertex_index_src
->ssa
->parent_instr
;
4263 bool can_use_temps
= nir_src_is_const(*off_src
) &&
4264 vertex_index_instr
->type
== nir_instr_type_intrinsic
&&
4265 nir_instr_as_intrinsic(vertex_index_instr
)->intrinsic
== nir_intrinsic_load_invocation_id
;
4270 unsigned idx
= nir_intrinsic_base(instr
) + nir_intrinsic_component(instr
) + 4 * nir_src_as_uint(*off_src
);
4271 Temp
*src
= &ctx
->inputs
.temps
[idx
];
4272 create_vec_from_array(ctx
, src
, dst
.size(), dst
.regClass().type(), 4u, 0, dst
);
4277 void visit_store_ls_or_es_output(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
4279 Builder
bld(ctx
->program
, ctx
->block
);
4281 if (ctx
->tcs_in_out_eq
&& store_output_to_temps(ctx
, instr
)) {
4282 /* When the TCS only reads this output directly and for the same vertices as its invocation id, it is unnecessary to store the VS output to LDS. */
4283 bool indirect_write
;
4284 bool temp_only_input
= tcs_driver_location_matches_api_mask(ctx
, instr
, true, ctx
->tcs_temp_only_inputs
, &indirect_write
);
4285 if (temp_only_input
&& !indirect_write
)
4289 std::pair
<Temp
, unsigned> offs
= get_intrinsic_io_basic_offset(ctx
, instr
, 4u);
4290 Temp src
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
4291 unsigned write_mask
= nir_intrinsic_write_mask(instr
);
4292 unsigned elem_size_bytes
= instr
->src
[0].ssa
->bit_size
/ 8u;
4294 if (ctx
->stage
== vertex_es
|| ctx
->stage
== tess_eval_es
) {
4295 /* GFX6-8: ES stage is not merged into GS, data is passed from ES to GS in VMEM. */
4296 Temp esgs_ring
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), ctx
->program
->private_segment_buffer
, Operand(RING_ESGS_VS
* 16u));
4297 Temp es2gs_offset
= get_arg(ctx
, ctx
->args
->es2gs_offset
);
4298 store_vmem_mubuf(ctx
, src
, esgs_ring
, offs
.first
, es2gs_offset
, offs
.second
, elem_size_bytes
, write_mask
, false, true, true);
4302 if (ctx
->stage
== vertex_geometry_gs
|| ctx
->stage
== tess_eval_geometry_gs
) {
4303 /* GFX9+: ES stage is merged into GS, data is passed between them using LDS. */
4304 unsigned itemsize
= ctx
->stage
== vertex_geometry_gs
4305 ? ctx
->program
->info
->vs
.es_info
.esgs_itemsize
4306 : ctx
->program
->info
->tes
.es_info
.esgs_itemsize
;
4307 Temp thread_id
= emit_mbcnt(ctx
, bld
.def(v1
));
4308 Temp wave_idx
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
), get_arg(ctx
, ctx
->args
->merged_wave_info
), Operand(4u << 16 | 24));
4309 Temp vertex_idx
= bld
.vop2(aco_opcode::v_or_b32
, bld
.def(v1
), thread_id
,
4310 bld
.v_mul24_imm(bld
.def(v1
), as_vgpr(ctx
, wave_idx
), ctx
->program
->wave_size
));
4311 lds_base
= bld
.v_mul24_imm(bld
.def(v1
), vertex_idx
, itemsize
);
4312 } else if (ctx
->stage
== vertex_ls
|| ctx
->stage
== vertex_tess_control_hs
) {
4313 /* GFX6-8: VS runs on LS stage when tessellation is used, but LS shares LDS space with HS.
4314 * GFX9+: LS is merged into HS, but still uses the same LDS layout.
4316 Temp vertex_idx
= get_arg(ctx
, ctx
->args
->rel_auto_id
);
4317 lds_base
= bld
.v_mul24_imm(bld
.def(v1
), vertex_idx
, ctx
->tcs_num_inputs
* 16u);
4319 unreachable("Invalid LS or ES stage");
4322 offs
= offset_add(ctx
, offs
, std::make_pair(lds_base
, 0u));
4323 unsigned lds_align
= calculate_lds_alignment(ctx
, offs
.second
);
4324 store_lds(ctx
, elem_size_bytes
, src
, write_mask
, offs
.first
, offs
.second
, lds_align
);
4328 bool tcs_output_is_tess_factor(isel_context
*ctx
, nir_intrinsic_instr
*instr
, bool per_vertex
)
4333 unsigned off
= nir_intrinsic_base(instr
) * 4u;
4334 return off
== ctx
->tcs_tess_lvl_out_loc
||
4335 off
== ctx
->tcs_tess_lvl_in_loc
;
4339 bool tcs_output_is_read_by_tes(isel_context
*ctx
, nir_intrinsic_instr
*instr
, bool per_vertex
)
4341 uint64_t mask
= per_vertex
4342 ? ctx
->program
->info
->tcs
.tes_inputs_read
4343 : ctx
->program
->info
->tcs
.tes_patch_inputs_read
;
4345 bool indirect_write
= false;
4346 bool output_read_by_tes
= tcs_driver_location_matches_api_mask(ctx
, instr
, per_vertex
, mask
, &indirect_write
);
4347 return indirect_write
|| output_read_by_tes
;
4350 bool tcs_output_is_read_by_tcs(isel_context
*ctx
, nir_intrinsic_instr
*instr
, bool per_vertex
)
4352 uint64_t mask
= per_vertex
4353 ? ctx
->shader
->info
.outputs_read
4354 : ctx
->shader
->info
.patch_outputs_read
;
4356 bool indirect_write
= false;
4357 bool output_read
= tcs_driver_location_matches_api_mask(ctx
, instr
, per_vertex
, mask
, &indirect_write
);
4358 return indirect_write
|| output_read
;
4361 void visit_store_tcs_output(isel_context
*ctx
, nir_intrinsic_instr
*instr
, bool per_vertex
)
4363 assert(ctx
->stage
== tess_control_hs
|| ctx
->stage
== vertex_tess_control_hs
);
4364 assert(ctx
->shader
->info
.stage
== MESA_SHADER_TESS_CTRL
);
4366 Builder
bld(ctx
->program
, ctx
->block
);
4368 Temp store_val
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
4369 unsigned elem_size_bytes
= instr
->src
[0].ssa
->bit_size
/ 8;
4370 unsigned write_mask
= nir_intrinsic_write_mask(instr
);
4372 bool is_tess_factor
= tcs_output_is_tess_factor(ctx
, instr
, per_vertex
);
4373 bool write_to_vmem
= !is_tess_factor
&& tcs_output_is_read_by_tes(ctx
, instr
, per_vertex
);
4374 bool write_to_lds
= is_tess_factor
|| tcs_output_is_read_by_tcs(ctx
, instr
, per_vertex
);
4376 if (write_to_vmem
) {
4377 std::pair
<Temp
, unsigned> vmem_offs
= per_vertex
4378 ? get_tcs_per_vertex_output_vmem_offset(ctx
, instr
)
4379 : get_tcs_per_patch_output_vmem_offset(ctx
, instr
);
4381 Temp hs_ring_tess_offchip
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), ctx
->program
->private_segment_buffer
, Operand(RING_HS_TESS_OFFCHIP
* 16u));
4382 Temp oc_lds
= get_arg(ctx
, ctx
->args
->oc_lds
);
4383 store_vmem_mubuf(ctx
, store_val
, hs_ring_tess_offchip
, vmem_offs
.first
, oc_lds
, vmem_offs
.second
, elem_size_bytes
, write_mask
, true, false);
4387 std::pair
<Temp
, unsigned> lds_offs
= get_tcs_output_lds_offset(ctx
, instr
, per_vertex
);
4388 unsigned lds_align
= calculate_lds_alignment(ctx
, lds_offs
.second
);
4389 store_lds(ctx
, elem_size_bytes
, store_val
, write_mask
, lds_offs
.first
, lds_offs
.second
, lds_align
);
4393 void visit_load_tcs_output(isel_context
*ctx
, nir_intrinsic_instr
*instr
, bool per_vertex
)
4395 assert(ctx
->stage
== tess_control_hs
|| ctx
->stage
== vertex_tess_control_hs
);
4396 assert(ctx
->shader
->info
.stage
== MESA_SHADER_TESS_CTRL
);
4398 Builder
bld(ctx
->program
, ctx
->block
);
4400 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
4401 std::pair
<Temp
, unsigned> lds_offs
= get_tcs_output_lds_offset(ctx
, instr
, per_vertex
);
4402 unsigned lds_align
= calculate_lds_alignment(ctx
, lds_offs
.second
);
4403 unsigned elem_size_bytes
= instr
->src
[0].ssa
->bit_size
/ 8;
4405 load_lds(ctx
, elem_size_bytes
, dst
, lds_offs
.first
, lds_offs
.second
, lds_align
);
4408 void visit_store_output(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
4410 if (ctx
->stage
== vertex_vs
||
4411 ctx
->stage
== tess_eval_vs
||
4412 ctx
->stage
== fragment_fs
||
4413 ctx
->stage
== ngg_vertex_gs
||
4414 ctx
->stage
== ngg_tess_eval_gs
||
4415 ctx
->shader
->info
.stage
== MESA_SHADER_GEOMETRY
) {
4416 bool stored_to_temps
= store_output_to_temps(ctx
, instr
);
4417 if (!stored_to_temps
) {
4418 fprintf(stderr
, "Unimplemented output offset instruction:\n");
4419 nir_print_instr(instr
->src
[1].ssa
->parent_instr
, stderr
);
4420 fprintf(stderr
, "\n");
4423 } else if (ctx
->stage
== vertex_es
||
4424 ctx
->stage
== vertex_ls
||
4425 ctx
->stage
== tess_eval_es
||
4426 (ctx
->stage
== vertex_tess_control_hs
&& ctx
->shader
->info
.stage
== MESA_SHADER_VERTEX
) ||
4427 (ctx
->stage
== vertex_geometry_gs
&& ctx
->shader
->info
.stage
== MESA_SHADER_VERTEX
) ||
4428 (ctx
->stage
== tess_eval_geometry_gs
&& ctx
->shader
->info
.stage
== MESA_SHADER_TESS_EVAL
)) {
4429 visit_store_ls_or_es_output(ctx
, instr
);
4430 } else if (ctx
->shader
->info
.stage
== MESA_SHADER_TESS_CTRL
) {
4431 visit_store_tcs_output(ctx
, instr
, false);
4433 unreachable("Shader stage not implemented");
4437 void visit_load_output(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
4439 visit_load_tcs_output(ctx
, instr
, false);
4442 void emit_interp_instr(isel_context
*ctx
, unsigned idx
, unsigned component
, Temp src
, Temp dst
, Temp prim_mask
)
4444 Temp coord1
= emit_extract_vector(ctx
, src
, 0, v1
);
4445 Temp coord2
= emit_extract_vector(ctx
, src
, 1, v1
);
4447 Builder
bld(ctx
->program
, ctx
->block
);
4449 if (dst
.regClass() == v2b
) {
4450 if (ctx
->program
->has_16bank_lds
) {
4451 assert(ctx
->options
->chip_class
<= GFX8
);
4452 Builder::Result interp_p1
=
4453 bld
.vintrp(aco_opcode::v_interp_mov_f32
, bld
.def(v1
),
4454 Operand(2u) /* P0 */, bld
.m0(prim_mask
), idx
, component
);
4455 interp_p1
= bld
.vintrp(aco_opcode::v_interp_p1lv_f16
, bld
.def(v2b
),
4456 coord1
, bld
.m0(prim_mask
), interp_p1
, idx
, component
);
4457 bld
.vintrp(aco_opcode::v_interp_p2_legacy_f16
, Definition(dst
), coord2
,
4458 bld
.m0(prim_mask
), interp_p1
, idx
, component
);
4460 aco_opcode interp_p2_op
= aco_opcode::v_interp_p2_f16
;
4462 if (ctx
->options
->chip_class
== GFX8
)
4463 interp_p2_op
= aco_opcode::v_interp_p2_legacy_f16
;
4465 Builder::Result interp_p1
=
4466 bld
.vintrp(aco_opcode::v_interp_p1ll_f16
, bld
.def(v1
),
4467 coord1
, bld
.m0(prim_mask
), idx
, component
);
4468 bld
.vintrp(interp_p2_op
, Definition(dst
), coord2
, bld
.m0(prim_mask
),
4469 interp_p1
, idx
, component
);
4472 Builder::Result interp_p1
=
4473 bld
.vintrp(aco_opcode::v_interp_p1_f32
, bld
.def(v1
), coord1
,
4474 bld
.m0(prim_mask
), idx
, component
);
4476 if (ctx
->program
->has_16bank_lds
)
4477 interp_p1
.instr
->operands
[0].setLateKill(true);
4479 bld
.vintrp(aco_opcode::v_interp_p2_f32
, Definition(dst
), coord2
,
4480 bld
.m0(prim_mask
), interp_p1
, idx
, component
);
4484 void emit_load_frag_coord(isel_context
*ctx
, Temp dst
, unsigned num_components
)
4486 aco_ptr
<Pseudo_instruction
> vec(create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, num_components
, 1));
4487 for (unsigned i
= 0; i
< num_components
; i
++)
4488 vec
->operands
[i
] = Operand(get_arg(ctx
, ctx
->args
->ac
.frag_pos
[i
]));
4489 if (G_0286CC_POS_W_FLOAT_ENA(ctx
->program
->config
->spi_ps_input_ena
)) {
4490 assert(num_components
== 4);
4491 Builder
bld(ctx
->program
, ctx
->block
);
4492 vec
->operands
[3] = bld
.vop1(aco_opcode::v_rcp_f32
, bld
.def(v1
), get_arg(ctx
, ctx
->args
->ac
.frag_pos
[3]));
4495 for (Operand
& op
: vec
->operands
)
4496 op
= op
.isUndefined() ? Operand(0u) : op
;
4498 vec
->definitions
[0] = Definition(dst
);
4499 ctx
->block
->instructions
.emplace_back(std::move(vec
));
4500 emit_split_vector(ctx
, dst
, num_components
);
4504 void visit_load_interpolated_input(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
4506 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
4507 Temp coords
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
4508 unsigned idx
= nir_intrinsic_base(instr
);
4509 unsigned component
= nir_intrinsic_component(instr
);
4510 Temp prim_mask
= get_arg(ctx
, ctx
->args
->ac
.prim_mask
);
4512 nir_const_value
* offset
= nir_src_as_const_value(instr
->src
[1]);
4514 assert(offset
->u32
== 0);
4516 /* the lower 15bit of the prim_mask contain the offset into LDS
4517 * while the upper bits contain the number of prims */
4518 Temp offset_src
= get_ssa_temp(ctx
, instr
->src
[1].ssa
);
4519 assert(offset_src
.regClass() == s1
&& "TODO: divergent offsets...");
4520 Builder
bld(ctx
->program
, ctx
->block
);
4521 Temp stride
= bld
.sop2(aco_opcode::s_lshr_b32
, bld
.def(s1
), bld
.def(s1
, scc
), prim_mask
, Operand(16u));
4522 stride
= bld
.sop1(aco_opcode::s_bcnt1_i32_b32
, bld
.def(s1
), bld
.def(s1
, scc
), stride
);
4523 stride
= bld
.sop2(aco_opcode::s_mul_i32
, bld
.def(s1
), stride
, Operand(48u));
4524 offset_src
= bld
.sop2(aco_opcode::s_mul_i32
, bld
.def(s1
), stride
, offset_src
);
4525 prim_mask
= bld
.sop2(aco_opcode::s_add_i32
, bld
.def(s1
, m0
), bld
.def(s1
, scc
), offset_src
, prim_mask
);
4528 if (instr
->dest
.ssa
.num_components
== 1) {
4529 emit_interp_instr(ctx
, idx
, component
, coords
, dst
, prim_mask
);
4531 aco_ptr
<Pseudo_instruction
> vec(create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, instr
->dest
.ssa
.num_components
, 1));
4532 for (unsigned i
= 0; i
< instr
->dest
.ssa
.num_components
; i
++)
4534 Temp tmp
= {ctx
->program
->allocateId(), v1
};
4535 emit_interp_instr(ctx
, idx
, component
+i
, coords
, tmp
, prim_mask
);
4536 vec
->operands
[i
] = Operand(tmp
);
4538 vec
->definitions
[0] = Definition(dst
);
4539 ctx
->block
->instructions
.emplace_back(std::move(vec
));
4543 bool check_vertex_fetch_size(isel_context
*ctx
, const ac_data_format_info
*vtx_info
,
4544 unsigned offset
, unsigned stride
, unsigned channels
)
4546 unsigned vertex_byte_size
= vtx_info
->chan_byte_size
* channels
;
4547 if (vtx_info
->chan_byte_size
!= 4 && channels
== 3)
4549 return (ctx
->options
->chip_class
!= GFX6
&& ctx
->options
->chip_class
!= GFX10
) ||
4550 (offset
% vertex_byte_size
== 0 && stride
% vertex_byte_size
== 0);
4553 uint8_t get_fetch_data_format(isel_context
*ctx
, const ac_data_format_info
*vtx_info
,
4554 unsigned offset
, unsigned stride
, unsigned *channels
)
4556 if (!vtx_info
->chan_byte_size
) {
4557 *channels
= vtx_info
->num_channels
;
4558 return vtx_info
->chan_format
;
4561 unsigned num_channels
= *channels
;
4562 if (!check_vertex_fetch_size(ctx
, vtx_info
, offset
, stride
, *channels
)) {
4563 unsigned new_channels
= num_channels
+ 1;
4564 /* first, assume more loads is worse and try using a larger data format */
4565 while (new_channels
<= 4 && !check_vertex_fetch_size(ctx
, vtx_info
, offset
, stride
, new_channels
)) {
4567 /* don't make the attribute potentially out-of-bounds */
4568 if (offset
+ new_channels
* vtx_info
->chan_byte_size
> stride
)
4572 if (new_channels
== 5) {
4573 /* then try decreasing load size (at the cost of more loads) */
4574 new_channels
= *channels
;
4575 while (new_channels
> 1 && !check_vertex_fetch_size(ctx
, vtx_info
, offset
, stride
, new_channels
))
4579 if (new_channels
< *channels
)
4580 *channels
= new_channels
;
4581 num_channels
= new_channels
;
4584 switch (vtx_info
->chan_format
) {
4585 case V_008F0C_BUF_DATA_FORMAT_8
:
4586 return (uint8_t[]){V_008F0C_BUF_DATA_FORMAT_8
, V_008F0C_BUF_DATA_FORMAT_8_8
,
4587 V_008F0C_BUF_DATA_FORMAT_INVALID
, V_008F0C_BUF_DATA_FORMAT_8_8_8_8
}[num_channels
- 1];
4588 case V_008F0C_BUF_DATA_FORMAT_16
:
4589 return (uint8_t[]){V_008F0C_BUF_DATA_FORMAT_16
, V_008F0C_BUF_DATA_FORMAT_16_16
,
4590 V_008F0C_BUF_DATA_FORMAT_INVALID
, V_008F0C_BUF_DATA_FORMAT_16_16_16_16
}[num_channels
- 1];
4591 case V_008F0C_BUF_DATA_FORMAT_32
:
4592 return (uint8_t[]){V_008F0C_BUF_DATA_FORMAT_32
, V_008F0C_BUF_DATA_FORMAT_32_32
,
4593 V_008F0C_BUF_DATA_FORMAT_32_32_32
, V_008F0C_BUF_DATA_FORMAT_32_32_32_32
}[num_channels
- 1];
4595 unreachable("shouldn't reach here");
4596 return V_008F0C_BUF_DATA_FORMAT_INVALID
;
4599 /* For 2_10_10_10 formats the alpha is handled as unsigned by pre-vega HW.
4600 * so we may need to fix it up. */
4601 Temp
adjust_vertex_fetch_alpha(isel_context
*ctx
, unsigned adjustment
, Temp alpha
)
4603 Builder
bld(ctx
->program
, ctx
->block
);
4605 if (adjustment
== RADV_ALPHA_ADJUST_SSCALED
)
4606 alpha
= bld
.vop1(aco_opcode::v_cvt_u32_f32
, bld
.def(v1
), alpha
);
4608 /* For the integer-like cases, do a natural sign extension.
4610 * For the SNORM case, the values are 0.0, 0.333, 0.666, 1.0
4611 * and happen to contain 0, 1, 2, 3 as the two LSBs of the
4614 alpha
= bld
.vop2(aco_opcode::v_lshlrev_b32
, bld
.def(v1
), Operand(adjustment
== RADV_ALPHA_ADJUST_SNORM
? 7u : 30u), alpha
);
4615 alpha
= bld
.vop2(aco_opcode::v_ashrrev_i32
, bld
.def(v1
), Operand(30u), alpha
);
4617 /* Convert back to the right type. */
4618 if (adjustment
== RADV_ALPHA_ADJUST_SNORM
) {
4619 alpha
= bld
.vop1(aco_opcode::v_cvt_f32_i32
, bld
.def(v1
), alpha
);
4620 Temp clamp
= bld
.vopc(aco_opcode::v_cmp_le_f32
, bld
.hint_vcc(bld
.def(bld
.lm
)), Operand(0xbf800000u
), alpha
);
4621 alpha
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), Operand(0xbf800000u
), alpha
, clamp
);
4622 } else if (adjustment
== RADV_ALPHA_ADJUST_SSCALED
) {
4623 alpha
= bld
.vop1(aco_opcode::v_cvt_f32_i32
, bld
.def(v1
), alpha
);
4629 void visit_load_input(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
4631 Builder
bld(ctx
->program
, ctx
->block
);
4632 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
4633 if (ctx
->shader
->info
.stage
== MESA_SHADER_VERTEX
) {
4635 nir_instr
*off_instr
= instr
->src
[0].ssa
->parent_instr
;
4636 if (off_instr
->type
!= nir_instr_type_load_const
) {
4637 fprintf(stderr
, "Unimplemented nir_intrinsic_load_input offset\n");
4638 nir_print_instr(off_instr
, stderr
);
4639 fprintf(stderr
, "\n");
4641 uint32_t offset
= nir_instr_as_load_const(off_instr
)->value
[0].u32
;
4643 Temp vertex_buffers
= convert_pointer_to_64_bit(ctx
, get_arg(ctx
, ctx
->args
->vertex_buffers
));
4645 unsigned location
= nir_intrinsic_base(instr
) / 4 - VERT_ATTRIB_GENERIC0
+ offset
;
4646 unsigned component
= nir_intrinsic_component(instr
);
4647 unsigned bitsize
= instr
->dest
.ssa
.bit_size
;
4648 unsigned attrib_binding
= ctx
->options
->key
.vs
.vertex_attribute_bindings
[location
];
4649 uint32_t attrib_offset
= ctx
->options
->key
.vs
.vertex_attribute_offsets
[location
];
4650 uint32_t attrib_stride
= ctx
->options
->key
.vs
.vertex_attribute_strides
[location
];
4651 unsigned attrib_format
= ctx
->options
->key
.vs
.vertex_attribute_formats
[location
];
4653 unsigned dfmt
= attrib_format
& 0xf;
4654 unsigned nfmt
= (attrib_format
>> 4) & 0x7;
4655 const struct ac_data_format_info
*vtx_info
= ac_get_data_format_info(dfmt
);
4657 unsigned mask
= nir_ssa_def_components_read(&instr
->dest
.ssa
) << component
;
4658 unsigned num_channels
= MIN2(util_last_bit(mask
), vtx_info
->num_channels
);
4659 unsigned alpha_adjust
= (ctx
->options
->key
.vs
.alpha_adjust
>> (location
* 2)) & 3;
4660 bool post_shuffle
= ctx
->options
->key
.vs
.post_shuffle
& (1 << location
);
4662 num_channels
= MAX2(num_channels
, 3);
4664 Operand off
= bld
.copy(bld
.def(s1
), Operand(attrib_binding
* 16u));
4665 Temp list
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), vertex_buffers
, off
);
4668 if (ctx
->options
->key
.vs
.instance_rate_inputs
& (1u << location
)) {
4669 uint32_t divisor
= ctx
->options
->key
.vs
.instance_rate_divisors
[location
];
4670 Temp start_instance
= get_arg(ctx
, ctx
->args
->ac
.start_instance
);
4672 Temp instance_id
= get_arg(ctx
, ctx
->args
->ac
.instance_id
);
4674 Temp divided
= bld
.tmp(v1
);
4675 emit_v_div_u32(ctx
, divided
, as_vgpr(ctx
, instance_id
), divisor
);
4676 index
= bld
.vadd32(bld
.def(v1
), start_instance
, divided
);
4678 index
= bld
.vadd32(bld
.def(v1
), start_instance
, instance_id
);
4681 index
= bld
.vop1(aco_opcode::v_mov_b32
, bld
.def(v1
), start_instance
);
4684 index
= bld
.vadd32(bld
.def(v1
),
4685 get_arg(ctx
, ctx
->args
->ac
.base_vertex
),
4686 get_arg(ctx
, ctx
->args
->ac
.vertex_id
));
4689 Temp channels
[num_channels
];
4690 unsigned channel_start
= 0;
4691 bool direct_fetch
= false;
4693 /* skip unused channels at the start */
4694 if (vtx_info
->chan_byte_size
&& !post_shuffle
) {
4695 channel_start
= ffs(mask
) - 1;
4696 for (unsigned i
= 0; i
< channel_start
; i
++)
4697 channels
[i
] = Temp(0, s1
);
4698 } else if (vtx_info
->chan_byte_size
&& post_shuffle
&& !(mask
& 0x8)) {
4699 num_channels
= 3 - (ffs(mask
) - 1);
4703 while (channel_start
< num_channels
) {
4704 unsigned fetch_component
= num_channels
- channel_start
;
4705 unsigned fetch_offset
= attrib_offset
+ channel_start
* vtx_info
->chan_byte_size
;
4706 bool expanded
= false;
4708 /* use MUBUF when possible to avoid possible alignment issues */
4709 /* TODO: we could use SDWA to unpack 8/16-bit attributes without extra instructions */
4710 bool use_mubuf
= (nfmt
== V_008F0C_BUF_NUM_FORMAT_FLOAT
||
4711 nfmt
== V_008F0C_BUF_NUM_FORMAT_UINT
||
4712 nfmt
== V_008F0C_BUF_NUM_FORMAT_SINT
) &&
4713 vtx_info
->chan_byte_size
== 4;
4714 unsigned fetch_dfmt
= V_008F0C_BUF_DATA_FORMAT_INVALID
;
4716 fetch_dfmt
= get_fetch_data_format(ctx
, vtx_info
, fetch_offset
, attrib_stride
, &fetch_component
);
4718 if (fetch_component
== 3 && ctx
->options
->chip_class
== GFX6
) {
4719 /* GFX6 only supports loading vec3 with MTBUF, expand to vec4. */
4720 fetch_component
= 4;
4725 unsigned fetch_bytes
= fetch_component
* bitsize
/ 8;
4727 Temp fetch_index
= index
;
4728 if (attrib_stride
!= 0 && fetch_offset
> attrib_stride
) {
4729 fetch_index
= bld
.vadd32(bld
.def(v1
), Operand(fetch_offset
/ attrib_stride
), fetch_index
);
4730 fetch_offset
= fetch_offset
% attrib_stride
;
4733 Operand
soffset(0u);
4734 if (fetch_offset
>= 4096) {
4735 soffset
= bld
.copy(bld
.def(s1
), Operand(fetch_offset
/ 4096 * 4096));
4736 fetch_offset
%= 4096;
4740 switch (fetch_bytes
) {
4742 assert(!use_mubuf
&& bitsize
== 16);
4743 opcode
= aco_opcode::tbuffer_load_format_d16_x
;
4746 if (bitsize
== 16) {
4748 opcode
= aco_opcode::tbuffer_load_format_d16_xy
;
4750 opcode
= use_mubuf
? aco_opcode::buffer_load_dword
: aco_opcode::tbuffer_load_format_x
;
4754 assert(!use_mubuf
&& bitsize
== 16);
4755 opcode
= aco_opcode::tbuffer_load_format_d16_xyz
;
4758 if (bitsize
== 16) {
4760 opcode
= aco_opcode::tbuffer_load_format_d16_xyzw
;
4762 opcode
= use_mubuf
? aco_opcode::buffer_load_dwordx2
: aco_opcode::tbuffer_load_format_xy
;
4766 assert(ctx
->options
->chip_class
>= GFX7
||
4767 (!use_mubuf
&& ctx
->options
->chip_class
== GFX6
));
4768 opcode
= use_mubuf
? aco_opcode::buffer_load_dwordx3
: aco_opcode::tbuffer_load_format_xyz
;
4771 opcode
= use_mubuf
? aco_opcode::buffer_load_dwordx4
: aco_opcode::tbuffer_load_format_xyzw
;
4774 unreachable("Unimplemented load_input vector size");
4778 if (channel_start
== 0 && fetch_bytes
== dst
.bytes() && !post_shuffle
&&
4779 !expanded
&& (alpha_adjust
== RADV_ALPHA_ADJUST_NONE
||
4780 num_channels
<= 3)) {
4781 direct_fetch
= true;
4784 fetch_dst
= bld
.tmp(RegClass::get(RegType::vgpr
, fetch_bytes
));
4788 Instruction
*mubuf
= bld
.mubuf(opcode
,
4789 Definition(fetch_dst
), list
, fetch_index
, soffset
,
4790 fetch_offset
, false, true).instr
;
4791 static_cast<MUBUF_instruction
*>(mubuf
)->can_reorder
= true;
4793 Instruction
*mtbuf
= bld
.mtbuf(opcode
,
4794 Definition(fetch_dst
), list
, fetch_index
, soffset
,
4795 fetch_dfmt
, nfmt
, fetch_offset
, false, true).instr
;
4796 static_cast<MTBUF_instruction
*>(mtbuf
)->can_reorder
= true;
4799 emit_split_vector(ctx
, fetch_dst
, fetch_dst
.size());
4801 if (fetch_component
== 1) {
4802 channels
[channel_start
] = fetch_dst
;
4804 for (unsigned i
= 0; i
< MIN2(fetch_component
, num_channels
- channel_start
); i
++)
4805 channels
[channel_start
+ i
] = emit_extract_vector(ctx
, fetch_dst
, i
,
4806 bitsize
== 16 ? v2b
: v1
);
4809 channel_start
+= fetch_component
;
4812 if (!direct_fetch
) {
4813 bool is_float
= nfmt
!= V_008F0C_BUF_NUM_FORMAT_UINT
&&
4814 nfmt
!= V_008F0C_BUF_NUM_FORMAT_SINT
;
4816 static const unsigned swizzle_normal
[4] = {0, 1, 2, 3};
4817 static const unsigned swizzle_post_shuffle
[4] = {2, 1, 0, 3};
4818 const unsigned *swizzle
= post_shuffle
? swizzle_post_shuffle
: swizzle_normal
;
4820 aco_ptr
<Instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, dst
.size(), 1)};
4821 std::array
<Temp
,NIR_MAX_VEC_COMPONENTS
> elems
;
4822 unsigned num_temp
= 0;
4823 for (unsigned i
= 0; i
< dst
.size(); i
++) {
4824 unsigned idx
= i
+ component
;
4825 if (swizzle
[idx
] < num_channels
&& channels
[swizzle
[idx
]].id()) {
4826 Temp channel
= channels
[swizzle
[idx
]];
4827 if (idx
== 3 && alpha_adjust
!= RADV_ALPHA_ADJUST_NONE
)
4828 channel
= adjust_vertex_fetch_alpha(ctx
, alpha_adjust
, channel
);
4829 vec
->operands
[i
] = Operand(channel
);
4833 } else if (is_float
&& idx
== 3) {
4834 vec
->operands
[i
] = Operand(0x3f800000u
);
4835 } else if (!is_float
&& idx
== 3) {
4836 vec
->operands
[i
] = Operand(1u);
4838 vec
->operands
[i
] = Operand(0u);
4841 vec
->definitions
[0] = Definition(dst
);
4842 ctx
->block
->instructions
.emplace_back(std::move(vec
));
4843 emit_split_vector(ctx
, dst
, dst
.size());
4845 if (num_temp
== dst
.size())
4846 ctx
->allocated_vec
.emplace(dst
.id(), elems
);
4848 } else if (ctx
->shader
->info
.stage
== MESA_SHADER_FRAGMENT
) {
4849 unsigned offset_idx
= instr
->intrinsic
== nir_intrinsic_load_input
? 0 : 1;
4850 nir_instr
*off_instr
= instr
->src
[offset_idx
].ssa
->parent_instr
;
4851 if (off_instr
->type
!= nir_instr_type_load_const
||
4852 nir_instr_as_load_const(off_instr
)->value
[0].u32
!= 0) {
4853 fprintf(stderr
, "Unimplemented nir_intrinsic_load_input offset\n");
4854 nir_print_instr(off_instr
, stderr
);
4855 fprintf(stderr
, "\n");
4858 Temp prim_mask
= get_arg(ctx
, ctx
->args
->ac
.prim_mask
);
4859 nir_const_value
* offset
= nir_src_as_const_value(instr
->src
[offset_idx
]);
4861 assert(offset
->u32
== 0);
4863 /* the lower 15bit of the prim_mask contain the offset into LDS
4864 * while the upper bits contain the number of prims */
4865 Temp offset_src
= get_ssa_temp(ctx
, instr
->src
[offset_idx
].ssa
);
4866 assert(offset_src
.regClass() == s1
&& "TODO: divergent offsets...");
4867 Builder
bld(ctx
->program
, ctx
->block
);
4868 Temp stride
= bld
.sop2(aco_opcode::s_lshr_b32
, bld
.def(s1
), bld
.def(s1
, scc
), prim_mask
, Operand(16u));
4869 stride
= bld
.sop1(aco_opcode::s_bcnt1_i32_b32
, bld
.def(s1
), bld
.def(s1
, scc
), stride
);
4870 stride
= bld
.sop2(aco_opcode::s_mul_i32
, bld
.def(s1
), stride
, Operand(48u));
4871 offset_src
= bld
.sop2(aco_opcode::s_mul_i32
, bld
.def(s1
), stride
, offset_src
);
4872 prim_mask
= bld
.sop2(aco_opcode::s_add_i32
, bld
.def(s1
, m0
), bld
.def(s1
, scc
), offset_src
, prim_mask
);
4875 unsigned idx
= nir_intrinsic_base(instr
);
4876 unsigned component
= nir_intrinsic_component(instr
);
4877 unsigned vertex_id
= 2; /* P0 */
4879 if (instr
->intrinsic
== nir_intrinsic_load_input_vertex
) {
4880 nir_const_value
* src0
= nir_src_as_const_value(instr
->src
[0]);
4881 switch (src0
->u32
) {
4883 vertex_id
= 2; /* P0 */
4886 vertex_id
= 0; /* P10 */
4889 vertex_id
= 1; /* P20 */
4892 unreachable("invalid vertex index");
4896 if (dst
.size() == 1) {
4897 bld
.vintrp(aco_opcode::v_interp_mov_f32
, Definition(dst
), Operand(vertex_id
), bld
.m0(prim_mask
), idx
, component
);
4899 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, dst
.size(), 1)};
4900 for (unsigned i
= 0; i
< dst
.size(); i
++)
4901 vec
->operands
[i
] = bld
.vintrp(aco_opcode::v_interp_mov_f32
, bld
.def(v1
), Operand(vertex_id
), bld
.m0(prim_mask
), idx
, component
+ i
);
4902 vec
->definitions
[0] = Definition(dst
);
4903 bld
.insert(std::move(vec
));
4906 } else if (ctx
->shader
->info
.stage
== MESA_SHADER_TESS_EVAL
) {
4907 Temp ring
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), ctx
->program
->private_segment_buffer
, Operand(RING_HS_TESS_OFFCHIP
* 16u));
4908 Temp soffset
= get_arg(ctx
, ctx
->args
->oc_lds
);
4909 std::pair
<Temp
, unsigned> offs
= get_tcs_per_patch_output_vmem_offset(ctx
, instr
);
4910 unsigned elem_size_bytes
= instr
->dest
.ssa
.bit_size
/ 8u;
4912 load_vmem_mubuf(ctx
, dst
, ring
, offs
.first
, soffset
, offs
.second
, elem_size_bytes
, instr
->dest
.ssa
.num_components
);
4914 unreachable("Shader stage not implemented");
4918 std::pair
<Temp
, unsigned> get_gs_per_vertex_input_offset(isel_context
*ctx
, nir_intrinsic_instr
*instr
, unsigned base_stride
= 1u)
4920 assert(ctx
->shader
->info
.stage
== MESA_SHADER_GEOMETRY
);
4922 Builder
bld(ctx
->program
, ctx
->block
);
4923 nir_src
*vertex_src
= nir_get_io_vertex_index_src(instr
);
4926 if (!nir_src_is_const(*vertex_src
)) {
4927 /* better code could be created, but this case probably doesn't happen
4928 * much in practice */
4929 Temp indirect_vertex
= as_vgpr(ctx
, get_ssa_temp(ctx
, vertex_src
->ssa
));
4930 for (unsigned i
= 0; i
< ctx
->shader
->info
.gs
.vertices_in
; i
++) {
4933 if (ctx
->stage
== vertex_geometry_gs
|| ctx
->stage
== tess_eval_geometry_gs
) {
4934 elem
= get_arg(ctx
, ctx
->args
->gs_vtx_offset
[i
/ 2u * 2u]);
4936 elem
= bld
.vop2(aco_opcode::v_lshrrev_b32
, bld
.def(v1
), Operand(16u), elem
);
4938 elem
= get_arg(ctx
, ctx
->args
->gs_vtx_offset
[i
]);
4941 if (vertex_offset
.id()) {
4942 Temp cond
= bld
.vopc(aco_opcode::v_cmp_eq_u32
, bld
.hint_vcc(bld
.def(bld
.lm
)),
4943 Operand(i
), indirect_vertex
);
4944 vertex_offset
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), vertex_offset
, elem
, cond
);
4946 vertex_offset
= elem
;
4950 if (ctx
->stage
== vertex_geometry_gs
|| ctx
->stage
== tess_eval_geometry_gs
)
4951 vertex_offset
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(0xffffu
), vertex_offset
);
4953 unsigned vertex
= nir_src_as_uint(*vertex_src
);
4954 if (ctx
->stage
== vertex_geometry_gs
|| ctx
->stage
== tess_eval_geometry_gs
)
4955 vertex_offset
= bld
.vop3(aco_opcode::v_bfe_u32
, bld
.def(v1
),
4956 get_arg(ctx
, ctx
->args
->gs_vtx_offset
[vertex
/ 2u * 2u]),
4957 Operand((vertex
% 2u) * 16u), Operand(16u));
4959 vertex_offset
= get_arg(ctx
, ctx
->args
->gs_vtx_offset
[vertex
]);
4962 std::pair
<Temp
, unsigned> offs
= get_intrinsic_io_basic_offset(ctx
, instr
, base_stride
);
4963 offs
= offset_add(ctx
, offs
, std::make_pair(vertex_offset
, 0u));
4964 return offset_mul(ctx
, offs
, 4u);
4967 void visit_load_gs_per_vertex_input(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
4969 assert(ctx
->shader
->info
.stage
== MESA_SHADER_GEOMETRY
);
4971 Builder
bld(ctx
->program
, ctx
->block
);
4972 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
4973 unsigned elem_size_bytes
= instr
->dest
.ssa
.bit_size
/ 8;
4975 if (ctx
->stage
== geometry_gs
) {
4976 std::pair
<Temp
, unsigned> offs
= get_gs_per_vertex_input_offset(ctx
, instr
, ctx
->program
->wave_size
);
4977 Temp ring
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), ctx
->program
->private_segment_buffer
, Operand(RING_ESGS_GS
* 16u));
4978 load_vmem_mubuf(ctx
, dst
, ring
, offs
.first
, Temp(), offs
.second
, elem_size_bytes
, instr
->dest
.ssa
.num_components
, 4u * ctx
->program
->wave_size
, false, true);
4979 } else if (ctx
->stage
== vertex_geometry_gs
|| ctx
->stage
== tess_eval_geometry_gs
) {
4980 std::pair
<Temp
, unsigned> offs
= get_gs_per_vertex_input_offset(ctx
, instr
);
4981 unsigned lds_align
= calculate_lds_alignment(ctx
, offs
.second
);
4982 load_lds(ctx
, elem_size_bytes
, dst
, offs
.first
, offs
.second
, lds_align
);
4984 unreachable("Unsupported GS stage.");
4988 void visit_load_tcs_per_vertex_input(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
4990 assert(ctx
->shader
->info
.stage
== MESA_SHADER_TESS_CTRL
);
4992 Builder
bld(ctx
->program
, ctx
->block
);
4993 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
4995 if (load_input_from_temps(ctx
, instr
, dst
))
4998 std::pair
<Temp
, unsigned> offs
= get_tcs_per_vertex_input_lds_offset(ctx
, instr
);
4999 unsigned elem_size_bytes
= instr
->dest
.ssa
.bit_size
/ 8;
5000 unsigned lds_align
= calculate_lds_alignment(ctx
, offs
.second
);
5002 load_lds(ctx
, elem_size_bytes
, dst
, offs
.first
, offs
.second
, lds_align
);
5005 void visit_load_tes_per_vertex_input(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
5007 assert(ctx
->shader
->info
.stage
== MESA_SHADER_TESS_EVAL
);
5009 Builder
bld(ctx
->program
, ctx
->block
);
5011 Temp ring
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), ctx
->program
->private_segment_buffer
, Operand(RING_HS_TESS_OFFCHIP
* 16u));
5012 Temp oc_lds
= get_arg(ctx
, ctx
->args
->oc_lds
);
5013 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
5015 unsigned elem_size_bytes
= instr
->dest
.ssa
.bit_size
/ 8;
5016 std::pair
<Temp
, unsigned> offs
= get_tcs_per_vertex_output_vmem_offset(ctx
, instr
);
5018 load_vmem_mubuf(ctx
, dst
, ring
, offs
.first
, oc_lds
, offs
.second
, elem_size_bytes
, instr
->dest
.ssa
.num_components
, 0u, true, true);
5021 void visit_load_per_vertex_input(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
5023 switch (ctx
->shader
->info
.stage
) {
5024 case MESA_SHADER_GEOMETRY
:
5025 visit_load_gs_per_vertex_input(ctx
, instr
);
5027 case MESA_SHADER_TESS_CTRL
:
5028 visit_load_tcs_per_vertex_input(ctx
, instr
);
5030 case MESA_SHADER_TESS_EVAL
:
5031 visit_load_tes_per_vertex_input(ctx
, instr
);
5034 unreachable("Unimplemented shader stage");
5038 void visit_load_per_vertex_output(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
5040 visit_load_tcs_output(ctx
, instr
, true);
5043 void visit_store_per_vertex_output(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
5045 assert(ctx
->stage
== tess_control_hs
|| ctx
->stage
== vertex_tess_control_hs
);
5046 assert(ctx
->shader
->info
.stage
== MESA_SHADER_TESS_CTRL
);
5048 visit_store_tcs_output(ctx
, instr
, true);
5051 void visit_load_tess_coord(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
5053 assert(ctx
->shader
->info
.stage
== MESA_SHADER_TESS_EVAL
);
5055 Builder
bld(ctx
->program
, ctx
->block
);
5056 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
5058 Operand
tes_u(get_arg(ctx
, ctx
->args
->tes_u
));
5059 Operand
tes_v(get_arg(ctx
, ctx
->args
->tes_v
));
5062 if (ctx
->shader
->info
.tess
.primitive_mode
== GL_TRIANGLES
) {
5063 Temp tmp
= bld
.vop2(aco_opcode::v_add_f32
, bld
.def(v1
), tes_u
, tes_v
);
5064 tmp
= bld
.vop2(aco_opcode::v_sub_f32
, bld
.def(v1
), Operand(0x3f800000u
/* 1.0f */), tmp
);
5065 tes_w
= Operand(tmp
);
5068 Temp tess_coord
= bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), tes_u
, tes_v
, tes_w
);
5069 emit_split_vector(ctx
, tess_coord
, 3);
5072 Temp
load_desc_ptr(isel_context
*ctx
, unsigned desc_set
)
5074 if (ctx
->program
->info
->need_indirect_descriptor_sets
) {
5075 Builder
bld(ctx
->program
, ctx
->block
);
5076 Temp ptr64
= convert_pointer_to_64_bit(ctx
, get_arg(ctx
, ctx
->args
->descriptor_sets
[0]));
5077 Operand off
= bld
.copy(bld
.def(s1
), Operand(desc_set
<< 2));
5078 return bld
.smem(aco_opcode::s_load_dword
, bld
.def(s1
), ptr64
, off
);//, false, false, false);
5081 return get_arg(ctx
, ctx
->args
->descriptor_sets
[desc_set
]);
5085 void visit_load_resource(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
5087 Builder
bld(ctx
->program
, ctx
->block
);
5088 Temp index
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
5089 if (!nir_dest_is_divergent(instr
->dest
))
5090 index
= bld
.as_uniform(index
);
5091 unsigned desc_set
= nir_intrinsic_desc_set(instr
);
5092 unsigned binding
= nir_intrinsic_binding(instr
);
5095 radv_pipeline_layout
*pipeline_layout
= ctx
->options
->layout
;
5096 radv_descriptor_set_layout
*layout
= pipeline_layout
->set
[desc_set
].layout
;
5097 unsigned offset
= layout
->binding
[binding
].offset
;
5099 if (layout
->binding
[binding
].type
== VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER_DYNAMIC
||
5100 layout
->binding
[binding
].type
== VK_DESCRIPTOR_TYPE_STORAGE_BUFFER_DYNAMIC
) {
5101 unsigned idx
= pipeline_layout
->set
[desc_set
].dynamic_offset_start
+ layout
->binding
[binding
].dynamic_offset_offset
;
5102 desc_ptr
= get_arg(ctx
, ctx
->args
->ac
.push_constants
);
5103 offset
= pipeline_layout
->push_constant_size
+ 16 * idx
;
5106 desc_ptr
= load_desc_ptr(ctx
, desc_set
);
5107 stride
= layout
->binding
[binding
].size
;
5110 nir_const_value
* nir_const_index
= nir_src_as_const_value(instr
->src
[0]);
5111 unsigned const_index
= nir_const_index
? nir_const_index
->u32
: 0;
5113 if (nir_const_index
) {
5114 const_index
= const_index
* stride
;
5115 } else if (index
.type() == RegType::vgpr
) {
5116 bool index24bit
= layout
->binding
[binding
].array_size
<= 0x1000000;
5117 index
= bld
.v_mul_imm(bld
.def(v1
), index
, stride
, index24bit
);
5119 index
= bld
.sop2(aco_opcode::s_mul_i32
, bld
.def(s1
), Operand(stride
), Operand(index
));
5123 if (nir_const_index
) {
5124 const_index
= const_index
+ offset
;
5125 } else if (index
.type() == RegType::vgpr
) {
5126 index
= bld
.vadd32(bld
.def(v1
), Operand(offset
), index
);
5128 index
= bld
.sop2(aco_opcode::s_add_i32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(offset
), Operand(index
));
5132 if (nir_const_index
&& const_index
== 0) {
5134 } else if (index
.type() == RegType::vgpr
) {
5135 index
= bld
.vadd32(bld
.def(v1
),
5136 nir_const_index
? Operand(const_index
) : Operand(index
),
5139 index
= bld
.sop2(aco_opcode::s_add_i32
, bld
.def(s1
), bld
.def(s1
, scc
),
5140 nir_const_index
? Operand(const_index
) : Operand(index
),
5144 bld
.copy(Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
)), index
);
5147 void load_buffer(isel_context
*ctx
, unsigned num_components
, unsigned component_size
,
5148 Temp dst
, Temp rsrc
, Temp offset
, unsigned align_mul
, unsigned align_offset
,
5149 bool glc
=false, bool readonly
=true, bool allow_smem
=true)
5151 Builder
bld(ctx
->program
, ctx
->block
);
5153 bool use_smem
= dst
.type() != RegType::vgpr
&& (!glc
|| ctx
->options
->chip_class
>= GFX8
) && allow_smem
;
5155 offset
= bld
.as_uniform(offset
);
5157 LoadEmitInfo info
= {Operand(offset
), dst
, num_components
, component_size
, rsrc
};
5159 info
.barrier
= readonly
? barrier_none
: barrier_buffer
;
5160 info
.can_reorder
= readonly
;
5161 info
.align_mul
= align_mul
;
5162 info
.align_offset
= align_offset
;
5164 emit_smem_load(ctx
, bld
, &info
);
5166 emit_mubuf_load(ctx
, bld
, &info
);
5169 void visit_load_ubo(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
5171 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
5172 Temp rsrc
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
5174 Builder
bld(ctx
->program
, ctx
->block
);
5176 nir_intrinsic_instr
* idx_instr
= nir_instr_as_intrinsic(instr
->src
[0].ssa
->parent_instr
);
5177 unsigned desc_set
= nir_intrinsic_desc_set(idx_instr
);
5178 unsigned binding
= nir_intrinsic_binding(idx_instr
);
5179 radv_descriptor_set_layout
*layout
= ctx
->options
->layout
->set
[desc_set
].layout
;
5181 if (layout
->binding
[binding
].type
== VK_DESCRIPTOR_TYPE_INLINE_UNIFORM_BLOCK_EXT
) {
5182 uint32_t desc_type
= S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X
) |
5183 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y
) |
5184 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z
) |
5185 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W
);
5186 if (ctx
->options
->chip_class
>= GFX10
) {
5187 desc_type
|= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_FLOAT
) |
5188 S_008F0C_OOB_SELECT(V_008F0C_OOB_SELECT_RAW
) |
5189 S_008F0C_RESOURCE_LEVEL(1);
5191 desc_type
|= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT
) |
5192 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32
);
5194 Temp upper_dwords
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s3
),
5195 Operand(S_008F04_BASE_ADDRESS_HI(ctx
->options
->address32_hi
)),
5196 Operand(0xFFFFFFFFu
),
5197 Operand(desc_type
));
5198 rsrc
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s4
),
5199 rsrc
, upper_dwords
);
5201 rsrc
= convert_pointer_to_64_bit(ctx
, rsrc
);
5202 rsrc
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), rsrc
, Operand(0u));
5204 unsigned size
= instr
->dest
.ssa
.bit_size
/ 8;
5205 load_buffer(ctx
, instr
->num_components
, size
, dst
, rsrc
, get_ssa_temp(ctx
, instr
->src
[1].ssa
),
5206 nir_intrinsic_align_mul(instr
), nir_intrinsic_align_offset(instr
));
5209 void visit_load_push_constant(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
5211 Builder
bld(ctx
->program
, ctx
->block
);
5212 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
5213 unsigned offset
= nir_intrinsic_base(instr
);
5214 unsigned count
= instr
->dest
.ssa
.num_components
;
5215 nir_const_value
*index_cv
= nir_src_as_const_value(instr
->src
[0]);
5217 if (index_cv
&& instr
->dest
.ssa
.bit_size
== 32) {
5218 unsigned start
= (offset
+ index_cv
->u32
) / 4u;
5219 start
-= ctx
->args
->ac
.base_inline_push_consts
;
5220 if (start
+ count
<= ctx
->args
->ac
.num_inline_push_consts
) {
5221 std::array
<Temp
,NIR_MAX_VEC_COMPONENTS
> elems
;
5222 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, count
, 1)};
5223 for (unsigned i
= 0; i
< count
; ++i
) {
5224 elems
[i
] = get_arg(ctx
, ctx
->args
->ac
.inline_push_consts
[start
+ i
]);
5225 vec
->operands
[i
] = Operand
{elems
[i
]};
5227 vec
->definitions
[0] = Definition(dst
);
5228 ctx
->block
->instructions
.emplace_back(std::move(vec
));
5229 ctx
->allocated_vec
.emplace(dst
.id(), elems
);
5234 Temp index
= bld
.as_uniform(get_ssa_temp(ctx
, instr
->src
[0].ssa
));
5235 if (offset
!= 0) // TODO check if index != 0 as well
5236 index
= bld
.sop2(aco_opcode::s_add_i32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(offset
), index
);
5237 Temp ptr
= convert_pointer_to_64_bit(ctx
, get_arg(ctx
, ctx
->args
->ac
.push_constants
));
5240 bool aligned
= true;
5242 if (instr
->dest
.ssa
.bit_size
== 8) {
5243 aligned
= index_cv
&& (offset
+ index_cv
->u32
) % 4 == 0;
5244 bool fits_in_dword
= count
== 1 || (index_cv
&& ((offset
+ index_cv
->u32
) % 4 + count
) <= 4);
5246 vec
= fits_in_dword
? bld
.tmp(s1
) : bld
.tmp(s2
);
5247 } else if (instr
->dest
.ssa
.bit_size
== 16) {
5248 aligned
= index_cv
&& (offset
+ index_cv
->u32
) % 4 == 0;
5250 vec
= count
== 4 ? bld
.tmp(s4
) : count
> 1 ? bld
.tmp(s2
) : bld
.tmp(s1
);
5255 switch (vec
.size()) {
5257 op
= aco_opcode::s_load_dword
;
5260 op
= aco_opcode::s_load_dwordx2
;
5266 op
= aco_opcode::s_load_dwordx4
;
5272 op
= aco_opcode::s_load_dwordx8
;
5275 unreachable("unimplemented or forbidden load_push_constant.");
5278 bld
.smem(op
, Definition(vec
), ptr
, index
);
5281 Operand byte_offset
= index_cv
? Operand((offset
+ index_cv
->u32
) % 4) : Operand(index
);
5282 byte_align_scalar(ctx
, vec
, byte_offset
, dst
);
5287 emit_split_vector(ctx
, vec
, 4);
5288 RegClass rc
= dst
.size() == 3 ? s1
: s2
;
5289 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
),
5290 emit_extract_vector(ctx
, vec
, 0, rc
),
5291 emit_extract_vector(ctx
, vec
, 1, rc
),
5292 emit_extract_vector(ctx
, vec
, 2, rc
));
5295 emit_split_vector(ctx
, dst
, instr
->dest
.ssa
.num_components
);
5298 void visit_load_constant(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
5300 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
5302 Builder
bld(ctx
->program
, ctx
->block
);
5304 uint32_t desc_type
= S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X
) |
5305 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y
) |
5306 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z
) |
5307 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W
);
5308 if (ctx
->options
->chip_class
>= GFX10
) {
5309 desc_type
|= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_FLOAT
) |
5310 S_008F0C_OOB_SELECT(V_008F0C_OOB_SELECT_RAW
) |
5311 S_008F0C_RESOURCE_LEVEL(1);
5313 desc_type
|= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT
) |
5314 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32
);
5317 unsigned base
= nir_intrinsic_base(instr
);
5318 unsigned range
= nir_intrinsic_range(instr
);
5320 Temp offset
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
5321 if (base
&& offset
.type() == RegType::sgpr
)
5322 offset
= bld
.sop2(aco_opcode::s_add_u32
, bld
.def(s1
), bld
.def(s1
, scc
), offset
, Operand(base
));
5323 else if (base
&& offset
.type() == RegType::vgpr
)
5324 offset
= bld
.vadd32(bld
.def(v1
), Operand(base
), offset
);
5326 Temp rsrc
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s4
),
5327 bld
.sop1(aco_opcode::p_constaddr
, bld
.def(s2
), bld
.def(s1
, scc
), Operand(ctx
->constant_data_offset
)),
5328 Operand(MIN2(base
+ range
, ctx
->shader
->constant_data_size
)),
5329 Operand(desc_type
));
5330 unsigned size
= instr
->dest
.ssa
.bit_size
/ 8;
5331 // TODO: get alignment information for subdword constants
5332 load_buffer(ctx
, instr
->num_components
, size
, dst
, rsrc
, offset
, size
, 0);
5335 void visit_discard_if(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
5337 if (ctx
->cf_info
.loop_nest_depth
|| ctx
->cf_info
.parent_if
.is_divergent
)
5338 ctx
->cf_info
.exec_potentially_empty_discard
= true;
5340 ctx
->program
->needs_exact
= true;
5342 // TODO: optimize uniform conditions
5343 Builder
bld(ctx
->program
, ctx
->block
);
5344 Temp src
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
5345 assert(src
.regClass() == bld
.lm
);
5346 src
= bld
.sop2(Builder::s_and
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), src
, Operand(exec
, bld
.lm
));
5347 bld
.pseudo(aco_opcode::p_discard_if
, src
);
5348 ctx
->block
->kind
|= block_kind_uses_discard_if
;
5352 void visit_discard(isel_context
* ctx
, nir_intrinsic_instr
*instr
)
5354 Builder
bld(ctx
->program
, ctx
->block
);
5356 if (ctx
->cf_info
.loop_nest_depth
|| ctx
->cf_info
.parent_if
.is_divergent
)
5357 ctx
->cf_info
.exec_potentially_empty_discard
= true;
5359 bool divergent
= ctx
->cf_info
.parent_if
.is_divergent
||
5360 ctx
->cf_info
.parent_loop
.has_divergent_continue
;
5362 if (ctx
->block
->loop_nest_depth
&&
5363 ((nir_instr_is_last(&instr
->instr
) && !divergent
) || divergent
)) {
5364 /* we handle discards the same way as jump instructions */
5365 append_logical_end(ctx
->block
);
5367 /* in loops, discard behaves like break */
5368 Block
*linear_target
= ctx
->cf_info
.parent_loop
.exit
;
5369 ctx
->block
->kind
|= block_kind_discard
;
5372 /* uniform discard - loop ends here */
5373 assert(nir_instr_is_last(&instr
->instr
));
5374 ctx
->block
->kind
|= block_kind_uniform
;
5375 ctx
->cf_info
.has_branch
= true;
5376 bld
.branch(aco_opcode::p_branch
);
5377 add_linear_edge(ctx
->block
->index
, linear_target
);
5381 /* we add a break right behind the discard() instructions */
5382 ctx
->block
->kind
|= block_kind_break
;
5383 unsigned idx
= ctx
->block
->index
;
5385 ctx
->cf_info
.parent_loop
.has_divergent_branch
= true;
5386 ctx
->cf_info
.nir_to_aco
[instr
->instr
.block
->index
] = idx
;
5388 /* remove critical edges from linear CFG */
5389 bld
.branch(aco_opcode::p_branch
);
5390 Block
* break_block
= ctx
->program
->create_and_insert_block();
5391 break_block
->loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
5392 break_block
->kind
|= block_kind_uniform
;
5393 add_linear_edge(idx
, break_block
);
5394 add_linear_edge(break_block
->index
, linear_target
);
5395 bld
.reset(break_block
);
5396 bld
.branch(aco_opcode::p_branch
);
5398 Block
* continue_block
= ctx
->program
->create_and_insert_block();
5399 continue_block
->loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
5400 add_linear_edge(idx
, continue_block
);
5401 append_logical_start(continue_block
);
5402 ctx
->block
= continue_block
;
5407 /* it can currently happen that NIR doesn't remove the unreachable code */
5408 if (!nir_instr_is_last(&instr
->instr
)) {
5409 ctx
->program
->needs_exact
= true;
5410 /* save exec somewhere temporarily so that it doesn't get
5411 * overwritten before the discard from outer exec masks */
5412 Temp cond
= bld
.sop2(Builder::s_and
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), Operand(0xFFFFFFFF), Operand(exec
, bld
.lm
));
5413 bld
.pseudo(aco_opcode::p_discard_if
, cond
);
5414 ctx
->block
->kind
|= block_kind_uses_discard_if
;
5418 /* This condition is incorrect for uniformly branched discards in a loop
5419 * predicated by a divergent condition, but the above code catches that case
5420 * and the discard would end up turning into a discard_if.
5430 if (!ctx
->cf_info
.parent_if
.is_divergent
) {
5431 /* program just ends here */
5432 ctx
->block
->kind
|= block_kind_uniform
;
5433 bld
.exp(aco_opcode::exp
, Operand(v1
), Operand(v1
), Operand(v1
), Operand(v1
),
5434 0 /* enabled mask */, 9 /* dest */,
5435 false /* compressed */, true/* done */, true /* valid mask */);
5436 bld
.sopp(aco_opcode::s_endpgm
);
5437 // TODO: it will potentially be followed by a branch which is dead code to sanitize NIR phis
5439 ctx
->block
->kind
|= block_kind_discard
;
5440 /* branch and linear edge is added by visit_if() */
5444 enum aco_descriptor_type
{
5455 should_declare_array(isel_context
*ctx
, enum glsl_sampler_dim sampler_dim
, bool is_array
) {
5456 if (sampler_dim
== GLSL_SAMPLER_DIM_BUF
)
5458 ac_image_dim dim
= ac_get_sampler_dim(ctx
->options
->chip_class
, sampler_dim
, is_array
);
5459 return dim
== ac_image_cube
||
5460 dim
== ac_image_1darray
||
5461 dim
== ac_image_2darray
||
5462 dim
== ac_image_2darraymsaa
;
5465 Temp
get_sampler_desc(isel_context
*ctx
, nir_deref_instr
*deref_instr
,
5466 enum aco_descriptor_type desc_type
,
5467 const nir_tex_instr
*tex_instr
, bool image
, bool write
)
5469 /* FIXME: we should lower the deref with some new nir_intrinsic_load_desc
5470 std::unordered_map<uint64_t, Temp>::iterator it = ctx->tex_desc.find((uint64_t) desc_type << 32 | deref_instr->dest.ssa.index);
5471 if (it != ctx->tex_desc.end())
5474 Temp index
= Temp();
5475 bool index_set
= false;
5476 unsigned constant_index
= 0;
5477 unsigned descriptor_set
;
5478 unsigned base_index
;
5479 Builder
bld(ctx
->program
, ctx
->block
);
5482 assert(tex_instr
&& !image
);
5484 base_index
= tex_instr
->sampler_index
;
5486 while(deref_instr
->deref_type
!= nir_deref_type_var
) {
5487 unsigned array_size
= glsl_get_aoa_size(deref_instr
->type
);
5491 assert(deref_instr
->deref_type
== nir_deref_type_array
);
5492 nir_const_value
*const_value
= nir_src_as_const_value(deref_instr
->arr
.index
);
5494 constant_index
+= array_size
* const_value
->u32
;
5496 Temp indirect
= get_ssa_temp(ctx
, deref_instr
->arr
.index
.ssa
);
5497 if (indirect
.type() == RegType::vgpr
)
5498 indirect
= bld
.vop1(aco_opcode::v_readfirstlane_b32
, bld
.def(s1
), indirect
);
5500 if (array_size
!= 1)
5501 indirect
= bld
.sop2(aco_opcode::s_mul_i32
, bld
.def(s1
), Operand(array_size
), indirect
);
5507 index
= bld
.sop2(aco_opcode::s_add_i32
, bld
.def(s1
), bld
.def(s1
, scc
), index
, indirect
);
5511 deref_instr
= nir_src_as_deref(deref_instr
->parent
);
5513 descriptor_set
= deref_instr
->var
->data
.descriptor_set
;
5514 base_index
= deref_instr
->var
->data
.binding
;
5517 Temp list
= load_desc_ptr(ctx
, descriptor_set
);
5518 list
= convert_pointer_to_64_bit(ctx
, list
);
5520 struct radv_descriptor_set_layout
*layout
= ctx
->options
->layout
->set
[descriptor_set
].layout
;
5521 struct radv_descriptor_set_binding_layout
*binding
= layout
->binding
+ base_index
;
5522 unsigned offset
= binding
->offset
;
5523 unsigned stride
= binding
->size
;
5527 assert(base_index
< layout
->binding_count
);
5529 switch (desc_type
) {
5530 case ACO_DESC_IMAGE
:
5532 opcode
= aco_opcode::s_load_dwordx8
;
5534 case ACO_DESC_FMASK
:
5536 opcode
= aco_opcode::s_load_dwordx8
;
5539 case ACO_DESC_SAMPLER
:
5541 opcode
= aco_opcode::s_load_dwordx4
;
5542 if (binding
->type
== VK_DESCRIPTOR_TYPE_COMBINED_IMAGE_SAMPLER
)
5543 offset
+= radv_combined_image_descriptor_sampler_offset(binding
);
5545 case ACO_DESC_BUFFER
:
5547 opcode
= aco_opcode::s_load_dwordx4
;
5549 case ACO_DESC_PLANE_0
:
5550 case ACO_DESC_PLANE_1
:
5552 opcode
= aco_opcode::s_load_dwordx8
;
5553 offset
+= 32 * (desc_type
- ACO_DESC_PLANE_0
);
5555 case ACO_DESC_PLANE_2
:
5557 opcode
= aco_opcode::s_load_dwordx4
;
5561 unreachable("invalid desc_type\n");
5564 offset
+= constant_index
* stride
;
5566 if (desc_type
== ACO_DESC_SAMPLER
&& binding
->immutable_samplers_offset
&&
5567 (!index_set
|| binding
->immutable_samplers_equal
)) {
5568 if (binding
->immutable_samplers_equal
)
5571 const uint32_t *samplers
= radv_immutable_samplers(layout
, binding
);
5572 return bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s4
),
5573 Operand(samplers
[constant_index
* 4 + 0]),
5574 Operand(samplers
[constant_index
* 4 + 1]),
5575 Operand(samplers
[constant_index
* 4 + 2]),
5576 Operand(samplers
[constant_index
* 4 + 3]));
5581 off
= bld
.copy(bld
.def(s1
), Operand(offset
));
5583 off
= Operand((Temp
)bld
.sop2(aco_opcode::s_add_i32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(offset
),
5584 bld
.sop2(aco_opcode::s_mul_i32
, bld
.def(s1
), Operand(stride
), index
)));
5587 Temp res
= bld
.smem(opcode
, bld
.def(type
), list
, off
);
5589 if (desc_type
== ACO_DESC_PLANE_2
) {
5591 for (unsigned i
= 0; i
< 8; i
++)
5592 components
[i
] = bld
.tmp(s1
);
5593 bld
.pseudo(aco_opcode::p_split_vector
,
5594 Definition(components
[0]),
5595 Definition(components
[1]),
5596 Definition(components
[2]),
5597 Definition(components
[3]),
5600 Temp desc2
= get_sampler_desc(ctx
, deref_instr
, ACO_DESC_PLANE_1
, tex_instr
, image
, write
);
5601 bld
.pseudo(aco_opcode::p_split_vector
,
5602 bld
.def(s1
), bld
.def(s1
), bld
.def(s1
), bld
.def(s1
),
5603 Definition(components
[4]),
5604 Definition(components
[5]),
5605 Definition(components
[6]),
5606 Definition(components
[7]),
5609 res
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s8
),
5610 components
[0], components
[1], components
[2], components
[3],
5611 components
[4], components
[5], components
[6], components
[7]);
5617 static int image_type_to_components_count(enum glsl_sampler_dim dim
, bool array
)
5620 case GLSL_SAMPLER_DIM_BUF
:
5622 case GLSL_SAMPLER_DIM_1D
:
5623 return array
? 2 : 1;
5624 case GLSL_SAMPLER_DIM_2D
:
5625 return array
? 3 : 2;
5626 case GLSL_SAMPLER_DIM_MS
:
5627 return array
? 4 : 3;
5628 case GLSL_SAMPLER_DIM_3D
:
5629 case GLSL_SAMPLER_DIM_CUBE
:
5631 case GLSL_SAMPLER_DIM_RECT
:
5632 case GLSL_SAMPLER_DIM_SUBPASS
:
5634 case GLSL_SAMPLER_DIM_SUBPASS_MS
:
5643 /* Adjust the sample index according to FMASK.
5645 * For uncompressed MSAA surfaces, FMASK should return 0x76543210,
5646 * which is the identity mapping. Each nibble says which physical sample
5647 * should be fetched to get that sample.
5649 * For example, 0x11111100 means there are only 2 samples stored and
5650 * the second sample covers 3/4 of the pixel. When reading samples 0
5651 * and 1, return physical sample 0 (determined by the first two 0s
5652 * in FMASK), otherwise return physical sample 1.
5654 * The sample index should be adjusted as follows:
5655 * sample_index = (fmask >> (sample_index * 4)) & 0xF;
5657 static Temp
adjust_sample_index_using_fmask(isel_context
*ctx
, bool da
, std::vector
<Temp
>& coords
, Operand sample_index
, Temp fmask_desc_ptr
)
5659 Builder
bld(ctx
->program
, ctx
->block
);
5660 Temp fmask
= bld
.tmp(v1
);
5661 unsigned dim
= ctx
->options
->chip_class
>= GFX10
5662 ? ac_get_sampler_dim(ctx
->options
->chip_class
, GLSL_SAMPLER_DIM_2D
, da
)
5665 Temp coord
= da
? bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v3
), coords
[0], coords
[1], coords
[2]) :
5666 bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), coords
[0], coords
[1]);
5667 aco_ptr
<MIMG_instruction
> load
{create_instruction
<MIMG_instruction
>(aco_opcode::image_load
, Format::MIMG
, 3, 1)};
5668 load
->operands
[0] = Operand(fmask_desc_ptr
);
5669 load
->operands
[1] = Operand(s4
); /* no sampler */
5670 load
->operands
[2] = Operand(coord
);
5671 load
->definitions
[0] = Definition(fmask
);
5678 load
->can_reorder
= true; /* fmask images shouldn't be modified */
5679 ctx
->block
->instructions
.emplace_back(std::move(load
));
5681 Operand sample_index4
;
5682 if (sample_index
.isConstant()) {
5683 if (sample_index
.constantValue() < 16) {
5684 sample_index4
= Operand(sample_index
.constantValue() << 2);
5686 sample_index4
= Operand(0u);
5688 } else if (sample_index
.regClass() == s1
) {
5689 sample_index4
= bld
.sop2(aco_opcode::s_lshl_b32
, bld
.def(s1
), bld
.def(s1
, scc
), sample_index
, Operand(2u));
5691 assert(sample_index
.regClass() == v1
);
5692 sample_index4
= bld
.vop2(aco_opcode::v_lshlrev_b32
, bld
.def(v1
), Operand(2u), sample_index
);
5696 if (sample_index4
.isConstant() && sample_index4
.constantValue() == 0)
5697 final_sample
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(15u), fmask
);
5698 else if (sample_index4
.isConstant() && sample_index4
.constantValue() == 28)
5699 final_sample
= bld
.vop2(aco_opcode::v_lshrrev_b32
, bld
.def(v1
), Operand(28u), fmask
);
5701 final_sample
= bld
.vop3(aco_opcode::v_bfe_u32
, bld
.def(v1
), fmask
, sample_index4
, Operand(4u));
5703 /* Don't rewrite the sample index if WORD1.DATA_FORMAT of the FMASK
5704 * resource descriptor is 0 (invalid),
5706 Temp compare
= bld
.tmp(bld
.lm
);
5707 bld
.vopc_e64(aco_opcode::v_cmp_lg_u32
, Definition(compare
),
5708 Operand(0u), emit_extract_vector(ctx
, fmask_desc_ptr
, 1, s1
)).def(0).setHint(vcc
);
5710 Temp sample_index_v
= bld
.vop1(aco_opcode::v_mov_b32
, bld
.def(v1
), sample_index
);
5712 /* Replace the MSAA sample index. */
5713 return bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), sample_index_v
, final_sample
, compare
);
5716 static Temp
get_image_coords(isel_context
*ctx
, const nir_intrinsic_instr
*instr
, const struct glsl_type
*type
)
5719 Temp src0
= get_ssa_temp(ctx
, instr
->src
[1].ssa
);
5720 enum glsl_sampler_dim dim
= glsl_get_sampler_dim(type
);
5721 bool is_array
= glsl_sampler_type_is_array(type
);
5722 ASSERTED
bool add_frag_pos
= (dim
== GLSL_SAMPLER_DIM_SUBPASS
|| dim
== GLSL_SAMPLER_DIM_SUBPASS_MS
);
5723 assert(!add_frag_pos
&& "Input attachments should be lowered.");
5724 bool is_ms
= (dim
== GLSL_SAMPLER_DIM_MS
|| dim
== GLSL_SAMPLER_DIM_SUBPASS_MS
);
5725 bool gfx9_1d
= ctx
->options
->chip_class
== GFX9
&& dim
== GLSL_SAMPLER_DIM_1D
;
5726 int count
= image_type_to_components_count(dim
, is_array
);
5727 std::vector
<Temp
> coords(count
);
5728 Builder
bld(ctx
->program
, ctx
->block
);
5732 Temp src2
= get_ssa_temp(ctx
, instr
->src
[2].ssa
);
5733 /* get sample index */
5734 if (instr
->intrinsic
== nir_intrinsic_image_deref_load
) {
5735 nir_const_value
*sample_cv
= nir_src_as_const_value(instr
->src
[2]);
5736 Operand sample_index
= sample_cv
? Operand(sample_cv
->u32
) : Operand(emit_extract_vector(ctx
, src2
, 0, v1
));
5737 std::vector
<Temp
> fmask_load_address
;
5738 for (unsigned i
= 0; i
< (is_array
? 3 : 2); i
++)
5739 fmask_load_address
.emplace_back(emit_extract_vector(ctx
, src0
, i
, v1
));
5741 Temp fmask_desc_ptr
= get_sampler_desc(ctx
, nir_instr_as_deref(instr
->src
[0].ssa
->parent_instr
), ACO_DESC_FMASK
, nullptr, false, false);
5742 coords
[count
] = adjust_sample_index_using_fmask(ctx
, is_array
, fmask_load_address
, sample_index
, fmask_desc_ptr
);
5744 coords
[count
] = emit_extract_vector(ctx
, src2
, 0, v1
);
5749 coords
[0] = emit_extract_vector(ctx
, src0
, 0, v1
);
5750 coords
.resize(coords
.size() + 1);
5751 coords
[1] = bld
.copy(bld
.def(v1
), Operand(0u));
5753 coords
[2] = emit_extract_vector(ctx
, src0
, 1, v1
);
5755 for (int i
= 0; i
< count
; i
++)
5756 coords
[i
] = emit_extract_vector(ctx
, src0
, i
, v1
);
5759 if (instr
->intrinsic
== nir_intrinsic_image_deref_load
||
5760 instr
->intrinsic
== nir_intrinsic_image_deref_store
) {
5761 int lod_index
= instr
->intrinsic
== nir_intrinsic_image_deref_load
? 3 : 4;
5762 bool level_zero
= nir_src_is_const(instr
->src
[lod_index
]) && nir_src_as_uint(instr
->src
[lod_index
]) == 0;
5765 coords
.emplace_back(get_ssa_temp(ctx
, instr
->src
[lod_index
].ssa
));
5768 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, coords
.size(), 1)};
5769 for (unsigned i
= 0; i
< coords
.size(); i
++)
5770 vec
->operands
[i
] = Operand(coords
[i
]);
5771 Temp res
= {ctx
->program
->allocateId(), RegClass(RegType::vgpr
, coords
.size())};
5772 vec
->definitions
[0] = Definition(res
);
5773 ctx
->block
->instructions
.emplace_back(std::move(vec
));
5778 void visit_image_load(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
5780 Builder
bld(ctx
->program
, ctx
->block
);
5781 const nir_variable
*var
= nir_deref_instr_get_variable(nir_instr_as_deref(instr
->src
[0].ssa
->parent_instr
));
5782 const struct glsl_type
*type
= glsl_without_array(var
->type
);
5783 const enum glsl_sampler_dim dim
= glsl_get_sampler_dim(type
);
5784 bool is_array
= glsl_sampler_type_is_array(type
);
5785 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
5787 if (dim
== GLSL_SAMPLER_DIM_BUF
) {
5788 unsigned mask
= nir_ssa_def_components_read(&instr
->dest
.ssa
);
5789 unsigned num_channels
= util_last_bit(mask
);
5790 Temp rsrc
= get_sampler_desc(ctx
, nir_instr_as_deref(instr
->src
[0].ssa
->parent_instr
), ACO_DESC_BUFFER
, nullptr, true, true);
5791 Temp vindex
= emit_extract_vector(ctx
, get_ssa_temp(ctx
, instr
->src
[1].ssa
), 0, v1
);
5794 switch (num_channels
) {
5796 opcode
= aco_opcode::buffer_load_format_x
;
5799 opcode
= aco_opcode::buffer_load_format_xy
;
5802 opcode
= aco_opcode::buffer_load_format_xyz
;
5805 opcode
= aco_opcode::buffer_load_format_xyzw
;
5808 unreachable(">4 channel buffer image load");
5810 aco_ptr
<MUBUF_instruction
> load
{create_instruction
<MUBUF_instruction
>(opcode
, Format::MUBUF
, 3, 1)};
5811 load
->operands
[0] = Operand(rsrc
);
5812 load
->operands
[1] = Operand(vindex
);
5813 load
->operands
[2] = Operand((uint32_t) 0);
5815 if (num_channels
== instr
->dest
.ssa
.num_components
&& dst
.type() == RegType::vgpr
)
5818 tmp
= {ctx
->program
->allocateId(), RegClass(RegType::vgpr
, num_channels
)};
5819 load
->definitions
[0] = Definition(tmp
);
5821 load
->glc
= var
->data
.access
& (ACCESS_VOLATILE
| ACCESS_COHERENT
);
5822 load
->dlc
= load
->glc
&& ctx
->options
->chip_class
>= GFX10
;
5823 load
->barrier
= barrier_image
;
5824 ctx
->block
->instructions
.emplace_back(std::move(load
));
5826 expand_vector(ctx
, tmp
, dst
, instr
->dest
.ssa
.num_components
, (1 << num_channels
) - 1);
5830 Temp coords
= get_image_coords(ctx
, instr
, type
);
5831 Temp resource
= get_sampler_desc(ctx
, nir_instr_as_deref(instr
->src
[0].ssa
->parent_instr
), ACO_DESC_IMAGE
, nullptr, true, true);
5833 unsigned dmask
= nir_ssa_def_components_read(&instr
->dest
.ssa
);
5834 unsigned num_components
= util_bitcount(dmask
);
5836 if (num_components
== instr
->dest
.ssa
.num_components
&& dst
.type() == RegType::vgpr
)
5839 tmp
= {ctx
->program
->allocateId(), RegClass(RegType::vgpr
, num_components
)};
5841 bool level_zero
= nir_src_is_const(instr
->src
[3]) && nir_src_as_uint(instr
->src
[3]) == 0;
5842 aco_opcode opcode
= level_zero
? aco_opcode::image_load
: aco_opcode::image_load_mip
;
5844 aco_ptr
<MIMG_instruction
> load
{create_instruction
<MIMG_instruction
>(opcode
, Format::MIMG
, 3, 1)};
5845 load
->operands
[0] = Operand(resource
);
5846 load
->operands
[1] = Operand(s4
); /* no sampler */
5847 load
->operands
[2] = Operand(coords
);
5848 load
->definitions
[0] = Definition(tmp
);
5849 load
->glc
= var
->data
.access
& (ACCESS_VOLATILE
| ACCESS_COHERENT
) ? 1 : 0;
5850 load
->dlc
= load
->glc
&& ctx
->options
->chip_class
>= GFX10
;
5851 load
->dim
= ac_get_image_dim(ctx
->options
->chip_class
, dim
, is_array
);
5852 load
->dmask
= dmask
;
5854 load
->da
= should_declare_array(ctx
, dim
, glsl_sampler_type_is_array(type
));
5855 load
->barrier
= barrier_image
;
5856 ctx
->block
->instructions
.emplace_back(std::move(load
));
5858 expand_vector(ctx
, tmp
, dst
, instr
->dest
.ssa
.num_components
, dmask
);
5862 void visit_image_store(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
5864 const nir_variable
*var
= nir_deref_instr_get_variable(nir_instr_as_deref(instr
->src
[0].ssa
->parent_instr
));
5865 const struct glsl_type
*type
= glsl_without_array(var
->type
);
5866 const enum glsl_sampler_dim dim
= glsl_get_sampler_dim(type
);
5867 bool is_array
= glsl_sampler_type_is_array(type
);
5868 Temp data
= as_vgpr(ctx
, get_ssa_temp(ctx
, instr
->src
[3].ssa
));
5870 bool glc
= ctx
->options
->chip_class
== GFX6
|| var
->data
.access
& (ACCESS_VOLATILE
| ACCESS_COHERENT
| ACCESS_NON_READABLE
) ? 1 : 0;
5872 if (dim
== GLSL_SAMPLER_DIM_BUF
) {
5873 Temp rsrc
= get_sampler_desc(ctx
, nir_instr_as_deref(instr
->src
[0].ssa
->parent_instr
), ACO_DESC_BUFFER
, nullptr, true, true);
5874 Temp vindex
= emit_extract_vector(ctx
, get_ssa_temp(ctx
, instr
->src
[1].ssa
), 0, v1
);
5876 switch (data
.size()) {
5878 opcode
= aco_opcode::buffer_store_format_x
;
5881 opcode
= aco_opcode::buffer_store_format_xy
;
5884 opcode
= aco_opcode::buffer_store_format_xyz
;
5887 opcode
= aco_opcode::buffer_store_format_xyzw
;
5890 unreachable(">4 channel buffer image store");
5892 aco_ptr
<MUBUF_instruction
> store
{create_instruction
<MUBUF_instruction
>(opcode
, Format::MUBUF
, 4, 0)};
5893 store
->operands
[0] = Operand(rsrc
);
5894 store
->operands
[1] = Operand(vindex
);
5895 store
->operands
[2] = Operand((uint32_t) 0);
5896 store
->operands
[3] = Operand(data
);
5897 store
->idxen
= true;
5900 store
->disable_wqm
= true;
5901 store
->barrier
= barrier_image
;
5902 ctx
->program
->needs_exact
= true;
5903 ctx
->block
->instructions
.emplace_back(std::move(store
));
5907 assert(data
.type() == RegType::vgpr
);
5908 Temp coords
= get_image_coords(ctx
, instr
, type
);
5909 Temp resource
= get_sampler_desc(ctx
, nir_instr_as_deref(instr
->src
[0].ssa
->parent_instr
), ACO_DESC_IMAGE
, nullptr, true, true);
5911 bool level_zero
= nir_src_is_const(instr
->src
[4]) && nir_src_as_uint(instr
->src
[4]) == 0;
5912 aco_opcode opcode
= level_zero
? aco_opcode::image_store
: aco_opcode::image_store_mip
;
5914 aco_ptr
<MIMG_instruction
> store
{create_instruction
<MIMG_instruction
>(opcode
, Format::MIMG
, 3, 0)};
5915 store
->operands
[0] = Operand(resource
);
5916 store
->operands
[1] = Operand(data
);
5917 store
->operands
[2] = Operand(coords
);
5920 store
->dim
= ac_get_image_dim(ctx
->options
->chip_class
, dim
, is_array
);
5921 store
->dmask
= (1 << data
.size()) - 1;
5923 store
->da
= should_declare_array(ctx
, dim
, glsl_sampler_type_is_array(type
));
5924 store
->disable_wqm
= true;
5925 store
->barrier
= barrier_image
;
5926 ctx
->program
->needs_exact
= true;
5927 ctx
->block
->instructions
.emplace_back(std::move(store
));
5931 void visit_image_atomic(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
5933 /* return the previous value if dest is ever used */
5934 bool return_previous
= false;
5935 nir_foreach_use_safe(use_src
, &instr
->dest
.ssa
) {
5936 return_previous
= true;
5939 nir_foreach_if_use_safe(use_src
, &instr
->dest
.ssa
) {
5940 return_previous
= true;
5944 const nir_variable
*var
= nir_deref_instr_get_variable(nir_instr_as_deref(instr
->src
[0].ssa
->parent_instr
));
5945 const struct glsl_type
*type
= glsl_without_array(var
->type
);
5946 const enum glsl_sampler_dim dim
= glsl_get_sampler_dim(type
);
5947 bool is_array
= glsl_sampler_type_is_array(type
);
5948 Builder
bld(ctx
->program
, ctx
->block
);
5950 Temp data
= as_vgpr(ctx
, get_ssa_temp(ctx
, instr
->src
[3].ssa
));
5951 assert(data
.size() == 1 && "64bit ssbo atomics not yet implemented.");
5953 if (instr
->intrinsic
== nir_intrinsic_image_deref_atomic_comp_swap
)
5954 data
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), get_ssa_temp(ctx
, instr
->src
[4].ssa
), data
);
5956 aco_opcode buf_op
, image_op
;
5957 switch (instr
->intrinsic
) {
5958 case nir_intrinsic_image_deref_atomic_add
:
5959 buf_op
= aco_opcode::buffer_atomic_add
;
5960 image_op
= aco_opcode::image_atomic_add
;
5962 case nir_intrinsic_image_deref_atomic_umin
:
5963 buf_op
= aco_opcode::buffer_atomic_umin
;
5964 image_op
= aco_opcode::image_atomic_umin
;
5966 case nir_intrinsic_image_deref_atomic_imin
:
5967 buf_op
= aco_opcode::buffer_atomic_smin
;
5968 image_op
= aco_opcode::image_atomic_smin
;
5970 case nir_intrinsic_image_deref_atomic_umax
:
5971 buf_op
= aco_opcode::buffer_atomic_umax
;
5972 image_op
= aco_opcode::image_atomic_umax
;
5974 case nir_intrinsic_image_deref_atomic_imax
:
5975 buf_op
= aco_opcode::buffer_atomic_smax
;
5976 image_op
= aco_opcode::image_atomic_smax
;
5978 case nir_intrinsic_image_deref_atomic_and
:
5979 buf_op
= aco_opcode::buffer_atomic_and
;
5980 image_op
= aco_opcode::image_atomic_and
;
5982 case nir_intrinsic_image_deref_atomic_or
:
5983 buf_op
= aco_opcode::buffer_atomic_or
;
5984 image_op
= aco_opcode::image_atomic_or
;
5986 case nir_intrinsic_image_deref_atomic_xor
:
5987 buf_op
= aco_opcode::buffer_atomic_xor
;
5988 image_op
= aco_opcode::image_atomic_xor
;
5990 case nir_intrinsic_image_deref_atomic_exchange
:
5991 buf_op
= aco_opcode::buffer_atomic_swap
;
5992 image_op
= aco_opcode::image_atomic_swap
;
5994 case nir_intrinsic_image_deref_atomic_comp_swap
:
5995 buf_op
= aco_opcode::buffer_atomic_cmpswap
;
5996 image_op
= aco_opcode::image_atomic_cmpswap
;
5999 unreachable("visit_image_atomic should only be called with nir_intrinsic_image_deref_atomic_* instructions.");
6002 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
6004 if (dim
== GLSL_SAMPLER_DIM_BUF
) {
6005 Temp vindex
= emit_extract_vector(ctx
, get_ssa_temp(ctx
, instr
->src
[1].ssa
), 0, v1
);
6006 Temp resource
= get_sampler_desc(ctx
, nir_instr_as_deref(instr
->src
[0].ssa
->parent_instr
), ACO_DESC_BUFFER
, nullptr, true, true);
6007 //assert(ctx->options->chip_class < GFX9 && "GFX9 stride size workaround not yet implemented.");
6008 aco_ptr
<MUBUF_instruction
> mubuf
{create_instruction
<MUBUF_instruction
>(buf_op
, Format::MUBUF
, 4, return_previous
? 1 : 0)};
6009 mubuf
->operands
[0] = Operand(resource
);
6010 mubuf
->operands
[1] = Operand(vindex
);
6011 mubuf
->operands
[2] = Operand((uint32_t)0);
6012 mubuf
->operands
[3] = Operand(data
);
6013 if (return_previous
)
6014 mubuf
->definitions
[0] = Definition(dst
);
6016 mubuf
->idxen
= true;
6017 mubuf
->glc
= return_previous
;
6018 mubuf
->dlc
= false; /* Not needed for atomics */
6019 mubuf
->disable_wqm
= true;
6020 mubuf
->barrier
= barrier_image
;
6021 ctx
->program
->needs_exact
= true;
6022 ctx
->block
->instructions
.emplace_back(std::move(mubuf
));
6026 Temp coords
= get_image_coords(ctx
, instr
, type
);
6027 Temp resource
= get_sampler_desc(ctx
, nir_instr_as_deref(instr
->src
[0].ssa
->parent_instr
), ACO_DESC_IMAGE
, nullptr, true, true);
6028 aco_ptr
<MIMG_instruction
> mimg
{create_instruction
<MIMG_instruction
>(image_op
, Format::MIMG
, 3, return_previous
? 1 : 0)};
6029 mimg
->operands
[0] = Operand(resource
);
6030 mimg
->operands
[1] = Operand(data
);
6031 mimg
->operands
[2] = Operand(coords
);
6032 if (return_previous
)
6033 mimg
->definitions
[0] = Definition(dst
);
6034 mimg
->glc
= return_previous
;
6035 mimg
->dlc
= false; /* Not needed for atomics */
6036 mimg
->dim
= ac_get_image_dim(ctx
->options
->chip_class
, dim
, is_array
);
6037 mimg
->dmask
= (1 << data
.size()) - 1;
6039 mimg
->da
= should_declare_array(ctx
, dim
, glsl_sampler_type_is_array(type
));
6040 mimg
->disable_wqm
= true;
6041 mimg
->barrier
= barrier_image
;
6042 ctx
->program
->needs_exact
= true;
6043 ctx
->block
->instructions
.emplace_back(std::move(mimg
));
6047 void get_buffer_size(isel_context
*ctx
, Temp desc
, Temp dst
, bool in_elements
)
6049 if (in_elements
&& ctx
->options
->chip_class
== GFX8
) {
6050 /* we only have to divide by 1, 2, 4, 8, 12 or 16 */
6051 Builder
bld(ctx
->program
, ctx
->block
);
6053 Temp size
= emit_extract_vector(ctx
, desc
, 2, s1
);
6055 Temp size_div3
= bld
.vop3(aco_opcode::v_mul_hi_u32
, bld
.def(v1
), bld
.copy(bld
.def(v1
), Operand(0xaaaaaaabu
)), size
);
6056 size_div3
= bld
.sop2(aco_opcode::s_lshr_b32
, bld
.def(s1
), bld
.as_uniform(size_div3
), Operand(1u));
6058 Temp stride
= emit_extract_vector(ctx
, desc
, 1, s1
);
6059 stride
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
), stride
, Operand((5u << 16) | 16u));
6061 Temp is12
= bld
.sopc(aco_opcode::s_cmp_eq_i32
, bld
.def(s1
, scc
), stride
, Operand(12u));
6062 size
= bld
.sop2(aco_opcode::s_cselect_b32
, bld
.def(s1
), size_div3
, size
, bld
.scc(is12
));
6064 Temp shr_dst
= dst
.type() == RegType::vgpr
? bld
.tmp(s1
) : dst
;
6065 bld
.sop2(aco_opcode::s_lshr_b32
, Definition(shr_dst
), bld
.def(s1
, scc
),
6066 size
, bld
.sop1(aco_opcode::s_ff1_i32_b32
, bld
.def(s1
), stride
));
6067 if (dst
.type() == RegType::vgpr
)
6068 bld
.copy(Definition(dst
), shr_dst
);
6070 /* TODO: we can probably calculate this faster with v_skip when stride != 12 */
6072 emit_extract_vector(ctx
, desc
, 2, dst
);
6076 void visit_image_size(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
6078 const nir_variable
*var
= nir_deref_instr_get_variable(nir_instr_as_deref(instr
->src
[0].ssa
->parent_instr
));
6079 const struct glsl_type
*type
= glsl_without_array(var
->type
);
6080 const enum glsl_sampler_dim dim
= glsl_get_sampler_dim(type
);
6081 bool is_array
= glsl_sampler_type_is_array(type
);
6082 Builder
bld(ctx
->program
, ctx
->block
);
6084 if (glsl_get_sampler_dim(type
) == GLSL_SAMPLER_DIM_BUF
) {
6085 Temp desc
= get_sampler_desc(ctx
, nir_instr_as_deref(instr
->src
[0].ssa
->parent_instr
), ACO_DESC_BUFFER
, NULL
, true, false);
6086 return get_buffer_size(ctx
, desc
, get_ssa_temp(ctx
, &instr
->dest
.ssa
), true);
6090 Temp lod
= bld
.vop1(aco_opcode::v_mov_b32
, bld
.def(v1
), Operand(0u));
6093 Temp resource
= get_sampler_desc(ctx
, nir_instr_as_deref(instr
->src
[0].ssa
->parent_instr
), ACO_DESC_IMAGE
, NULL
, true, false);
6095 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
6097 aco_ptr
<MIMG_instruction
> mimg
{create_instruction
<MIMG_instruction
>(aco_opcode::image_get_resinfo
, Format::MIMG
, 3, 1)};
6098 mimg
->operands
[0] = Operand(resource
);
6099 mimg
->operands
[1] = Operand(s4
); /* no sampler */
6100 mimg
->operands
[2] = Operand(lod
);
6101 uint8_t& dmask
= mimg
->dmask
;
6102 mimg
->dim
= ac_get_image_dim(ctx
->options
->chip_class
, dim
, is_array
);
6103 mimg
->dmask
= (1 << instr
->dest
.ssa
.num_components
) - 1;
6104 mimg
->da
= glsl_sampler_type_is_array(type
);
6105 mimg
->can_reorder
= true;
6106 Definition
& def
= mimg
->definitions
[0];
6107 ctx
->block
->instructions
.emplace_back(std::move(mimg
));
6109 if (glsl_get_sampler_dim(type
) == GLSL_SAMPLER_DIM_CUBE
&&
6110 glsl_sampler_type_is_array(type
)) {
6112 assert(instr
->dest
.ssa
.num_components
== 3);
6113 Temp tmp
= {ctx
->program
->allocateId(), v3
};
6114 def
= Definition(tmp
);
6115 emit_split_vector(ctx
, tmp
, 3);
6117 /* divide 3rd value by 6 by multiplying with magic number */
6118 Temp c
= bld
.copy(bld
.def(s1
), Operand((uint32_t) 0x2AAAAAAB));
6119 Temp by_6
= bld
.vop3(aco_opcode::v_mul_hi_i32
, bld
.def(v1
), emit_extract_vector(ctx
, tmp
, 2, v1
), c
);
6121 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
),
6122 emit_extract_vector(ctx
, tmp
, 0, v1
),
6123 emit_extract_vector(ctx
, tmp
, 1, v1
),
6126 } else if (ctx
->options
->chip_class
== GFX9
&&
6127 glsl_get_sampler_dim(type
) == GLSL_SAMPLER_DIM_1D
&&
6128 glsl_sampler_type_is_array(type
)) {
6129 assert(instr
->dest
.ssa
.num_components
== 2);
6130 def
= Definition(dst
);
6133 def
= Definition(dst
);
6136 emit_split_vector(ctx
, dst
, instr
->dest
.ssa
.num_components
);
6139 void visit_load_ssbo(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
6141 Builder
bld(ctx
->program
, ctx
->block
);
6142 unsigned num_components
= instr
->num_components
;
6144 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
6145 Temp rsrc
= convert_pointer_to_64_bit(ctx
, get_ssa_temp(ctx
, instr
->src
[0].ssa
));
6146 rsrc
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), rsrc
, Operand(0u));
6148 unsigned access
= nir_intrinsic_access(instr
);
6149 bool glc
= access
& (ACCESS_VOLATILE
| ACCESS_COHERENT
);
6150 unsigned size
= instr
->dest
.ssa
.bit_size
/ 8;
6152 uint32_t flags
= get_all_buffer_resource_flags(ctx
, instr
->src
[0].ssa
, access
);
6153 /* GLC bypasses VMEM/SMEM caches, so GLC SMEM loads/stores are coherent with GLC VMEM loads/stores
6154 * TODO: this optimization is disabled for now because we still need to ensure correct ordering
6156 bool allow_smem
= !(flags
& (0 && glc
? has_nonglc_vmem_store
: has_vmem_store
));
6157 allow_smem
|= ((access
& ACCESS_RESTRICT
) && (access
& ACCESS_NON_WRITEABLE
)) || (access
& ACCESS_CAN_REORDER
);
6159 load_buffer(ctx
, num_components
, size
, dst
, rsrc
, get_ssa_temp(ctx
, instr
->src
[1].ssa
),
6160 nir_intrinsic_align_mul(instr
), nir_intrinsic_align_offset(instr
), glc
, false, allow_smem
);
6163 void visit_store_ssbo(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
6165 Builder
bld(ctx
->program
, ctx
->block
);
6166 Temp data
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
6167 unsigned elem_size_bytes
= instr
->src
[0].ssa
->bit_size
/ 8;
6168 unsigned writemask
= widen_mask(nir_intrinsic_write_mask(instr
), elem_size_bytes
);
6169 Temp offset
= get_ssa_temp(ctx
, instr
->src
[2].ssa
);
6171 Temp rsrc
= convert_pointer_to_64_bit(ctx
, get_ssa_temp(ctx
, instr
->src
[1].ssa
));
6172 rsrc
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), rsrc
, Operand(0u));
6174 bool glc
= nir_intrinsic_access(instr
) & (ACCESS_VOLATILE
| ACCESS_COHERENT
| ACCESS_NON_READABLE
);
6175 uint32_t flags
= get_all_buffer_resource_flags(ctx
, instr
->src
[1].ssa
, nir_intrinsic_access(instr
));
6176 /* GLC bypasses VMEM/SMEM caches, so GLC SMEM loads/stores are coherent with GLC VMEM loads/stores
6177 * TODO: this optimization is disabled for now because we still need to ensure correct ordering
6179 bool allow_smem
= !(flags
& (0 && glc
? has_nonglc_vmem_loadstore
: has_vmem_loadstore
));
6181 bool smem
= !nir_src_is_divergent(instr
->src
[2]) &&
6182 ctx
->options
->chip_class
>= GFX8
&&
6183 (elem_size_bytes
>= 4 || can_subdword_ssbo_store_use_smem(instr
)) &&
6186 offset
= bld
.as_uniform(offset
);
6187 bool smem_nonfs
= smem
&& ctx
->stage
!= fragment_fs
;
6189 unsigned write_count
= 0;
6190 Temp write_datas
[32];
6191 unsigned offsets
[32];
6192 split_buffer_store(ctx
, instr
, smem
, smem_nonfs
? RegType::sgpr
: (smem
? data
.type() : RegType::vgpr
),
6193 data
, writemask
, 16, &write_count
, write_datas
, offsets
);
6195 for (unsigned i
= 0; i
< write_count
; i
++) {
6196 aco_opcode op
= get_buffer_store_op(smem
, write_datas
[i
].bytes());
6197 if (smem
&& ctx
->stage
== fragment_fs
)
6198 op
= aco_opcode::p_fs_buffer_store_smem
;
6201 aco_ptr
<SMEM_instruction
> store
{create_instruction
<SMEM_instruction
>(op
, Format::SMEM
, 3, 0)};
6202 store
->operands
[0] = Operand(rsrc
);
6204 Temp off
= bld
.sop2(aco_opcode::s_add_i32
, bld
.def(s1
), bld
.def(s1
, scc
),
6205 offset
, Operand(offsets
[i
]));
6206 store
->operands
[1] = Operand(off
);
6208 store
->operands
[1] = Operand(offset
);
6210 if (op
!= aco_opcode::p_fs_buffer_store_smem
)
6211 store
->operands
[1].setFixed(m0
);
6212 store
->operands
[2] = Operand(write_datas
[i
]);
6215 store
->disable_wqm
= true;
6216 store
->barrier
= barrier_buffer
;
6217 ctx
->block
->instructions
.emplace_back(std::move(store
));
6218 ctx
->program
->wb_smem_l1_on_end
= true;
6219 if (op
== aco_opcode::p_fs_buffer_store_smem
) {
6220 ctx
->block
->kind
|= block_kind_needs_lowering
;
6221 ctx
->program
->needs_exact
= true;
6224 aco_ptr
<MUBUF_instruction
> store
{create_instruction
<MUBUF_instruction
>(op
, Format::MUBUF
, 4, 0)};
6225 store
->operands
[0] = Operand(rsrc
);
6226 store
->operands
[1] = offset
.type() == RegType::vgpr
? Operand(offset
) : Operand(v1
);
6227 store
->operands
[2] = offset
.type() == RegType::sgpr
? Operand(offset
) : Operand((uint32_t) 0);
6228 store
->operands
[3] = Operand(write_datas
[i
]);
6229 store
->offset
= offsets
[i
];
6230 store
->offen
= (offset
.type() == RegType::vgpr
);
6233 store
->disable_wqm
= true;
6234 store
->barrier
= barrier_buffer
;
6235 ctx
->program
->needs_exact
= true;
6236 ctx
->block
->instructions
.emplace_back(std::move(store
));
6241 void visit_atomic_ssbo(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
6243 /* return the previous value if dest is ever used */
6244 bool return_previous
= false;
6245 nir_foreach_use_safe(use_src
, &instr
->dest
.ssa
) {
6246 return_previous
= true;
6249 nir_foreach_if_use_safe(use_src
, &instr
->dest
.ssa
) {
6250 return_previous
= true;
6254 Builder
bld(ctx
->program
, ctx
->block
);
6255 Temp data
= as_vgpr(ctx
, get_ssa_temp(ctx
, instr
->src
[2].ssa
));
6257 if (instr
->intrinsic
== nir_intrinsic_ssbo_atomic_comp_swap
)
6258 data
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(RegType::vgpr
, data
.size() * 2),
6259 get_ssa_temp(ctx
, instr
->src
[3].ssa
), data
);
6261 Temp offset
= get_ssa_temp(ctx
, instr
->src
[1].ssa
);
6262 Temp rsrc
= convert_pointer_to_64_bit(ctx
, get_ssa_temp(ctx
, instr
->src
[0].ssa
));
6263 rsrc
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), rsrc
, Operand(0u));
6265 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
6267 aco_opcode op32
, op64
;
6268 switch (instr
->intrinsic
) {
6269 case nir_intrinsic_ssbo_atomic_add
:
6270 op32
= aco_opcode::buffer_atomic_add
;
6271 op64
= aco_opcode::buffer_atomic_add_x2
;
6273 case nir_intrinsic_ssbo_atomic_imin
:
6274 op32
= aco_opcode::buffer_atomic_smin
;
6275 op64
= aco_opcode::buffer_atomic_smin_x2
;
6277 case nir_intrinsic_ssbo_atomic_umin
:
6278 op32
= aco_opcode::buffer_atomic_umin
;
6279 op64
= aco_opcode::buffer_atomic_umin_x2
;
6281 case nir_intrinsic_ssbo_atomic_imax
:
6282 op32
= aco_opcode::buffer_atomic_smax
;
6283 op64
= aco_opcode::buffer_atomic_smax_x2
;
6285 case nir_intrinsic_ssbo_atomic_umax
:
6286 op32
= aco_opcode::buffer_atomic_umax
;
6287 op64
= aco_opcode::buffer_atomic_umax_x2
;
6289 case nir_intrinsic_ssbo_atomic_and
:
6290 op32
= aco_opcode::buffer_atomic_and
;
6291 op64
= aco_opcode::buffer_atomic_and_x2
;
6293 case nir_intrinsic_ssbo_atomic_or
:
6294 op32
= aco_opcode::buffer_atomic_or
;
6295 op64
= aco_opcode::buffer_atomic_or_x2
;
6297 case nir_intrinsic_ssbo_atomic_xor
:
6298 op32
= aco_opcode::buffer_atomic_xor
;
6299 op64
= aco_opcode::buffer_atomic_xor_x2
;
6301 case nir_intrinsic_ssbo_atomic_exchange
:
6302 op32
= aco_opcode::buffer_atomic_swap
;
6303 op64
= aco_opcode::buffer_atomic_swap_x2
;
6305 case nir_intrinsic_ssbo_atomic_comp_swap
:
6306 op32
= aco_opcode::buffer_atomic_cmpswap
;
6307 op64
= aco_opcode::buffer_atomic_cmpswap_x2
;
6310 unreachable("visit_atomic_ssbo should only be called with nir_intrinsic_ssbo_atomic_* instructions.");
6312 aco_opcode op
= instr
->dest
.ssa
.bit_size
== 32 ? op32
: op64
;
6313 aco_ptr
<MUBUF_instruction
> mubuf
{create_instruction
<MUBUF_instruction
>(op
, Format::MUBUF
, 4, return_previous
? 1 : 0)};
6314 mubuf
->operands
[0] = Operand(rsrc
);
6315 mubuf
->operands
[1] = offset
.type() == RegType::vgpr
? Operand(offset
) : Operand(v1
);
6316 mubuf
->operands
[2] = offset
.type() == RegType::sgpr
? Operand(offset
) : Operand((uint32_t) 0);
6317 mubuf
->operands
[3] = Operand(data
);
6318 if (return_previous
)
6319 mubuf
->definitions
[0] = Definition(dst
);
6321 mubuf
->offen
= (offset
.type() == RegType::vgpr
);
6322 mubuf
->glc
= return_previous
;
6323 mubuf
->dlc
= false; /* Not needed for atomics */
6324 mubuf
->disable_wqm
= true;
6325 mubuf
->barrier
= barrier_buffer
;
6326 ctx
->program
->needs_exact
= true;
6327 ctx
->block
->instructions
.emplace_back(std::move(mubuf
));
6330 void visit_get_buffer_size(isel_context
*ctx
, nir_intrinsic_instr
*instr
) {
6332 Temp index
= convert_pointer_to_64_bit(ctx
, get_ssa_temp(ctx
, instr
->src
[0].ssa
));
6333 Builder
bld(ctx
->program
, ctx
->block
);
6334 Temp desc
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), index
, Operand(0u));
6335 get_buffer_size(ctx
, desc
, get_ssa_temp(ctx
, &instr
->dest
.ssa
), false);
6338 void visit_load_global(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
6340 Builder
bld(ctx
->program
, ctx
->block
);
6341 unsigned num_components
= instr
->num_components
;
6342 unsigned component_size
= instr
->dest
.ssa
.bit_size
/ 8;
6344 LoadEmitInfo info
= {Operand(get_ssa_temp(ctx
, instr
->src
[0].ssa
)),
6345 get_ssa_temp(ctx
, &instr
->dest
.ssa
),
6346 num_components
, component_size
};
6347 info
.glc
= nir_intrinsic_access(instr
) & (ACCESS_VOLATILE
| ACCESS_COHERENT
);
6348 info
.align_mul
= nir_intrinsic_align_mul(instr
);
6349 info
.align_offset
= nir_intrinsic_align_offset(instr
);
6350 info
.barrier
= barrier_buffer
;
6351 info
.can_reorder
= false;
6352 /* VMEM stores don't update the SMEM cache and it's difficult to prove that
6353 * it's safe to use SMEM */
6354 bool can_use_smem
= nir_intrinsic_access(instr
) & ACCESS_NON_WRITEABLE
;
6355 if (info
.dst
.type() == RegType::vgpr
|| (info
.glc
&& ctx
->options
->chip_class
< GFX8
) || !can_use_smem
) {
6356 emit_global_load(ctx
, bld
, &info
);
6358 info
.offset
= Operand(bld
.as_uniform(info
.offset
));
6359 emit_smem_load(ctx
, bld
, &info
);
6363 void visit_store_global(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
6365 Builder
bld(ctx
->program
, ctx
->block
);
6366 unsigned elem_size_bytes
= instr
->src
[0].ssa
->bit_size
/ 8;
6367 unsigned writemask
= widen_mask(nir_intrinsic_write_mask(instr
), elem_size_bytes
);
6369 Temp data
= as_vgpr(ctx
, get_ssa_temp(ctx
, instr
->src
[0].ssa
));
6370 Temp addr
= get_ssa_temp(ctx
, instr
->src
[1].ssa
);
6371 bool glc
= nir_intrinsic_access(instr
) & (ACCESS_VOLATILE
| ACCESS_COHERENT
| ACCESS_NON_READABLE
);
6373 if (ctx
->options
->chip_class
>= GFX7
)
6374 addr
= as_vgpr(ctx
, addr
);
6376 unsigned write_count
= 0;
6377 Temp write_datas
[32];
6378 unsigned offsets
[32];
6379 split_buffer_store(ctx
, instr
, false, RegType::vgpr
, data
, writemask
,
6380 16, &write_count
, write_datas
, offsets
);
6382 for (unsigned i
= 0; i
< write_count
; i
++) {
6383 if (ctx
->options
->chip_class
>= GFX7
) {
6384 unsigned offset
= offsets
[i
];
6385 Temp store_addr
= addr
;
6386 if (offset
> 0 && ctx
->options
->chip_class
< GFX9
) {
6387 Temp addr0
= bld
.tmp(v1
), addr1
= bld
.tmp(v1
);
6388 Temp new_addr0
= bld
.tmp(v1
), new_addr1
= bld
.tmp(v1
);
6389 Temp carry
= bld
.tmp(bld
.lm
);
6390 bld
.pseudo(aco_opcode::p_split_vector
, Definition(addr0
), Definition(addr1
), addr
);
6392 bld
.vop2(aco_opcode::v_add_co_u32
, Definition(new_addr0
), bld
.hint_vcc(Definition(carry
)),
6393 Operand(offset
), addr0
);
6394 bld
.vop2(aco_opcode::v_addc_co_u32
, Definition(new_addr1
), bld
.def(bld
.lm
),
6396 carry
).def(1).setHint(vcc
);
6398 store_addr
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), new_addr0
, new_addr1
);
6403 bool global
= ctx
->options
->chip_class
>= GFX9
;
6405 switch (write_datas
[i
].bytes()) {
6407 op
= global
? aco_opcode::global_store_byte
: aco_opcode::flat_store_byte
;
6410 op
= global
? aco_opcode::global_store_short
: aco_opcode::flat_store_short
;
6413 op
= global
? aco_opcode::global_store_dword
: aco_opcode::flat_store_dword
;
6416 op
= global
? aco_opcode::global_store_dwordx2
: aco_opcode::flat_store_dwordx2
;
6419 op
= global
? aco_opcode::global_store_dwordx3
: aco_opcode::flat_store_dwordx3
;
6422 op
= global
? aco_opcode::global_store_dwordx4
: aco_opcode::flat_store_dwordx4
;
6425 unreachable("store_global not implemented for this size.");
6428 aco_ptr
<FLAT_instruction
> flat
{create_instruction
<FLAT_instruction
>(op
, global
? Format::GLOBAL
: Format::FLAT
, 3, 0)};
6429 flat
->operands
[0] = Operand(store_addr
);
6430 flat
->operands
[1] = Operand(s1
);
6431 flat
->operands
[2] = Operand(write_datas
[i
]);
6434 flat
->offset
= offset
;
6435 flat
->disable_wqm
= true;
6436 flat
->barrier
= barrier_buffer
;
6437 ctx
->program
->needs_exact
= true;
6438 ctx
->block
->instructions
.emplace_back(std::move(flat
));
6440 assert(ctx
->options
->chip_class
== GFX6
);
6442 aco_opcode op
= get_buffer_store_op(false, write_datas
[i
].bytes());
6444 Temp rsrc
= get_gfx6_global_rsrc(bld
, addr
);
6446 aco_ptr
<MUBUF_instruction
> mubuf
{create_instruction
<MUBUF_instruction
>(op
, Format::MUBUF
, 4, 0)};
6447 mubuf
->operands
[0] = Operand(rsrc
);
6448 mubuf
->operands
[1] = addr
.type() == RegType::vgpr
? Operand(addr
) : Operand(v1
);
6449 mubuf
->operands
[2] = Operand(0u);
6450 mubuf
->operands
[3] = Operand(write_datas
[i
]);
6453 mubuf
->offset
= offsets
[i
];
6454 mubuf
->addr64
= addr
.type() == RegType::vgpr
;
6455 mubuf
->disable_wqm
= true;
6456 mubuf
->barrier
= barrier_buffer
;
6457 ctx
->program
->needs_exact
= true;
6458 ctx
->block
->instructions
.emplace_back(std::move(mubuf
));
6463 void visit_global_atomic(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
6465 /* return the previous value if dest is ever used */
6466 bool return_previous
= false;
6467 nir_foreach_use_safe(use_src
, &instr
->dest
.ssa
) {
6468 return_previous
= true;
6471 nir_foreach_if_use_safe(use_src
, &instr
->dest
.ssa
) {
6472 return_previous
= true;
6476 Builder
bld(ctx
->program
, ctx
->block
);
6477 Temp addr
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
6478 Temp data
= as_vgpr(ctx
, get_ssa_temp(ctx
, instr
->src
[1].ssa
));
6480 if (ctx
->options
->chip_class
>= GFX7
)
6481 addr
= as_vgpr(ctx
, addr
);
6483 if (instr
->intrinsic
== nir_intrinsic_global_atomic_comp_swap
)
6484 data
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(RegType::vgpr
, data
.size() * 2),
6485 get_ssa_temp(ctx
, instr
->src
[2].ssa
), data
);
6487 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
6489 aco_opcode op32
, op64
;
6491 if (ctx
->options
->chip_class
>= GFX7
) {
6492 bool global
= ctx
->options
->chip_class
>= GFX9
;
6493 switch (instr
->intrinsic
) {
6494 case nir_intrinsic_global_atomic_add
:
6495 op32
= global
? aco_opcode::global_atomic_add
: aco_opcode::flat_atomic_add
;
6496 op64
= global
? aco_opcode::global_atomic_add_x2
: aco_opcode::flat_atomic_add_x2
;
6498 case nir_intrinsic_global_atomic_imin
:
6499 op32
= global
? aco_opcode::global_atomic_smin
: aco_opcode::flat_atomic_smin
;
6500 op64
= global
? aco_opcode::global_atomic_smin_x2
: aco_opcode::flat_atomic_smin_x2
;
6502 case nir_intrinsic_global_atomic_umin
:
6503 op32
= global
? aco_opcode::global_atomic_umin
: aco_opcode::flat_atomic_umin
;
6504 op64
= global
? aco_opcode::global_atomic_umin_x2
: aco_opcode::flat_atomic_umin_x2
;
6506 case nir_intrinsic_global_atomic_imax
:
6507 op32
= global
? aco_opcode::global_atomic_smax
: aco_opcode::flat_atomic_smax
;
6508 op64
= global
? aco_opcode::global_atomic_smax_x2
: aco_opcode::flat_atomic_smax_x2
;
6510 case nir_intrinsic_global_atomic_umax
:
6511 op32
= global
? aco_opcode::global_atomic_umax
: aco_opcode::flat_atomic_umax
;
6512 op64
= global
? aco_opcode::global_atomic_umax_x2
: aco_opcode::flat_atomic_umax_x2
;
6514 case nir_intrinsic_global_atomic_and
:
6515 op32
= global
? aco_opcode::global_atomic_and
: aco_opcode::flat_atomic_and
;
6516 op64
= global
? aco_opcode::global_atomic_and_x2
: aco_opcode::flat_atomic_and_x2
;
6518 case nir_intrinsic_global_atomic_or
:
6519 op32
= global
? aco_opcode::global_atomic_or
: aco_opcode::flat_atomic_or
;
6520 op64
= global
? aco_opcode::global_atomic_or_x2
: aco_opcode::flat_atomic_or_x2
;
6522 case nir_intrinsic_global_atomic_xor
:
6523 op32
= global
? aco_opcode::global_atomic_xor
: aco_opcode::flat_atomic_xor
;
6524 op64
= global
? aco_opcode::global_atomic_xor_x2
: aco_opcode::flat_atomic_xor_x2
;
6526 case nir_intrinsic_global_atomic_exchange
:
6527 op32
= global
? aco_opcode::global_atomic_swap
: aco_opcode::flat_atomic_swap
;
6528 op64
= global
? aco_opcode::global_atomic_swap_x2
: aco_opcode::flat_atomic_swap_x2
;
6530 case nir_intrinsic_global_atomic_comp_swap
:
6531 op32
= global
? aco_opcode::global_atomic_cmpswap
: aco_opcode::flat_atomic_cmpswap
;
6532 op64
= global
? aco_opcode::global_atomic_cmpswap_x2
: aco_opcode::flat_atomic_cmpswap_x2
;
6535 unreachable("visit_atomic_global should only be called with nir_intrinsic_global_atomic_* instructions.");
6538 aco_opcode op
= instr
->dest
.ssa
.bit_size
== 32 ? op32
: op64
;
6539 aco_ptr
<FLAT_instruction
> flat
{create_instruction
<FLAT_instruction
>(op
, global
? Format::GLOBAL
: Format::FLAT
, 3, return_previous
? 1 : 0)};
6540 flat
->operands
[0] = Operand(addr
);
6541 flat
->operands
[1] = Operand(s1
);
6542 flat
->operands
[2] = Operand(data
);
6543 if (return_previous
)
6544 flat
->definitions
[0] = Definition(dst
);
6545 flat
->glc
= return_previous
;
6546 flat
->dlc
= false; /* Not needed for atomics */
6548 flat
->disable_wqm
= true;
6549 flat
->barrier
= barrier_buffer
;
6550 ctx
->program
->needs_exact
= true;
6551 ctx
->block
->instructions
.emplace_back(std::move(flat
));
6553 assert(ctx
->options
->chip_class
== GFX6
);
6555 switch (instr
->intrinsic
) {
6556 case nir_intrinsic_global_atomic_add
:
6557 op32
= aco_opcode::buffer_atomic_add
;
6558 op64
= aco_opcode::buffer_atomic_add_x2
;
6560 case nir_intrinsic_global_atomic_imin
:
6561 op32
= aco_opcode::buffer_atomic_smin
;
6562 op64
= aco_opcode::buffer_atomic_smin_x2
;
6564 case nir_intrinsic_global_atomic_umin
:
6565 op32
= aco_opcode::buffer_atomic_umin
;
6566 op64
= aco_opcode::buffer_atomic_umin_x2
;
6568 case nir_intrinsic_global_atomic_imax
:
6569 op32
= aco_opcode::buffer_atomic_smax
;
6570 op64
= aco_opcode::buffer_atomic_smax_x2
;
6572 case nir_intrinsic_global_atomic_umax
:
6573 op32
= aco_opcode::buffer_atomic_umax
;
6574 op64
= aco_opcode::buffer_atomic_umax_x2
;
6576 case nir_intrinsic_global_atomic_and
:
6577 op32
= aco_opcode::buffer_atomic_and
;
6578 op64
= aco_opcode::buffer_atomic_and_x2
;
6580 case nir_intrinsic_global_atomic_or
:
6581 op32
= aco_opcode::buffer_atomic_or
;
6582 op64
= aco_opcode::buffer_atomic_or_x2
;
6584 case nir_intrinsic_global_atomic_xor
:
6585 op32
= aco_opcode::buffer_atomic_xor
;
6586 op64
= aco_opcode::buffer_atomic_xor_x2
;
6588 case nir_intrinsic_global_atomic_exchange
:
6589 op32
= aco_opcode::buffer_atomic_swap
;
6590 op64
= aco_opcode::buffer_atomic_swap_x2
;
6592 case nir_intrinsic_global_atomic_comp_swap
:
6593 op32
= aco_opcode::buffer_atomic_cmpswap
;
6594 op64
= aco_opcode::buffer_atomic_cmpswap_x2
;
6597 unreachable("visit_atomic_global should only be called with nir_intrinsic_global_atomic_* instructions.");
6600 Temp rsrc
= get_gfx6_global_rsrc(bld
, addr
);
6602 aco_opcode op
= instr
->dest
.ssa
.bit_size
== 32 ? op32
: op64
;
6604 aco_ptr
<MUBUF_instruction
> mubuf
{create_instruction
<MUBUF_instruction
>(op
, Format::MUBUF
, 4, return_previous
? 1 : 0)};
6605 mubuf
->operands
[0] = Operand(rsrc
);
6606 mubuf
->operands
[1] = addr
.type() == RegType::vgpr
? Operand(addr
) : Operand(v1
);
6607 mubuf
->operands
[2] = Operand(0u);
6608 mubuf
->operands
[3] = Operand(data
);
6609 if (return_previous
)
6610 mubuf
->definitions
[0] = Definition(dst
);
6611 mubuf
->glc
= return_previous
;
6614 mubuf
->addr64
= addr
.type() == RegType::vgpr
;
6615 mubuf
->disable_wqm
= true;
6616 mubuf
->barrier
= barrier_buffer
;
6617 ctx
->program
->needs_exact
= true;
6618 ctx
->block
->instructions
.emplace_back(std::move(mubuf
));
6622 void emit_memory_barrier(isel_context
*ctx
, nir_intrinsic_instr
*instr
) {
6623 Builder
bld(ctx
->program
, ctx
->block
);
6624 switch(instr
->intrinsic
) {
6625 case nir_intrinsic_group_memory_barrier
:
6626 case nir_intrinsic_memory_barrier
:
6627 bld
.barrier(aco_opcode::p_memory_barrier_common
);
6629 case nir_intrinsic_memory_barrier_buffer
:
6630 bld
.barrier(aco_opcode::p_memory_barrier_buffer
);
6632 case nir_intrinsic_memory_barrier_image
:
6633 bld
.barrier(aco_opcode::p_memory_barrier_image
);
6635 case nir_intrinsic_memory_barrier_tcs_patch
:
6636 case nir_intrinsic_memory_barrier_shared
:
6637 bld
.barrier(aco_opcode::p_memory_barrier_shared
);
6640 unreachable("Unimplemented memory barrier intrinsic");
6645 void visit_load_shared(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
6647 // TODO: implement sparse reads using ds_read2_b32 and nir_ssa_def_components_read()
6648 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
6649 Temp address
= as_vgpr(ctx
, get_ssa_temp(ctx
, instr
->src
[0].ssa
));
6650 Builder
bld(ctx
->program
, ctx
->block
);
6652 unsigned elem_size_bytes
= instr
->dest
.ssa
.bit_size
/ 8;
6653 unsigned align
= nir_intrinsic_align_mul(instr
) ? nir_intrinsic_align(instr
) : elem_size_bytes
;
6654 load_lds(ctx
, elem_size_bytes
, dst
, address
, nir_intrinsic_base(instr
), align
);
6657 void visit_store_shared(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
6659 unsigned writemask
= nir_intrinsic_write_mask(instr
);
6660 Temp data
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
6661 Temp address
= as_vgpr(ctx
, get_ssa_temp(ctx
, instr
->src
[1].ssa
));
6662 unsigned elem_size_bytes
= instr
->src
[0].ssa
->bit_size
/ 8;
6664 unsigned align
= nir_intrinsic_align_mul(instr
) ? nir_intrinsic_align(instr
) : elem_size_bytes
;
6665 store_lds(ctx
, elem_size_bytes
, data
, writemask
, address
, nir_intrinsic_base(instr
), align
);
6668 void visit_shared_atomic(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
6670 unsigned offset
= nir_intrinsic_base(instr
);
6671 Builder
bld(ctx
->program
, ctx
->block
);
6672 Operand m
= load_lds_size_m0(bld
);
6673 Temp data
= as_vgpr(ctx
, get_ssa_temp(ctx
, instr
->src
[1].ssa
));
6674 Temp address
= as_vgpr(ctx
, get_ssa_temp(ctx
, instr
->src
[0].ssa
));
6676 unsigned num_operands
= 3;
6677 aco_opcode op32
, op64
, op32_rtn
, op64_rtn
;
6678 switch(instr
->intrinsic
) {
6679 case nir_intrinsic_shared_atomic_add
:
6680 op32
= aco_opcode::ds_add_u32
;
6681 op64
= aco_opcode::ds_add_u64
;
6682 op32_rtn
= aco_opcode::ds_add_rtn_u32
;
6683 op64_rtn
= aco_opcode::ds_add_rtn_u64
;
6685 case nir_intrinsic_shared_atomic_imin
:
6686 op32
= aco_opcode::ds_min_i32
;
6687 op64
= aco_opcode::ds_min_i64
;
6688 op32_rtn
= aco_opcode::ds_min_rtn_i32
;
6689 op64_rtn
= aco_opcode::ds_min_rtn_i64
;
6691 case nir_intrinsic_shared_atomic_umin
:
6692 op32
= aco_opcode::ds_min_u32
;
6693 op64
= aco_opcode::ds_min_u64
;
6694 op32_rtn
= aco_opcode::ds_min_rtn_u32
;
6695 op64_rtn
= aco_opcode::ds_min_rtn_u64
;
6697 case nir_intrinsic_shared_atomic_imax
:
6698 op32
= aco_opcode::ds_max_i32
;
6699 op64
= aco_opcode::ds_max_i64
;
6700 op32_rtn
= aco_opcode::ds_max_rtn_i32
;
6701 op64_rtn
= aco_opcode::ds_max_rtn_i64
;
6703 case nir_intrinsic_shared_atomic_umax
:
6704 op32
= aco_opcode::ds_max_u32
;
6705 op64
= aco_opcode::ds_max_u64
;
6706 op32_rtn
= aco_opcode::ds_max_rtn_u32
;
6707 op64_rtn
= aco_opcode::ds_max_rtn_u64
;
6709 case nir_intrinsic_shared_atomic_and
:
6710 op32
= aco_opcode::ds_and_b32
;
6711 op64
= aco_opcode::ds_and_b64
;
6712 op32_rtn
= aco_opcode::ds_and_rtn_b32
;
6713 op64_rtn
= aco_opcode::ds_and_rtn_b64
;
6715 case nir_intrinsic_shared_atomic_or
:
6716 op32
= aco_opcode::ds_or_b32
;
6717 op64
= aco_opcode::ds_or_b64
;
6718 op32_rtn
= aco_opcode::ds_or_rtn_b32
;
6719 op64_rtn
= aco_opcode::ds_or_rtn_b64
;
6721 case nir_intrinsic_shared_atomic_xor
:
6722 op32
= aco_opcode::ds_xor_b32
;
6723 op64
= aco_opcode::ds_xor_b64
;
6724 op32_rtn
= aco_opcode::ds_xor_rtn_b32
;
6725 op64_rtn
= aco_opcode::ds_xor_rtn_b64
;
6727 case nir_intrinsic_shared_atomic_exchange
:
6728 op32
= aco_opcode::ds_write_b32
;
6729 op64
= aco_opcode::ds_write_b64
;
6730 op32_rtn
= aco_opcode::ds_wrxchg_rtn_b32
;
6731 op64_rtn
= aco_opcode::ds_wrxchg_rtn_b64
;
6733 case nir_intrinsic_shared_atomic_comp_swap
:
6734 op32
= aco_opcode::ds_cmpst_b32
;
6735 op64
= aco_opcode::ds_cmpst_b64
;
6736 op32_rtn
= aco_opcode::ds_cmpst_rtn_b32
;
6737 op64_rtn
= aco_opcode::ds_cmpst_rtn_b64
;
6741 unreachable("Unhandled shared atomic intrinsic");
6744 /* return the previous value if dest is ever used */
6745 bool return_previous
= false;
6746 nir_foreach_use_safe(use_src
, &instr
->dest
.ssa
) {
6747 return_previous
= true;
6750 nir_foreach_if_use_safe(use_src
, &instr
->dest
.ssa
) {
6751 return_previous
= true;
6756 if (data
.size() == 1) {
6757 assert(instr
->dest
.ssa
.bit_size
== 32);
6758 op
= return_previous
? op32_rtn
: op32
;
6760 assert(instr
->dest
.ssa
.bit_size
== 64);
6761 op
= return_previous
? op64_rtn
: op64
;
6764 if (offset
> 65535) {
6765 address
= bld
.vadd32(bld
.def(v1
), Operand(offset
), address
);
6769 aco_ptr
<DS_instruction
> ds
;
6770 ds
.reset(create_instruction
<DS_instruction
>(op
, Format::DS
, num_operands
, return_previous
? 1 : 0));
6771 ds
->operands
[0] = Operand(address
);
6772 ds
->operands
[1] = Operand(data
);
6773 if (num_operands
== 4)
6774 ds
->operands
[2] = Operand(get_ssa_temp(ctx
, instr
->src
[2].ssa
));
6775 ds
->operands
[num_operands
- 1] = m
;
6776 ds
->offset0
= offset
;
6777 if (return_previous
)
6778 ds
->definitions
[0] = Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
));
6779 ctx
->block
->instructions
.emplace_back(std::move(ds
));
6782 Temp
get_scratch_resource(isel_context
*ctx
)
6784 Builder
bld(ctx
->program
, ctx
->block
);
6785 Temp scratch_addr
= ctx
->program
->private_segment_buffer
;
6786 if (ctx
->stage
!= compute_cs
)
6787 scratch_addr
= bld
.smem(aco_opcode::s_load_dwordx2
, bld
.def(s2
), scratch_addr
, Operand(0u));
6789 uint32_t rsrc_conf
= S_008F0C_ADD_TID_ENABLE(1) |
6790 S_008F0C_INDEX_STRIDE(ctx
->program
->wave_size
== 64 ? 3 : 2);;
6792 if (ctx
->program
->chip_class
>= GFX10
) {
6793 rsrc_conf
|= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_FLOAT
) |
6794 S_008F0C_OOB_SELECT(V_008F0C_OOB_SELECT_RAW
) |
6795 S_008F0C_RESOURCE_LEVEL(1);
6796 } else if (ctx
->program
->chip_class
<= GFX7
) { /* dfmt modifies stride on GFX8/GFX9 when ADD_TID_EN=1 */
6797 rsrc_conf
|= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT
) |
6798 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32
);
6801 /* older generations need element size = 16 bytes. element size removed in GFX9 */
6802 if (ctx
->program
->chip_class
<= GFX8
)
6803 rsrc_conf
|= S_008F0C_ELEMENT_SIZE(3);
6805 return bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s4
), scratch_addr
, Operand(-1u), Operand(rsrc_conf
));
6808 void visit_load_scratch(isel_context
*ctx
, nir_intrinsic_instr
*instr
) {
6809 Builder
bld(ctx
->program
, ctx
->block
);
6810 Temp rsrc
= get_scratch_resource(ctx
);
6811 Temp offset
= as_vgpr(ctx
, get_ssa_temp(ctx
, instr
->src
[0].ssa
));
6812 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
6814 LoadEmitInfo info
= {Operand(offset
), dst
, instr
->dest
.ssa
.num_components
,
6815 instr
->dest
.ssa
.bit_size
/ 8u, rsrc
};
6816 info
.align_mul
= nir_intrinsic_align_mul(instr
);
6817 info
.align_offset
= nir_intrinsic_align_offset(instr
);
6818 info
.swizzle_component_size
= 16;
6819 info
.can_reorder
= false;
6820 info
.soffset
= ctx
->program
->scratch_offset
;
6821 emit_mubuf_load(ctx
, bld
, &info
);
6824 void visit_store_scratch(isel_context
*ctx
, nir_intrinsic_instr
*instr
) {
6825 Builder
bld(ctx
->program
, ctx
->block
);
6826 Temp rsrc
= get_scratch_resource(ctx
);
6827 Temp data
= as_vgpr(ctx
, get_ssa_temp(ctx
, instr
->src
[0].ssa
));
6828 Temp offset
= as_vgpr(ctx
, get_ssa_temp(ctx
, instr
->src
[1].ssa
));
6830 unsigned elem_size_bytes
= instr
->src
[0].ssa
->bit_size
/ 8;
6831 unsigned writemask
= widen_mask(nir_intrinsic_write_mask(instr
), elem_size_bytes
);
6833 unsigned write_count
= 0;
6834 Temp write_datas
[32];
6835 unsigned offsets
[32];
6836 split_buffer_store(ctx
, instr
, false, RegType::vgpr
, data
, writemask
,
6837 16, &write_count
, write_datas
, offsets
);
6839 for (unsigned i
= 0; i
< write_count
; i
++) {
6840 aco_opcode op
= get_buffer_store_op(false, write_datas
[i
].bytes());
6841 bld
.mubuf(op
, rsrc
, offset
, ctx
->program
->scratch_offset
, write_datas
[i
], offsets
[i
], true);
6845 void visit_load_sample_mask_in(isel_context
*ctx
, nir_intrinsic_instr
*instr
) {
6846 uint8_t log2_ps_iter_samples
;
6847 if (ctx
->program
->info
->ps
.force_persample
) {
6848 log2_ps_iter_samples
=
6849 util_logbase2(ctx
->options
->key
.fs
.num_samples
);
6851 log2_ps_iter_samples
= ctx
->options
->key
.fs
.log2_ps_iter_samples
;
6854 /* The bit pattern matches that used by fixed function fragment
6856 static const unsigned ps_iter_masks
[] = {
6857 0xffff, /* not used */
6863 assert(log2_ps_iter_samples
< ARRAY_SIZE(ps_iter_masks
));
6865 Builder
bld(ctx
->program
, ctx
->block
);
6867 Temp sample_id
= bld
.vop3(aco_opcode::v_bfe_u32
, bld
.def(v1
),
6868 get_arg(ctx
, ctx
->args
->ac
.ancillary
), Operand(8u), Operand(4u));
6869 Temp ps_iter_mask
= bld
.vop1(aco_opcode::v_mov_b32
, bld
.def(v1
), Operand(ps_iter_masks
[log2_ps_iter_samples
]));
6870 Temp mask
= bld
.vop2(aco_opcode::v_lshlrev_b32
, bld
.def(v1
), sample_id
, ps_iter_mask
);
6871 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
6872 bld
.vop2(aco_opcode::v_and_b32
, Definition(dst
), mask
, get_arg(ctx
, ctx
->args
->ac
.sample_coverage
));
6875 void visit_emit_vertex_with_counter(isel_context
*ctx
, nir_intrinsic_instr
*instr
) {
6876 Builder
bld(ctx
->program
, ctx
->block
);
6878 unsigned stream
= nir_intrinsic_stream_id(instr
);
6879 Temp next_vertex
= as_vgpr(ctx
, get_ssa_temp(ctx
, instr
->src
[0].ssa
));
6880 next_vertex
= bld
.v_mul_imm(bld
.def(v1
), next_vertex
, 4u);
6881 nir_const_value
*next_vertex_cv
= nir_src_as_const_value(instr
->src
[0]);
6884 Temp gsvs_ring
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), ctx
->program
->private_segment_buffer
, Operand(RING_GSVS_GS
* 16u));
6886 unsigned num_components
=
6887 ctx
->program
->info
->gs
.num_stream_output_components
[stream
];
6888 assert(num_components
);
6890 unsigned stride
= 4u * num_components
* ctx
->shader
->info
.gs
.vertices_out
;
6891 unsigned stream_offset
= 0;
6892 for (unsigned i
= 0; i
< stream
; i
++) {
6893 unsigned prev_stride
= 4u * ctx
->program
->info
->gs
.num_stream_output_components
[i
] * ctx
->shader
->info
.gs
.vertices_out
;
6894 stream_offset
+= prev_stride
* ctx
->program
->wave_size
;
6897 /* Limit on the stride field for <= GFX7. */
6898 assert(stride
< (1 << 14));
6900 Temp gsvs_dwords
[4];
6901 for (unsigned i
= 0; i
< 4; i
++)
6902 gsvs_dwords
[i
] = bld
.tmp(s1
);
6903 bld
.pseudo(aco_opcode::p_split_vector
,
6904 Definition(gsvs_dwords
[0]),
6905 Definition(gsvs_dwords
[1]),
6906 Definition(gsvs_dwords
[2]),
6907 Definition(gsvs_dwords
[3]),
6910 if (stream_offset
) {
6911 Temp stream_offset_tmp
= bld
.copy(bld
.def(s1
), Operand(stream_offset
));
6913 Temp carry
= bld
.tmp(s1
);
6914 gsvs_dwords
[0] = bld
.sop2(aco_opcode::s_add_u32
, bld
.def(s1
), bld
.scc(Definition(carry
)), gsvs_dwords
[0], stream_offset_tmp
);
6915 gsvs_dwords
[1] = bld
.sop2(aco_opcode::s_addc_u32
, bld
.def(s1
), bld
.def(s1
, scc
), gsvs_dwords
[1], Operand(0u), bld
.scc(carry
));
6918 gsvs_dwords
[1] = bld
.sop2(aco_opcode::s_or_b32
, bld
.def(s1
), bld
.def(s1
, scc
), gsvs_dwords
[1], Operand(S_008F04_STRIDE(stride
)));
6919 gsvs_dwords
[2] = bld
.copy(bld
.def(s1
), Operand((uint32_t)ctx
->program
->wave_size
));
6921 gsvs_ring
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s4
),
6922 gsvs_dwords
[0], gsvs_dwords
[1], gsvs_dwords
[2], gsvs_dwords
[3]);
6924 unsigned offset
= 0;
6925 for (unsigned i
= 0; i
<= VARYING_SLOT_VAR31
; i
++) {
6926 if (ctx
->program
->info
->gs
.output_streams
[i
] != stream
)
6929 for (unsigned j
= 0; j
< 4; j
++) {
6930 if (!(ctx
->program
->info
->gs
.output_usage_mask
[i
] & (1 << j
)))
6933 if (ctx
->outputs
.mask
[i
] & (1 << j
)) {
6934 Operand vaddr_offset
= next_vertex_cv
? Operand(v1
) : Operand(next_vertex
);
6935 unsigned const_offset
= (offset
+ (next_vertex_cv
? next_vertex_cv
->u32
: 0u)) * 4u;
6936 if (const_offset
>= 4096u) {
6937 if (vaddr_offset
.isUndefined())
6938 vaddr_offset
= bld
.copy(bld
.def(v1
), Operand(const_offset
/ 4096u * 4096u));
6940 vaddr_offset
= bld
.vadd32(bld
.def(v1
), Operand(const_offset
/ 4096u * 4096u), vaddr_offset
);
6941 const_offset
%= 4096u;
6944 aco_ptr
<MTBUF_instruction
> mtbuf
{create_instruction
<MTBUF_instruction
>(aco_opcode::tbuffer_store_format_x
, Format::MTBUF
, 4, 0)};
6945 mtbuf
->operands
[0] = Operand(gsvs_ring
);
6946 mtbuf
->operands
[1] = vaddr_offset
;
6947 mtbuf
->operands
[2] = Operand(get_arg(ctx
, ctx
->args
->gs2vs_offset
));
6948 mtbuf
->operands
[3] = Operand(ctx
->outputs
.temps
[i
* 4u + j
]);
6949 mtbuf
->offen
= !vaddr_offset
.isUndefined();
6950 mtbuf
->dfmt
= V_008F0C_BUF_DATA_FORMAT_32
;
6951 mtbuf
->nfmt
= V_008F0C_BUF_NUM_FORMAT_UINT
;
6952 mtbuf
->offset
= const_offset
;
6955 mtbuf
->barrier
= barrier_gs_data
;
6956 mtbuf
->can_reorder
= true;
6957 bld
.insert(std::move(mtbuf
));
6960 offset
+= ctx
->shader
->info
.gs
.vertices_out
;
6963 /* outputs for the next vertex are undefined and keeping them around can
6964 * create invalid IR with control flow */
6965 ctx
->outputs
.mask
[i
] = 0;
6968 bld
.sopp(aco_opcode::s_sendmsg
, bld
.m0(ctx
->gs_wave_id
), -1, sendmsg_gs(false, true, stream
));
6971 Temp
emit_boolean_reduce(isel_context
*ctx
, nir_op op
, unsigned cluster_size
, Temp src
)
6973 Builder
bld(ctx
->program
, ctx
->block
);
6975 if (cluster_size
== 1) {
6977 } if (op
== nir_op_iand
&& cluster_size
== 4) {
6978 //subgroupClusteredAnd(val, 4) -> ~wqm(exec & ~val)
6979 Temp tmp
= bld
.sop2(Builder::s_andn2
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), Operand(exec
, bld
.lm
), src
);
6980 return bld
.sop1(Builder::s_not
, bld
.def(bld
.lm
), bld
.def(s1
, scc
),
6981 bld
.sop1(Builder::s_wqm
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), tmp
));
6982 } else if (op
== nir_op_ior
&& cluster_size
== 4) {
6983 //subgroupClusteredOr(val, 4) -> wqm(val & exec)
6984 return bld
.sop1(Builder::s_wqm
, bld
.def(bld
.lm
), bld
.def(s1
, scc
),
6985 bld
.sop2(Builder::s_and
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), src
, Operand(exec
, bld
.lm
)));
6986 } else if (op
== nir_op_iand
&& cluster_size
== ctx
->program
->wave_size
) {
6987 //subgroupAnd(val) -> (exec & ~val) == 0
6988 Temp tmp
= bld
.sop2(Builder::s_andn2
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), Operand(exec
, bld
.lm
), src
).def(1).getTemp();
6989 Temp cond
= bool_to_vector_condition(ctx
, emit_wqm(ctx
, tmp
));
6990 return bld
.sop1(Builder::s_not
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), cond
);
6991 } else if (op
== nir_op_ior
&& cluster_size
== ctx
->program
->wave_size
) {
6992 //subgroupOr(val) -> (val & exec) != 0
6993 Temp tmp
= bld
.sop2(Builder::s_and
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), src
, Operand(exec
, bld
.lm
)).def(1).getTemp();
6994 return bool_to_vector_condition(ctx
, tmp
);
6995 } else if (op
== nir_op_ixor
&& cluster_size
== ctx
->program
->wave_size
) {
6996 //subgroupXor(val) -> s_bcnt1_i32_b64(val & exec) & 1
6997 Temp tmp
= bld
.sop2(Builder::s_and
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), src
, Operand(exec
, bld
.lm
));
6998 tmp
= bld
.sop1(Builder::s_bcnt1_i32
, bld
.def(s1
), bld
.def(s1
, scc
), tmp
);
6999 tmp
= bld
.sop2(aco_opcode::s_and_b32
, bld
.def(s1
), bld
.def(s1
, scc
), tmp
, Operand(1u)).def(1).getTemp();
7000 return bool_to_vector_condition(ctx
, tmp
);
7002 //subgroupClustered{And,Or,Xor}(val, n) ->
7003 //lane_id = v_mbcnt_hi_u32_b32(-1, v_mbcnt_lo_u32_b32(-1, 0)) ; just v_mbcnt_lo_u32_b32 on wave32
7004 //cluster_offset = ~(n - 1) & lane_id
7005 //cluster_mask = ((1 << n) - 1)
7006 //subgroupClusteredAnd():
7007 // return ((val | ~exec) >> cluster_offset) & cluster_mask == cluster_mask
7008 //subgroupClusteredOr():
7009 // return ((val & exec) >> cluster_offset) & cluster_mask != 0
7010 //subgroupClusteredXor():
7011 // return v_bnt_u32_b32(((val & exec) >> cluster_offset) & cluster_mask, 0) & 1 != 0
7012 Temp lane_id
= emit_mbcnt(ctx
, bld
.def(v1
));
7013 Temp cluster_offset
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(~uint32_t(cluster_size
- 1)), lane_id
);
7016 if (op
== nir_op_iand
)
7017 tmp
= bld
.sop2(Builder::s_orn2
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), src
, Operand(exec
, bld
.lm
));
7019 tmp
= bld
.sop2(Builder::s_and
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), src
, Operand(exec
, bld
.lm
));
7021 uint32_t cluster_mask
= cluster_size
== 32 ? -1 : (1u << cluster_size
) - 1u;
7023 if (ctx
->program
->chip_class
<= GFX7
)
7024 tmp
= bld
.vop3(aco_opcode::v_lshr_b64
, bld
.def(v2
), tmp
, cluster_offset
);
7025 else if (ctx
->program
->wave_size
== 64)
7026 tmp
= bld
.vop3(aco_opcode::v_lshrrev_b64
, bld
.def(v2
), cluster_offset
, tmp
);
7028 tmp
= bld
.vop2_e64(aco_opcode::v_lshrrev_b32
, bld
.def(v1
), cluster_offset
, tmp
);
7029 tmp
= emit_extract_vector(ctx
, tmp
, 0, v1
);
7030 if (cluster_mask
!= 0xffffffff)
7031 tmp
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(cluster_mask
), tmp
);
7033 Definition cmp_def
= Definition();
7034 if (op
== nir_op_iand
) {
7035 cmp_def
= bld
.vopc(aco_opcode::v_cmp_eq_u32
, bld
.def(bld
.lm
), Operand(cluster_mask
), tmp
).def(0);
7036 } else if (op
== nir_op_ior
) {
7037 cmp_def
= bld
.vopc(aco_opcode::v_cmp_lg_u32
, bld
.def(bld
.lm
), Operand(0u), tmp
).def(0);
7038 } else if (op
== nir_op_ixor
) {
7039 tmp
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(1u),
7040 bld
.vop3(aco_opcode::v_bcnt_u32_b32
, bld
.def(v1
), tmp
, Operand(0u)));
7041 cmp_def
= bld
.vopc(aco_opcode::v_cmp_lg_u32
, bld
.def(bld
.lm
), Operand(0u), tmp
).def(0);
7043 cmp_def
.setHint(vcc
);
7044 return cmp_def
.getTemp();
7048 Temp
emit_boolean_exclusive_scan(isel_context
*ctx
, nir_op op
, Temp src
)
7050 Builder
bld(ctx
->program
, ctx
->block
);
7052 //subgroupExclusiveAnd(val) -> mbcnt(exec & ~val) == 0
7053 //subgroupExclusiveOr(val) -> mbcnt(val & exec) != 0
7054 //subgroupExclusiveXor(val) -> mbcnt(val & exec) & 1 != 0
7056 if (op
== nir_op_iand
)
7057 tmp
= bld
.sop2(Builder::s_andn2
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), Operand(exec
, bld
.lm
), src
);
7059 tmp
= bld
.sop2(Builder::s_and
, bld
.def(s2
), bld
.def(s1
, scc
), src
, Operand(exec
, bld
.lm
));
7061 Builder::Result lohi
= bld
.pseudo(aco_opcode::p_split_vector
, bld
.def(s1
), bld
.def(s1
), tmp
);
7062 Temp lo
= lohi
.def(0).getTemp();
7063 Temp hi
= lohi
.def(1).getTemp();
7064 Temp mbcnt
= emit_mbcnt(ctx
, bld
.def(v1
), Operand(lo
), Operand(hi
));
7066 Definition cmp_def
= Definition();
7067 if (op
== nir_op_iand
)
7068 cmp_def
= bld
.vopc(aco_opcode::v_cmp_eq_u32
, bld
.def(bld
.lm
), Operand(0u), mbcnt
).def(0);
7069 else if (op
== nir_op_ior
)
7070 cmp_def
= bld
.vopc(aco_opcode::v_cmp_lg_u32
, bld
.def(bld
.lm
), Operand(0u), mbcnt
).def(0);
7071 else if (op
== nir_op_ixor
)
7072 cmp_def
= bld
.vopc(aco_opcode::v_cmp_lg_u32
, bld
.def(bld
.lm
), Operand(0u),
7073 bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(1u), mbcnt
)).def(0);
7074 cmp_def
.setHint(vcc
);
7075 return cmp_def
.getTemp();
7078 Temp
emit_boolean_inclusive_scan(isel_context
*ctx
, nir_op op
, Temp src
)
7080 Builder
bld(ctx
->program
, ctx
->block
);
7082 //subgroupInclusiveAnd(val) -> subgroupExclusiveAnd(val) && val
7083 //subgroupInclusiveOr(val) -> subgroupExclusiveOr(val) || val
7084 //subgroupInclusiveXor(val) -> subgroupExclusiveXor(val) ^^ val
7085 Temp tmp
= emit_boolean_exclusive_scan(ctx
, op
, src
);
7086 if (op
== nir_op_iand
)
7087 return bld
.sop2(Builder::s_and
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), tmp
, src
);
7088 else if (op
== nir_op_ior
)
7089 return bld
.sop2(Builder::s_or
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), tmp
, src
);
7090 else if (op
== nir_op_ixor
)
7091 return bld
.sop2(Builder::s_xor
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), tmp
, src
);
7097 void emit_uniform_subgroup(isel_context
*ctx
, nir_intrinsic_instr
*instr
, Temp src
)
7099 Builder
bld(ctx
->program
, ctx
->block
);
7100 Definition
dst(get_ssa_temp(ctx
, &instr
->dest
.ssa
));
7101 if (src
.regClass().type() == RegType::vgpr
) {
7102 bld
.pseudo(aco_opcode::p_as_uniform
, dst
, src
);
7103 } else if (src
.regClass() == s1
) {
7104 bld
.sop1(aco_opcode::s_mov_b32
, dst
, src
);
7105 } else if (src
.regClass() == s2
) {
7106 bld
.sop1(aco_opcode::s_mov_b64
, dst
, src
);
7108 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
7109 nir_print_instr(&instr
->instr
, stderr
);
7110 fprintf(stderr
, "\n");
7114 void emit_interp_center(isel_context
*ctx
, Temp dst
, Temp pos1
, Temp pos2
)
7116 Builder
bld(ctx
->program
, ctx
->block
);
7117 Temp persp_center
= get_arg(ctx
, ctx
->args
->ac
.persp_center
);
7118 Temp p1
= emit_extract_vector(ctx
, persp_center
, 0, v1
);
7119 Temp p2
= emit_extract_vector(ctx
, persp_center
, 1, v1
);
7121 Temp ddx_1
, ddx_2
, ddy_1
, ddy_2
;
7122 uint32_t dpp_ctrl0
= dpp_quad_perm(0, 0, 0, 0);
7123 uint32_t dpp_ctrl1
= dpp_quad_perm(1, 1, 1, 1);
7124 uint32_t dpp_ctrl2
= dpp_quad_perm(2, 2, 2, 2);
7127 if (ctx
->program
->chip_class
>= GFX8
) {
7128 Temp tl_1
= bld
.vop1_dpp(aco_opcode::v_mov_b32
, bld
.def(v1
), p1
, dpp_ctrl0
);
7129 ddx_1
= bld
.vop2_dpp(aco_opcode::v_sub_f32
, bld
.def(v1
), p1
, tl_1
, dpp_ctrl1
);
7130 ddy_1
= bld
.vop2_dpp(aco_opcode::v_sub_f32
, bld
.def(v1
), p1
, tl_1
, dpp_ctrl2
);
7131 Temp tl_2
= bld
.vop1_dpp(aco_opcode::v_mov_b32
, bld
.def(v1
), p2
, dpp_ctrl0
);
7132 ddx_2
= bld
.vop2_dpp(aco_opcode::v_sub_f32
, bld
.def(v1
), p2
, tl_2
, dpp_ctrl1
);
7133 ddy_2
= bld
.vop2_dpp(aco_opcode::v_sub_f32
, bld
.def(v1
), p2
, tl_2
, dpp_ctrl2
);
7135 Temp tl_1
= bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), p1
, (1 << 15) | dpp_ctrl0
);
7136 ddx_1
= bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), p1
, (1 << 15) | dpp_ctrl1
);
7137 ddx_1
= bld
.vop2(aco_opcode::v_sub_f32
, bld
.def(v1
), ddx_1
, tl_1
);
7138 ddx_2
= bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), p1
, (1 << 15) | dpp_ctrl2
);
7139 ddx_2
= bld
.vop2(aco_opcode::v_sub_f32
, bld
.def(v1
), ddx_2
, tl_1
);
7140 Temp tl_2
= bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), p2
, (1 << 15) | dpp_ctrl0
);
7141 ddy_1
= bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), p2
, (1 << 15) | dpp_ctrl1
);
7142 ddy_1
= bld
.vop2(aco_opcode::v_sub_f32
, bld
.def(v1
), ddy_1
, tl_2
);
7143 ddy_2
= bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), p2
, (1 << 15) | dpp_ctrl2
);
7144 ddy_2
= bld
.vop2(aco_opcode::v_sub_f32
, bld
.def(v1
), ddy_2
, tl_2
);
7147 /* res_k = p_k + ddx_k * pos1 + ddy_k * pos2 */
7148 Temp tmp1
= bld
.vop3(aco_opcode::v_mad_f32
, bld
.def(v1
), ddx_1
, pos1
, p1
);
7149 Temp tmp2
= bld
.vop3(aco_opcode::v_mad_f32
, bld
.def(v1
), ddx_2
, pos1
, p2
);
7150 tmp1
= bld
.vop3(aco_opcode::v_mad_f32
, bld
.def(v1
), ddy_1
, pos2
, tmp1
);
7151 tmp2
= bld
.vop3(aco_opcode::v_mad_f32
, bld
.def(v1
), ddy_2
, pos2
, tmp2
);
7152 Temp wqm1
= bld
.tmp(v1
);
7153 emit_wqm(ctx
, tmp1
, wqm1
, true);
7154 Temp wqm2
= bld
.tmp(v1
);
7155 emit_wqm(ctx
, tmp2
, wqm2
, true);
7156 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), wqm1
, wqm2
);
7160 void visit_intrinsic(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
7162 Builder
bld(ctx
->program
, ctx
->block
);
7163 switch(instr
->intrinsic
) {
7164 case nir_intrinsic_load_barycentric_sample
:
7165 case nir_intrinsic_load_barycentric_pixel
:
7166 case nir_intrinsic_load_barycentric_centroid
: {
7167 glsl_interp_mode mode
= (glsl_interp_mode
)nir_intrinsic_interp_mode(instr
);
7168 Temp bary
= Temp(0, s2
);
7170 case INTERP_MODE_SMOOTH
:
7171 case INTERP_MODE_NONE
:
7172 if (instr
->intrinsic
== nir_intrinsic_load_barycentric_pixel
)
7173 bary
= get_arg(ctx
, ctx
->args
->ac
.persp_center
);
7174 else if (instr
->intrinsic
== nir_intrinsic_load_barycentric_centroid
)
7175 bary
= ctx
->persp_centroid
;
7176 else if (instr
->intrinsic
== nir_intrinsic_load_barycentric_sample
)
7177 bary
= get_arg(ctx
, ctx
->args
->ac
.persp_sample
);
7179 case INTERP_MODE_NOPERSPECTIVE
:
7180 if (instr
->intrinsic
== nir_intrinsic_load_barycentric_pixel
)
7181 bary
= get_arg(ctx
, ctx
->args
->ac
.linear_center
);
7182 else if (instr
->intrinsic
== nir_intrinsic_load_barycentric_centroid
)
7183 bary
= ctx
->linear_centroid
;
7184 else if (instr
->intrinsic
== nir_intrinsic_load_barycentric_sample
)
7185 bary
= get_arg(ctx
, ctx
->args
->ac
.linear_sample
);
7190 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7191 Temp p1
= emit_extract_vector(ctx
, bary
, 0, v1
);
7192 Temp p2
= emit_extract_vector(ctx
, bary
, 1, v1
);
7193 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
),
7194 Operand(p1
), Operand(p2
));
7195 emit_split_vector(ctx
, dst
, 2);
7198 case nir_intrinsic_load_barycentric_model
: {
7199 Temp model
= get_arg(ctx
, ctx
->args
->ac
.pull_model
);
7201 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7202 Temp p1
= emit_extract_vector(ctx
, model
, 0, v1
);
7203 Temp p2
= emit_extract_vector(ctx
, model
, 1, v1
);
7204 Temp p3
= emit_extract_vector(ctx
, model
, 2, v1
);
7205 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
),
7206 Operand(p1
), Operand(p2
), Operand(p3
));
7207 emit_split_vector(ctx
, dst
, 3);
7210 case nir_intrinsic_load_barycentric_at_sample
: {
7211 uint32_t sample_pos_offset
= RING_PS_SAMPLE_POSITIONS
* 16;
7212 switch (ctx
->options
->key
.fs
.num_samples
) {
7213 case 2: sample_pos_offset
+= 1 << 3; break;
7214 case 4: sample_pos_offset
+= 3 << 3; break;
7215 case 8: sample_pos_offset
+= 7 << 3; break;
7219 Temp addr
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
7220 nir_const_value
* const_addr
= nir_src_as_const_value(instr
->src
[0]);
7221 Temp private_segment_buffer
= ctx
->program
->private_segment_buffer
;
7222 if (addr
.type() == RegType::sgpr
) {
7225 sample_pos_offset
+= const_addr
->u32
<< 3;
7226 offset
= Operand(sample_pos_offset
);
7227 } else if (ctx
->options
->chip_class
>= GFX9
) {
7228 offset
= bld
.sop2(aco_opcode::s_lshl3_add_u32
, bld
.def(s1
), bld
.def(s1
, scc
), addr
, Operand(sample_pos_offset
));
7230 offset
= bld
.sop2(aco_opcode::s_lshl_b32
, bld
.def(s1
), bld
.def(s1
, scc
), addr
, Operand(3u));
7231 offset
= bld
.sop2(aco_opcode::s_add_u32
, bld
.def(s1
), bld
.def(s1
, scc
), addr
, Operand(sample_pos_offset
));
7234 Operand off
= bld
.copy(bld
.def(s1
), Operand(offset
));
7235 sample_pos
= bld
.smem(aco_opcode::s_load_dwordx2
, bld
.def(s2
), private_segment_buffer
, off
);
7237 } else if (ctx
->options
->chip_class
>= GFX9
) {
7238 addr
= bld
.vop2(aco_opcode::v_lshlrev_b32
, bld
.def(v1
), Operand(3u), addr
);
7239 sample_pos
= bld
.global(aco_opcode::global_load_dwordx2
, bld
.def(v2
), addr
, private_segment_buffer
, sample_pos_offset
);
7240 } else if (ctx
->options
->chip_class
>= GFX7
) {
7241 /* addr += private_segment_buffer + sample_pos_offset */
7242 Temp tmp0
= bld
.tmp(s1
);
7243 Temp tmp1
= bld
.tmp(s1
);
7244 bld
.pseudo(aco_opcode::p_split_vector
, Definition(tmp0
), Definition(tmp1
), private_segment_buffer
);
7245 Definition scc_tmp
= bld
.def(s1
, scc
);
7246 tmp0
= bld
.sop2(aco_opcode::s_add_u32
, bld
.def(s1
), scc_tmp
, tmp0
, Operand(sample_pos_offset
));
7247 tmp1
= bld
.sop2(aco_opcode::s_addc_u32
, bld
.def(s1
), bld
.def(s1
, scc
), tmp1
, Operand(0u), bld
.scc(scc_tmp
.getTemp()));
7248 addr
= bld
.vop2(aco_opcode::v_lshlrev_b32
, bld
.def(v1
), Operand(3u), addr
);
7249 Temp pck0
= bld
.tmp(v1
);
7250 Temp carry
= bld
.vadd32(Definition(pck0
), tmp0
, addr
, true).def(1).getTemp();
7251 tmp1
= as_vgpr(ctx
, tmp1
);
7252 Temp pck1
= bld
.vop2_e64(aco_opcode::v_addc_co_u32
, bld
.def(v1
), bld
.hint_vcc(bld
.def(bld
.lm
)), tmp1
, Operand(0u), carry
);
7253 addr
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), pck0
, pck1
);
7255 /* sample_pos = flat_load_dwordx2 addr */
7256 sample_pos
= bld
.flat(aco_opcode::flat_load_dwordx2
, bld
.def(v2
), addr
, Operand(s1
));
7258 assert(ctx
->options
->chip_class
== GFX6
);
7260 uint32_t rsrc_conf
= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT
) |
7261 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32
);
7262 Temp rsrc
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s4
), private_segment_buffer
, Operand(0u), Operand(rsrc_conf
));
7264 addr
= bld
.vop2(aco_opcode::v_lshlrev_b32
, bld
.def(v1
), Operand(3u), addr
);
7265 addr
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), addr
, Operand(0u));
7267 sample_pos
= bld
.tmp(v2
);
7269 aco_ptr
<MUBUF_instruction
> load
{create_instruction
<MUBUF_instruction
>(aco_opcode::buffer_load_dwordx2
, Format::MUBUF
, 3, 1)};
7270 load
->definitions
[0] = Definition(sample_pos
);
7271 load
->operands
[0] = Operand(rsrc
);
7272 load
->operands
[1] = Operand(addr
);
7273 load
->operands
[2] = Operand(0u);
7274 load
->offset
= sample_pos_offset
;
7276 load
->addr64
= true;
7279 load
->disable_wqm
= false;
7280 load
->barrier
= barrier_none
;
7281 load
->can_reorder
= true;
7282 ctx
->block
->instructions
.emplace_back(std::move(load
));
7285 /* sample_pos -= 0.5 */
7286 Temp pos1
= bld
.tmp(RegClass(sample_pos
.type(), 1));
7287 Temp pos2
= bld
.tmp(RegClass(sample_pos
.type(), 1));
7288 bld
.pseudo(aco_opcode::p_split_vector
, Definition(pos1
), Definition(pos2
), sample_pos
);
7289 pos1
= bld
.vop2_e64(aco_opcode::v_sub_f32
, bld
.def(v1
), pos1
, Operand(0x3f000000u
));
7290 pos2
= bld
.vop2_e64(aco_opcode::v_sub_f32
, bld
.def(v1
), pos2
, Operand(0x3f000000u
));
7292 emit_interp_center(ctx
, get_ssa_temp(ctx
, &instr
->dest
.ssa
), pos1
, pos2
);
7295 case nir_intrinsic_load_barycentric_at_offset
: {
7296 Temp offset
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
7297 RegClass rc
= RegClass(offset
.type(), 1);
7298 Temp pos1
= bld
.tmp(rc
), pos2
= bld
.tmp(rc
);
7299 bld
.pseudo(aco_opcode::p_split_vector
, Definition(pos1
), Definition(pos2
), offset
);
7300 emit_interp_center(ctx
, get_ssa_temp(ctx
, &instr
->dest
.ssa
), pos1
, pos2
);
7303 case nir_intrinsic_load_front_face
: {
7304 bld
.vopc(aco_opcode::v_cmp_lg_u32
, Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
)),
7305 Operand(0u), get_arg(ctx
, ctx
->args
->ac
.front_face
)).def(0).setHint(vcc
);
7308 case nir_intrinsic_load_view_index
: {
7309 if (ctx
->stage
& (sw_vs
| sw_gs
| sw_tcs
| sw_tes
)) {
7310 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7311 bld
.copy(Definition(dst
), Operand(get_arg(ctx
, ctx
->args
->ac
.view_index
)));
7317 case nir_intrinsic_load_layer_id
: {
7318 unsigned idx
= nir_intrinsic_base(instr
);
7319 bld
.vintrp(aco_opcode::v_interp_mov_f32
, Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
)),
7320 Operand(2u), bld
.m0(get_arg(ctx
, ctx
->args
->ac
.prim_mask
)), idx
, 0);
7323 case nir_intrinsic_load_frag_coord
: {
7324 emit_load_frag_coord(ctx
, get_ssa_temp(ctx
, &instr
->dest
.ssa
), 4);
7327 case nir_intrinsic_load_sample_pos
: {
7328 Temp posx
= get_arg(ctx
, ctx
->args
->ac
.frag_pos
[0]);
7329 Temp posy
= get_arg(ctx
, ctx
->args
->ac
.frag_pos
[1]);
7330 bld
.pseudo(aco_opcode::p_create_vector
, Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
)),
7331 posx
.id() ? bld
.vop1(aco_opcode::v_fract_f32
, bld
.def(v1
), posx
) : Operand(0u),
7332 posy
.id() ? bld
.vop1(aco_opcode::v_fract_f32
, bld
.def(v1
), posy
) : Operand(0u));
7335 case nir_intrinsic_load_tess_coord
:
7336 visit_load_tess_coord(ctx
, instr
);
7338 case nir_intrinsic_load_interpolated_input
:
7339 visit_load_interpolated_input(ctx
, instr
);
7341 case nir_intrinsic_store_output
:
7342 visit_store_output(ctx
, instr
);
7344 case nir_intrinsic_load_input
:
7345 case nir_intrinsic_load_input_vertex
:
7346 visit_load_input(ctx
, instr
);
7348 case nir_intrinsic_load_output
:
7349 visit_load_output(ctx
, instr
);
7351 case nir_intrinsic_load_per_vertex_input
:
7352 visit_load_per_vertex_input(ctx
, instr
);
7354 case nir_intrinsic_load_per_vertex_output
:
7355 visit_load_per_vertex_output(ctx
, instr
);
7357 case nir_intrinsic_store_per_vertex_output
:
7358 visit_store_per_vertex_output(ctx
, instr
);
7360 case nir_intrinsic_load_ubo
:
7361 visit_load_ubo(ctx
, instr
);
7363 case nir_intrinsic_load_push_constant
:
7364 visit_load_push_constant(ctx
, instr
);
7366 case nir_intrinsic_load_constant
:
7367 visit_load_constant(ctx
, instr
);
7369 case nir_intrinsic_vulkan_resource_index
:
7370 visit_load_resource(ctx
, instr
);
7372 case nir_intrinsic_discard
:
7373 visit_discard(ctx
, instr
);
7375 case nir_intrinsic_discard_if
:
7376 visit_discard_if(ctx
, instr
);
7378 case nir_intrinsic_load_shared
:
7379 visit_load_shared(ctx
, instr
);
7381 case nir_intrinsic_store_shared
:
7382 visit_store_shared(ctx
, instr
);
7384 case nir_intrinsic_shared_atomic_add
:
7385 case nir_intrinsic_shared_atomic_imin
:
7386 case nir_intrinsic_shared_atomic_umin
:
7387 case nir_intrinsic_shared_atomic_imax
:
7388 case nir_intrinsic_shared_atomic_umax
:
7389 case nir_intrinsic_shared_atomic_and
:
7390 case nir_intrinsic_shared_atomic_or
:
7391 case nir_intrinsic_shared_atomic_xor
:
7392 case nir_intrinsic_shared_atomic_exchange
:
7393 case nir_intrinsic_shared_atomic_comp_swap
:
7394 visit_shared_atomic(ctx
, instr
);
7396 case nir_intrinsic_image_deref_load
:
7397 visit_image_load(ctx
, instr
);
7399 case nir_intrinsic_image_deref_store
:
7400 visit_image_store(ctx
, instr
);
7402 case nir_intrinsic_image_deref_atomic_add
:
7403 case nir_intrinsic_image_deref_atomic_umin
:
7404 case nir_intrinsic_image_deref_atomic_imin
:
7405 case nir_intrinsic_image_deref_atomic_umax
:
7406 case nir_intrinsic_image_deref_atomic_imax
:
7407 case nir_intrinsic_image_deref_atomic_and
:
7408 case nir_intrinsic_image_deref_atomic_or
:
7409 case nir_intrinsic_image_deref_atomic_xor
:
7410 case nir_intrinsic_image_deref_atomic_exchange
:
7411 case nir_intrinsic_image_deref_atomic_comp_swap
:
7412 visit_image_atomic(ctx
, instr
);
7414 case nir_intrinsic_image_deref_size
:
7415 visit_image_size(ctx
, instr
);
7417 case nir_intrinsic_load_ssbo
:
7418 visit_load_ssbo(ctx
, instr
);
7420 case nir_intrinsic_store_ssbo
:
7421 visit_store_ssbo(ctx
, instr
);
7423 case nir_intrinsic_load_global
:
7424 visit_load_global(ctx
, instr
);
7426 case nir_intrinsic_store_global
:
7427 visit_store_global(ctx
, instr
);
7429 case nir_intrinsic_global_atomic_add
:
7430 case nir_intrinsic_global_atomic_imin
:
7431 case nir_intrinsic_global_atomic_umin
:
7432 case nir_intrinsic_global_atomic_imax
:
7433 case nir_intrinsic_global_atomic_umax
:
7434 case nir_intrinsic_global_atomic_and
:
7435 case nir_intrinsic_global_atomic_or
:
7436 case nir_intrinsic_global_atomic_xor
:
7437 case nir_intrinsic_global_atomic_exchange
:
7438 case nir_intrinsic_global_atomic_comp_swap
:
7439 visit_global_atomic(ctx
, instr
);
7441 case nir_intrinsic_ssbo_atomic_add
:
7442 case nir_intrinsic_ssbo_atomic_imin
:
7443 case nir_intrinsic_ssbo_atomic_umin
:
7444 case nir_intrinsic_ssbo_atomic_imax
:
7445 case nir_intrinsic_ssbo_atomic_umax
:
7446 case nir_intrinsic_ssbo_atomic_and
:
7447 case nir_intrinsic_ssbo_atomic_or
:
7448 case nir_intrinsic_ssbo_atomic_xor
:
7449 case nir_intrinsic_ssbo_atomic_exchange
:
7450 case nir_intrinsic_ssbo_atomic_comp_swap
:
7451 visit_atomic_ssbo(ctx
, instr
);
7453 case nir_intrinsic_load_scratch
:
7454 visit_load_scratch(ctx
, instr
);
7456 case nir_intrinsic_store_scratch
:
7457 visit_store_scratch(ctx
, instr
);
7459 case nir_intrinsic_get_buffer_size
:
7460 visit_get_buffer_size(ctx
, instr
);
7462 case nir_intrinsic_control_barrier
: {
7463 if (ctx
->program
->chip_class
== GFX6
&& ctx
->shader
->info
.stage
== MESA_SHADER_TESS_CTRL
) {
7464 /* GFX6 only (thanks to a hw bug workaround):
7465 * The real barrier instruction isn’t needed, because an entire patch
7466 * always fits into a single wave.
7471 if (ctx
->program
->workgroup_size
> ctx
->program
->wave_size
)
7472 bld
.sopp(aco_opcode::s_barrier
);
7476 case nir_intrinsic_memory_barrier_tcs_patch
:
7477 case nir_intrinsic_group_memory_barrier
:
7478 case nir_intrinsic_memory_barrier
:
7479 case nir_intrinsic_memory_barrier_buffer
:
7480 case nir_intrinsic_memory_barrier_image
:
7481 case nir_intrinsic_memory_barrier_shared
:
7482 emit_memory_barrier(ctx
, instr
);
7484 case nir_intrinsic_load_num_work_groups
: {
7485 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7486 bld
.copy(Definition(dst
), Operand(get_arg(ctx
, ctx
->args
->ac
.num_work_groups
)));
7487 emit_split_vector(ctx
, dst
, 3);
7490 case nir_intrinsic_load_local_invocation_id
: {
7491 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7492 bld
.copy(Definition(dst
), Operand(get_arg(ctx
, ctx
->args
->ac
.local_invocation_ids
)));
7493 emit_split_vector(ctx
, dst
, 3);
7496 case nir_intrinsic_load_work_group_id
: {
7497 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7498 struct ac_arg
*args
= ctx
->args
->ac
.workgroup_ids
;
7499 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
),
7500 args
[0].used
? Operand(get_arg(ctx
, args
[0])) : Operand(0u),
7501 args
[1].used
? Operand(get_arg(ctx
, args
[1])) : Operand(0u),
7502 args
[2].used
? Operand(get_arg(ctx
, args
[2])) : Operand(0u));
7503 emit_split_vector(ctx
, dst
, 3);
7506 case nir_intrinsic_load_local_invocation_index
: {
7507 Temp id
= emit_mbcnt(ctx
, bld
.def(v1
));
7509 /* The tg_size bits [6:11] contain the subgroup id,
7510 * we need this multiplied by the wave size, and then OR the thread id to it.
7512 if (ctx
->program
->wave_size
== 64) {
7513 /* After the s_and the bits are already multiplied by 64 (left shifted by 6) so we can just feed that to v_or */
7514 Temp tg_num
= bld
.sop2(aco_opcode::s_and_b32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(0xfc0u
),
7515 get_arg(ctx
, ctx
->args
->ac
.tg_size
));
7516 bld
.vop2(aco_opcode::v_or_b32
, Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
)), tg_num
, id
);
7518 /* Extract the bit field and multiply the result by 32 (left shift by 5), then do the OR */
7519 Temp tg_num
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
),
7520 get_arg(ctx
, ctx
->args
->ac
.tg_size
), Operand(0x6u
| (0x6u
<< 16)));
7521 bld
.vop3(aco_opcode::v_lshl_or_b32
, Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
)), tg_num
, Operand(0x5u
), id
);
7525 case nir_intrinsic_load_subgroup_id
: {
7526 if (ctx
->stage
== compute_cs
) {
7527 bld
.sop2(aco_opcode::s_bfe_u32
, Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
)), bld
.def(s1
, scc
),
7528 get_arg(ctx
, ctx
->args
->ac
.tg_size
), Operand(0x6u
| (0x6u
<< 16)));
7530 bld
.sop1(aco_opcode::s_mov_b32
, Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
)), Operand(0x0u
));
7534 case nir_intrinsic_load_subgroup_invocation
: {
7535 emit_mbcnt(ctx
, Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
)));
7538 case nir_intrinsic_load_num_subgroups
: {
7539 if (ctx
->stage
== compute_cs
)
7540 bld
.sop2(aco_opcode::s_and_b32
, Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
)), bld
.def(s1
, scc
), Operand(0x3fu
),
7541 get_arg(ctx
, ctx
->args
->ac
.tg_size
));
7543 bld
.sop1(aco_opcode::s_mov_b32
, Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
)), Operand(0x1u
));
7546 case nir_intrinsic_ballot
: {
7547 Temp src
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
7548 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7549 Definition tmp
= bld
.def(dst
.regClass());
7550 Definition lanemask_tmp
= dst
.size() == bld
.lm
.size() ? tmp
: bld
.def(src
.regClass());
7551 if (instr
->src
[0].ssa
->bit_size
== 1) {
7552 assert(src
.regClass() == bld
.lm
);
7553 bld
.sop2(Builder::s_and
, lanemask_tmp
, bld
.def(s1
, scc
), Operand(exec
, bld
.lm
), src
);
7554 } else if (instr
->src
[0].ssa
->bit_size
== 32 && src
.regClass() == v1
) {
7555 bld
.vopc(aco_opcode::v_cmp_lg_u32
, lanemask_tmp
, Operand(0u), src
);
7556 } else if (instr
->src
[0].ssa
->bit_size
== 64 && src
.regClass() == v2
) {
7557 bld
.vopc(aco_opcode::v_cmp_lg_u64
, lanemask_tmp
, Operand(0u), src
);
7559 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
7560 nir_print_instr(&instr
->instr
, stderr
);
7561 fprintf(stderr
, "\n");
7563 if (dst
.size() != bld
.lm
.size()) {
7564 /* Wave32 with ballot size set to 64 */
7565 bld
.pseudo(aco_opcode::p_create_vector
, Definition(tmp
), lanemask_tmp
.getTemp(), Operand(0u));
7567 emit_wqm(ctx
, tmp
.getTemp(), dst
);
7570 case nir_intrinsic_shuffle
:
7571 case nir_intrinsic_read_invocation
: {
7572 Temp src
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
7573 if (!nir_src_is_divergent(instr
->src
[0])) {
7574 emit_uniform_subgroup(ctx
, instr
, src
);
7576 Temp tid
= get_ssa_temp(ctx
, instr
->src
[1].ssa
);
7577 if (instr
->intrinsic
== nir_intrinsic_read_invocation
|| !nir_src_is_divergent(instr
->src
[1]))
7578 tid
= bld
.as_uniform(tid
);
7579 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7580 if (src
.regClass() == v1b
|| src
.regClass() == v2b
) {
7581 Temp tmp
= bld
.tmp(v1
);
7582 tmp
= emit_wqm(ctx
, emit_bpermute(ctx
, bld
, tid
, src
), tmp
);
7583 if (dst
.type() == RegType::vgpr
)
7584 bld
.pseudo(aco_opcode::p_split_vector
, Definition(dst
), bld
.def(src
.regClass() == v1b
? v3b
: v2b
), tmp
);
7586 bld
.pseudo(aco_opcode::p_as_uniform
, Definition(dst
), tmp
);
7587 } else if (src
.regClass() == v1
) {
7588 emit_wqm(ctx
, emit_bpermute(ctx
, bld
, tid
, src
), dst
);
7589 } else if (src
.regClass() == v2
) {
7590 Temp lo
= bld
.tmp(v1
), hi
= bld
.tmp(v1
);
7591 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lo
), Definition(hi
), src
);
7592 lo
= emit_wqm(ctx
, emit_bpermute(ctx
, bld
, tid
, lo
));
7593 hi
= emit_wqm(ctx
, emit_bpermute(ctx
, bld
, tid
, hi
));
7594 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lo
, hi
);
7595 emit_split_vector(ctx
, dst
, 2);
7596 } else if (instr
->dest
.ssa
.bit_size
== 1 && tid
.regClass() == s1
) {
7597 assert(src
.regClass() == bld
.lm
);
7598 Temp tmp
= bld
.sopc(Builder::s_bitcmp1
, bld
.def(s1
, scc
), src
, tid
);
7599 bool_to_vector_condition(ctx
, emit_wqm(ctx
, tmp
), dst
);
7600 } else if (instr
->dest
.ssa
.bit_size
== 1 && tid
.regClass() == v1
) {
7601 assert(src
.regClass() == bld
.lm
);
7603 if (ctx
->program
->chip_class
<= GFX7
)
7604 tmp
= bld
.vop3(aco_opcode::v_lshr_b64
, bld
.def(v2
), src
, tid
);
7605 else if (ctx
->program
->wave_size
== 64)
7606 tmp
= bld
.vop3(aco_opcode::v_lshrrev_b64
, bld
.def(v2
), tid
, src
);
7608 tmp
= bld
.vop2_e64(aco_opcode::v_lshrrev_b32
, bld
.def(v1
), tid
, src
);
7609 tmp
= emit_extract_vector(ctx
, tmp
, 0, v1
);
7610 tmp
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(1u), tmp
);
7611 emit_wqm(ctx
, bld
.vopc(aco_opcode::v_cmp_lg_u32
, bld
.def(bld
.lm
), Operand(0u), tmp
), dst
);
7613 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
7614 nir_print_instr(&instr
->instr
, stderr
);
7615 fprintf(stderr
, "\n");
7620 case nir_intrinsic_load_sample_id
: {
7621 bld
.vop3(aco_opcode::v_bfe_u32
, Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
)),
7622 get_arg(ctx
, ctx
->args
->ac
.ancillary
), Operand(8u), Operand(4u));
7625 case nir_intrinsic_load_sample_mask_in
: {
7626 visit_load_sample_mask_in(ctx
, instr
);
7629 case nir_intrinsic_read_first_invocation
: {
7630 Temp src
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
7631 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7632 if (src
.regClass() == v1b
|| src
.regClass() == v2b
|| src
.regClass() == v1
) {
7634 bld
.vop1(aco_opcode::v_readfirstlane_b32
, bld
.def(s1
), src
),
7636 } else if (src
.regClass() == v2
) {
7637 Temp lo
= bld
.tmp(v1
), hi
= bld
.tmp(v1
);
7638 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lo
), Definition(hi
), src
);
7639 lo
= emit_wqm(ctx
, bld
.vop1(aco_opcode::v_readfirstlane_b32
, bld
.def(s1
), lo
));
7640 hi
= emit_wqm(ctx
, bld
.vop1(aco_opcode::v_readfirstlane_b32
, bld
.def(s1
), hi
));
7641 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lo
, hi
);
7642 emit_split_vector(ctx
, dst
, 2);
7643 } else if (instr
->dest
.ssa
.bit_size
== 1) {
7644 assert(src
.regClass() == bld
.lm
);
7645 Temp tmp
= bld
.sopc(Builder::s_bitcmp1
, bld
.def(s1
, scc
), src
,
7646 bld
.sop1(Builder::s_ff1_i32
, bld
.def(s1
), Operand(exec
, bld
.lm
)));
7647 bool_to_vector_condition(ctx
, emit_wqm(ctx
, tmp
), dst
);
7648 } else if (src
.regClass() == s1
) {
7649 bld
.sop1(aco_opcode::s_mov_b32
, Definition(dst
), src
);
7650 } else if (src
.regClass() == s2
) {
7651 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), src
);
7653 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
7654 nir_print_instr(&instr
->instr
, stderr
);
7655 fprintf(stderr
, "\n");
7659 case nir_intrinsic_vote_all
: {
7660 Temp src
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
7661 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7662 assert(src
.regClass() == bld
.lm
);
7663 assert(dst
.regClass() == bld
.lm
);
7665 Temp tmp
= bld
.sop2(Builder::s_andn2
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), Operand(exec
, bld
.lm
), src
).def(1).getTemp();
7666 Temp cond
= bool_to_vector_condition(ctx
, emit_wqm(ctx
, tmp
));
7667 bld
.sop1(Builder::s_not
, Definition(dst
), bld
.def(s1
, scc
), cond
);
7670 case nir_intrinsic_vote_any
: {
7671 Temp src
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
7672 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7673 assert(src
.regClass() == bld
.lm
);
7674 assert(dst
.regClass() == bld
.lm
);
7676 Temp tmp
= bool_to_scalar_condition(ctx
, src
);
7677 bool_to_vector_condition(ctx
, emit_wqm(ctx
, tmp
), dst
);
7680 case nir_intrinsic_reduce
:
7681 case nir_intrinsic_inclusive_scan
:
7682 case nir_intrinsic_exclusive_scan
: {
7683 Temp src
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
7684 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7685 nir_op op
= (nir_op
) nir_intrinsic_reduction_op(instr
);
7686 unsigned cluster_size
= instr
->intrinsic
== nir_intrinsic_reduce
?
7687 nir_intrinsic_cluster_size(instr
) : 0;
7688 cluster_size
= util_next_power_of_two(MIN2(cluster_size
? cluster_size
: ctx
->program
->wave_size
, ctx
->program
->wave_size
));
7690 if (!nir_src_is_divergent(instr
->src
[0]) && (op
== nir_op_ior
|| op
== nir_op_iand
)) {
7691 emit_uniform_subgroup(ctx
, instr
, src
);
7692 } else if (instr
->dest
.ssa
.bit_size
== 1) {
7693 if (op
== nir_op_imul
|| op
== nir_op_umin
|| op
== nir_op_imin
)
7695 else if (op
== nir_op_iadd
)
7697 else if (op
== nir_op_umax
|| op
== nir_op_imax
)
7699 assert(op
== nir_op_iand
|| op
== nir_op_ior
|| op
== nir_op_ixor
);
7701 switch (instr
->intrinsic
) {
7702 case nir_intrinsic_reduce
:
7703 emit_wqm(ctx
, emit_boolean_reduce(ctx
, op
, cluster_size
, src
), dst
);
7705 case nir_intrinsic_exclusive_scan
:
7706 emit_wqm(ctx
, emit_boolean_exclusive_scan(ctx
, op
, src
), dst
);
7708 case nir_intrinsic_inclusive_scan
:
7709 emit_wqm(ctx
, emit_boolean_inclusive_scan(ctx
, op
, src
), dst
);
7714 } else if (cluster_size
== 1) {
7715 bld
.copy(Definition(dst
), src
);
7717 unsigned bit_size
= instr
->src
[0].ssa
->bit_size
;
7719 src
= emit_extract_vector(ctx
, src
, 0, RegClass::get(RegType::vgpr
, bit_size
/ 8));
7723 #define CASEI(name) case nir_op_##name: reduce_op = (bit_size == 32) ? name##32 : (bit_size == 16) ? name##16 : (bit_size == 8) ? name##8 : name##64; break;
7724 #define CASEF(name) case nir_op_##name: reduce_op = (bit_size == 32) ? name##32 : (bit_size == 16) ? name##16 : name##64; break;
7739 unreachable("unknown reduction op");
7745 switch (instr
->intrinsic
) {
7746 case nir_intrinsic_reduce
: aco_op
= aco_opcode::p_reduce
; break;
7747 case nir_intrinsic_inclusive_scan
: aco_op
= aco_opcode::p_inclusive_scan
; break;
7748 case nir_intrinsic_exclusive_scan
: aco_op
= aco_opcode::p_exclusive_scan
; break;
7750 unreachable("unknown reduce intrinsic");
7753 aco_ptr
<Pseudo_reduction_instruction
> reduce
{create_instruction
<Pseudo_reduction_instruction
>(aco_op
, Format::PSEUDO_REDUCTION
, 3, 5)};
7754 reduce
->operands
[0] = Operand(src
);
7755 // filled in by aco_reduce_assign.cpp, used internally as part of the
7757 assert(dst
.size() == 1 || dst
.size() == 2);
7758 reduce
->operands
[1] = Operand(RegClass(RegType::vgpr
, dst
.size()).as_linear());
7759 reduce
->operands
[2] = Operand(v1
.as_linear());
7761 Temp tmp_dst
= bld
.tmp(dst
.regClass());
7762 reduce
->definitions
[0] = Definition(tmp_dst
);
7763 reduce
->definitions
[1] = bld
.def(ctx
->program
->lane_mask
); // used internally
7764 reduce
->definitions
[2] = Definition();
7765 reduce
->definitions
[3] = Definition(scc
, s1
);
7766 reduce
->definitions
[4] = Definition();
7767 reduce
->reduce_op
= reduce_op
;
7768 reduce
->cluster_size
= cluster_size
;
7769 ctx
->block
->instructions
.emplace_back(std::move(reduce
));
7771 emit_wqm(ctx
, tmp_dst
, dst
);
7775 case nir_intrinsic_quad_broadcast
: {
7776 Temp src
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
7777 if (!nir_dest_is_divergent(instr
->dest
)) {
7778 emit_uniform_subgroup(ctx
, instr
, src
);
7780 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7781 unsigned lane
= nir_src_as_const_value(instr
->src
[1])->u32
;
7782 uint32_t dpp_ctrl
= dpp_quad_perm(lane
, lane
, lane
, lane
);
7784 if (instr
->dest
.ssa
.bit_size
== 1) {
7785 assert(src
.regClass() == bld
.lm
);
7786 assert(dst
.regClass() == bld
.lm
);
7787 uint32_t half_mask
= 0x11111111u
<< lane
;
7788 Temp mask_tmp
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s2
), Operand(half_mask
), Operand(half_mask
));
7789 Temp tmp
= bld
.tmp(bld
.lm
);
7790 bld
.sop1(Builder::s_wqm
, Definition(tmp
),
7791 bld
.sop2(Builder::s_and
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), mask_tmp
,
7792 bld
.sop2(Builder::s_and
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), src
, Operand(exec
, bld
.lm
))));
7793 emit_wqm(ctx
, tmp
, dst
);
7794 } else if (instr
->dest
.ssa
.bit_size
== 8) {
7795 Temp tmp
= bld
.tmp(v1
);
7796 if (ctx
->program
->chip_class
>= GFX8
)
7797 emit_wqm(ctx
, bld
.vop1_dpp(aco_opcode::v_mov_b32
, bld
.def(v1
), src
, dpp_ctrl
), tmp
);
7799 emit_wqm(ctx
, bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), src
, (1 << 15) | dpp_ctrl
), tmp
);
7800 bld
.pseudo(aco_opcode::p_split_vector
, Definition(dst
), bld
.def(v3b
), tmp
);
7801 } else if (instr
->dest
.ssa
.bit_size
== 16) {
7802 Temp tmp
= bld
.tmp(v1
);
7803 if (ctx
->program
->chip_class
>= GFX8
)
7804 emit_wqm(ctx
, bld
.vop1_dpp(aco_opcode::v_mov_b32
, bld
.def(v1
), src
, dpp_ctrl
), tmp
);
7806 emit_wqm(ctx
, bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), src
, (1 << 15) | dpp_ctrl
), tmp
);
7807 bld
.pseudo(aco_opcode::p_split_vector
, Definition(dst
), bld
.def(v2b
), tmp
);
7808 } else if (instr
->dest
.ssa
.bit_size
== 32) {
7809 if (ctx
->program
->chip_class
>= GFX8
)
7810 emit_wqm(ctx
, bld
.vop1_dpp(aco_opcode::v_mov_b32
, bld
.def(v1
), src
, dpp_ctrl
), dst
);
7812 emit_wqm(ctx
, bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), src
, (1 << 15) | dpp_ctrl
), dst
);
7813 } else if (instr
->dest
.ssa
.bit_size
== 64) {
7814 Temp lo
= bld
.tmp(v1
), hi
= bld
.tmp(v1
);
7815 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lo
), Definition(hi
), src
);
7816 if (ctx
->program
->chip_class
>= GFX8
) {
7817 lo
= emit_wqm(ctx
, bld
.vop1_dpp(aco_opcode::v_mov_b32
, bld
.def(v1
), lo
, dpp_ctrl
));
7818 hi
= emit_wqm(ctx
, bld
.vop1_dpp(aco_opcode::v_mov_b32
, bld
.def(v1
), hi
, dpp_ctrl
));
7820 lo
= emit_wqm(ctx
, bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), lo
, (1 << 15) | dpp_ctrl
));
7821 hi
= emit_wqm(ctx
, bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), hi
, (1 << 15) | dpp_ctrl
));
7823 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lo
, hi
);
7824 emit_split_vector(ctx
, dst
, 2);
7826 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
7827 nir_print_instr(&instr
->instr
, stderr
);
7828 fprintf(stderr
, "\n");
7833 case nir_intrinsic_quad_swap_horizontal
:
7834 case nir_intrinsic_quad_swap_vertical
:
7835 case nir_intrinsic_quad_swap_diagonal
:
7836 case nir_intrinsic_quad_swizzle_amd
: {
7837 Temp src
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
7838 if (!nir_dest_is_divergent(instr
->dest
)) {
7839 emit_uniform_subgroup(ctx
, instr
, src
);
7842 uint16_t dpp_ctrl
= 0;
7843 switch (instr
->intrinsic
) {
7844 case nir_intrinsic_quad_swap_horizontal
:
7845 dpp_ctrl
= dpp_quad_perm(1, 0, 3, 2);
7847 case nir_intrinsic_quad_swap_vertical
:
7848 dpp_ctrl
= dpp_quad_perm(2, 3, 0, 1);
7850 case nir_intrinsic_quad_swap_diagonal
:
7851 dpp_ctrl
= dpp_quad_perm(3, 2, 1, 0);
7853 case nir_intrinsic_quad_swizzle_amd
:
7854 dpp_ctrl
= nir_intrinsic_swizzle_mask(instr
);
7859 if (ctx
->program
->chip_class
< GFX8
)
7860 dpp_ctrl
|= (1 << 15);
7862 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7863 if (instr
->dest
.ssa
.bit_size
== 1) {
7864 assert(src
.regClass() == bld
.lm
);
7865 src
= bld
.vop2_e64(aco_opcode::v_cndmask_b32
, bld
.def(v1
), Operand(0u), Operand((uint32_t)-1), src
);
7866 if (ctx
->program
->chip_class
>= GFX8
)
7867 src
= bld
.vop1_dpp(aco_opcode::v_mov_b32
, bld
.def(v1
), src
, dpp_ctrl
);
7869 src
= bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), src
, dpp_ctrl
);
7870 Temp tmp
= bld
.vopc(aco_opcode::v_cmp_lg_u32
, bld
.def(bld
.lm
), Operand(0u), src
);
7871 emit_wqm(ctx
, tmp
, dst
);
7872 } else if (instr
->dest
.ssa
.bit_size
== 8) {
7873 Temp tmp
= bld
.tmp(v1
);
7874 if (ctx
->program
->chip_class
>= GFX8
)
7875 emit_wqm(ctx
, bld
.vop1_dpp(aco_opcode::v_mov_b32
, bld
.def(v1
), src
, dpp_ctrl
), tmp
);
7877 emit_wqm(ctx
, bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), src
, dpp_ctrl
), tmp
);
7878 bld
.pseudo(aco_opcode::p_split_vector
, Definition(dst
), bld
.def(v3b
), tmp
);
7879 } else if (instr
->dest
.ssa
.bit_size
== 16) {
7880 Temp tmp
= bld
.tmp(v1
);
7881 if (ctx
->program
->chip_class
>= GFX8
)
7882 emit_wqm(ctx
, bld
.vop1_dpp(aco_opcode::v_mov_b32
, bld
.def(v1
), src
, dpp_ctrl
), tmp
);
7884 emit_wqm(ctx
, bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), src
, dpp_ctrl
), tmp
);
7885 bld
.pseudo(aco_opcode::p_split_vector
, Definition(dst
), bld
.def(v2b
), tmp
);
7886 } else if (instr
->dest
.ssa
.bit_size
== 32) {
7888 if (ctx
->program
->chip_class
>= GFX8
)
7889 tmp
= bld
.vop1_dpp(aco_opcode::v_mov_b32
, bld
.def(v1
), src
, dpp_ctrl
);
7891 tmp
= bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), src
, dpp_ctrl
);
7892 emit_wqm(ctx
, tmp
, dst
);
7893 } else if (instr
->dest
.ssa
.bit_size
== 64) {
7894 Temp lo
= bld
.tmp(v1
), hi
= bld
.tmp(v1
);
7895 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lo
), Definition(hi
), src
);
7896 if (ctx
->program
->chip_class
>= GFX8
) {
7897 lo
= emit_wqm(ctx
, bld
.vop1_dpp(aco_opcode::v_mov_b32
, bld
.def(v1
), lo
, dpp_ctrl
));
7898 hi
= emit_wqm(ctx
, bld
.vop1_dpp(aco_opcode::v_mov_b32
, bld
.def(v1
), hi
, dpp_ctrl
));
7900 lo
= emit_wqm(ctx
, bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), lo
, dpp_ctrl
));
7901 hi
= emit_wqm(ctx
, bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), hi
, dpp_ctrl
));
7903 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lo
, hi
);
7904 emit_split_vector(ctx
, dst
, 2);
7906 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
7907 nir_print_instr(&instr
->instr
, stderr
);
7908 fprintf(stderr
, "\n");
7912 case nir_intrinsic_masked_swizzle_amd
: {
7913 Temp src
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
7914 if (!nir_dest_is_divergent(instr
->dest
)) {
7915 emit_uniform_subgroup(ctx
, instr
, src
);
7918 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7919 uint32_t mask
= nir_intrinsic_swizzle_mask(instr
);
7920 if (dst
.regClass() == v1
) {
7922 bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), src
, mask
, 0, false),
7924 } else if (dst
.regClass() == v2
) {
7925 Temp lo
= bld
.tmp(v1
), hi
= bld
.tmp(v1
);
7926 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lo
), Definition(hi
), src
);
7927 lo
= emit_wqm(ctx
, bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), lo
, mask
, 0, false));
7928 hi
= emit_wqm(ctx
, bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), hi
, mask
, 0, false));
7929 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lo
, hi
);
7930 emit_split_vector(ctx
, dst
, 2);
7932 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
7933 nir_print_instr(&instr
->instr
, stderr
);
7934 fprintf(stderr
, "\n");
7938 case nir_intrinsic_write_invocation_amd
: {
7939 Temp src
= as_vgpr(ctx
, get_ssa_temp(ctx
, instr
->src
[0].ssa
));
7940 Temp val
= bld
.as_uniform(get_ssa_temp(ctx
, instr
->src
[1].ssa
));
7941 Temp lane
= bld
.as_uniform(get_ssa_temp(ctx
, instr
->src
[2].ssa
));
7942 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7943 if (dst
.regClass() == v1
) {
7944 /* src2 is ignored for writelane. RA assigns the same reg for dst */
7945 emit_wqm(ctx
, bld
.writelane(bld
.def(v1
), val
, lane
, src
), dst
);
7946 } else if (dst
.regClass() == v2
) {
7947 Temp src_lo
= bld
.tmp(v1
), src_hi
= bld
.tmp(v1
);
7948 Temp val_lo
= bld
.tmp(s1
), val_hi
= bld
.tmp(s1
);
7949 bld
.pseudo(aco_opcode::p_split_vector
, Definition(src_lo
), Definition(src_hi
), src
);
7950 bld
.pseudo(aco_opcode::p_split_vector
, Definition(val_lo
), Definition(val_hi
), val
);
7951 Temp lo
= emit_wqm(ctx
, bld
.writelane(bld
.def(v1
), val_lo
, lane
, src_hi
));
7952 Temp hi
= emit_wqm(ctx
, bld
.writelane(bld
.def(v1
), val_hi
, lane
, src_hi
));
7953 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lo
, hi
);
7954 emit_split_vector(ctx
, dst
, 2);
7956 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
7957 nir_print_instr(&instr
->instr
, stderr
);
7958 fprintf(stderr
, "\n");
7962 case nir_intrinsic_mbcnt_amd
: {
7963 Temp src
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
7964 RegClass rc
= RegClass(src
.type(), 1);
7965 Temp mask_lo
= bld
.tmp(rc
), mask_hi
= bld
.tmp(rc
);
7966 bld
.pseudo(aco_opcode::p_split_vector
, Definition(mask_lo
), Definition(mask_hi
), src
);
7967 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7968 Temp wqm_tmp
= emit_mbcnt(ctx
, bld
.def(v1
), Operand(mask_lo
), Operand(mask_hi
));
7969 emit_wqm(ctx
, wqm_tmp
, dst
);
7972 case nir_intrinsic_load_helper_invocation
: {
7973 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7974 bld
.pseudo(aco_opcode::p_load_helper
, Definition(dst
));
7975 ctx
->block
->kind
|= block_kind_needs_lowering
;
7976 ctx
->program
->needs_exact
= true;
7979 case nir_intrinsic_is_helper_invocation
: {
7980 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7981 bld
.pseudo(aco_opcode::p_is_helper
, Definition(dst
));
7982 ctx
->block
->kind
|= block_kind_needs_lowering
;
7983 ctx
->program
->needs_exact
= true;
7986 case nir_intrinsic_demote
:
7987 bld
.pseudo(aco_opcode::p_demote_to_helper
, Operand(-1u));
7989 if (ctx
->cf_info
.loop_nest_depth
|| ctx
->cf_info
.parent_if
.is_divergent
)
7990 ctx
->cf_info
.exec_potentially_empty_discard
= true;
7991 ctx
->block
->kind
|= block_kind_uses_demote
;
7992 ctx
->program
->needs_exact
= true;
7994 case nir_intrinsic_demote_if
: {
7995 Temp src
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
7996 assert(src
.regClass() == bld
.lm
);
7997 Temp cond
= bld
.sop2(Builder::s_and
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), src
, Operand(exec
, bld
.lm
));
7998 bld
.pseudo(aco_opcode::p_demote_to_helper
, cond
);
8000 if (ctx
->cf_info
.loop_nest_depth
|| ctx
->cf_info
.parent_if
.is_divergent
)
8001 ctx
->cf_info
.exec_potentially_empty_discard
= true;
8002 ctx
->block
->kind
|= block_kind_uses_demote
;
8003 ctx
->program
->needs_exact
= true;
8006 case nir_intrinsic_first_invocation
: {
8007 emit_wqm(ctx
, bld
.sop1(Builder::s_ff1_i32
, bld
.def(s1
), Operand(exec
, bld
.lm
)),
8008 get_ssa_temp(ctx
, &instr
->dest
.ssa
));
8011 case nir_intrinsic_shader_clock
: {
8013 nir_intrinsic_memory_scope(instr
) == NIR_SCOPE_DEVICE
?
8014 aco_opcode::s_memrealtime
: aco_opcode::s_memtime
;
8015 bld
.smem(opcode
, Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
)), false);
8016 emit_split_vector(ctx
, get_ssa_temp(ctx
, &instr
->dest
.ssa
), 2);
8019 case nir_intrinsic_load_vertex_id_zero_base
: {
8020 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
8021 bld
.copy(Definition(dst
), get_arg(ctx
, ctx
->args
->ac
.vertex_id
));
8024 case nir_intrinsic_load_first_vertex
: {
8025 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
8026 bld
.copy(Definition(dst
), get_arg(ctx
, ctx
->args
->ac
.base_vertex
));
8029 case nir_intrinsic_load_base_instance
: {
8030 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
8031 bld
.copy(Definition(dst
), get_arg(ctx
, ctx
->args
->ac
.start_instance
));
8034 case nir_intrinsic_load_instance_id
: {
8035 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
8036 bld
.copy(Definition(dst
), get_arg(ctx
, ctx
->args
->ac
.instance_id
));
8039 case nir_intrinsic_load_draw_id
: {
8040 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
8041 bld
.copy(Definition(dst
), get_arg(ctx
, ctx
->args
->ac
.draw_id
));
8044 case nir_intrinsic_load_invocation_id
: {
8045 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
8047 if (ctx
->shader
->info
.stage
== MESA_SHADER_GEOMETRY
) {
8048 if (ctx
->options
->chip_class
>= GFX10
)
8049 bld
.vop2_e64(aco_opcode::v_and_b32
, Definition(dst
), Operand(127u), get_arg(ctx
, ctx
->args
->ac
.gs_invocation_id
));
8051 bld
.copy(Definition(dst
), get_arg(ctx
, ctx
->args
->ac
.gs_invocation_id
));
8052 } else if (ctx
->shader
->info
.stage
== MESA_SHADER_TESS_CTRL
) {
8053 bld
.vop3(aco_opcode::v_bfe_u32
, Definition(dst
),
8054 get_arg(ctx
, ctx
->args
->ac
.tcs_rel_ids
), Operand(8u), Operand(5u));
8056 unreachable("Unsupported stage for load_invocation_id");
8061 case nir_intrinsic_load_primitive_id
: {
8062 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
8064 switch (ctx
->shader
->info
.stage
) {
8065 case MESA_SHADER_GEOMETRY
:
8066 bld
.copy(Definition(dst
), get_arg(ctx
, ctx
->args
->ac
.gs_prim_id
));
8068 case MESA_SHADER_TESS_CTRL
:
8069 bld
.copy(Definition(dst
), get_arg(ctx
, ctx
->args
->ac
.tcs_patch_id
));
8071 case MESA_SHADER_TESS_EVAL
:
8072 bld
.copy(Definition(dst
), get_arg(ctx
, ctx
->args
->ac
.tes_patch_id
));
8075 unreachable("Unimplemented shader stage for nir_intrinsic_load_primitive_id");
8080 case nir_intrinsic_load_patch_vertices_in
: {
8081 assert(ctx
->shader
->info
.stage
== MESA_SHADER_TESS_CTRL
||
8082 ctx
->shader
->info
.stage
== MESA_SHADER_TESS_EVAL
);
8084 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
8085 bld
.copy(Definition(dst
), Operand(ctx
->args
->options
->key
.tcs
.input_vertices
));
8088 case nir_intrinsic_emit_vertex_with_counter
: {
8089 visit_emit_vertex_with_counter(ctx
, instr
);
8092 case nir_intrinsic_end_primitive_with_counter
: {
8093 unsigned stream
= nir_intrinsic_stream_id(instr
);
8094 bld
.sopp(aco_opcode::s_sendmsg
, bld
.m0(ctx
->gs_wave_id
), -1, sendmsg_gs(true, false, stream
));
8097 case nir_intrinsic_set_vertex_count
: {
8098 /* unused, the HW keeps track of this for us */
8102 fprintf(stderr
, "Unimplemented intrinsic instr: ");
8103 nir_print_instr(&instr
->instr
, stderr
);
8104 fprintf(stderr
, "\n");
8112 void tex_fetch_ptrs(isel_context
*ctx
, nir_tex_instr
*instr
,
8113 Temp
*res_ptr
, Temp
*samp_ptr
, Temp
*fmask_ptr
,
8114 enum glsl_base_type
*stype
)
8116 nir_deref_instr
*texture_deref_instr
= NULL
;
8117 nir_deref_instr
*sampler_deref_instr
= NULL
;
8120 for (unsigned i
= 0; i
< instr
->num_srcs
; i
++) {
8121 switch (instr
->src
[i
].src_type
) {
8122 case nir_tex_src_texture_deref
:
8123 texture_deref_instr
= nir_src_as_deref(instr
->src
[i
].src
);
8125 case nir_tex_src_sampler_deref
:
8126 sampler_deref_instr
= nir_src_as_deref(instr
->src
[i
].src
);
8128 case nir_tex_src_plane
:
8129 plane
= nir_src_as_int(instr
->src
[i
].src
);
8136 *stype
= glsl_get_sampler_result_type(texture_deref_instr
->type
);
8138 if (!sampler_deref_instr
)
8139 sampler_deref_instr
= texture_deref_instr
;
8142 assert(instr
->op
!= nir_texop_txf_ms
&&
8143 instr
->op
!= nir_texop_samples_identical
);
8144 assert(instr
->sampler_dim
!= GLSL_SAMPLER_DIM_BUF
);
8145 *res_ptr
= get_sampler_desc(ctx
, texture_deref_instr
, (aco_descriptor_type
)(ACO_DESC_PLANE_0
+ plane
), instr
, false, false);
8146 } else if (instr
->sampler_dim
== GLSL_SAMPLER_DIM_BUF
) {
8147 *res_ptr
= get_sampler_desc(ctx
, texture_deref_instr
, ACO_DESC_BUFFER
, instr
, false, false);
8148 } else if (instr
->op
== nir_texop_fragment_mask_fetch
) {
8149 *res_ptr
= get_sampler_desc(ctx
, texture_deref_instr
, ACO_DESC_FMASK
, instr
, false, false);
8151 *res_ptr
= get_sampler_desc(ctx
, texture_deref_instr
, ACO_DESC_IMAGE
, instr
, false, false);
8154 *samp_ptr
= get_sampler_desc(ctx
, sampler_deref_instr
, ACO_DESC_SAMPLER
, instr
, false, false);
8156 if (instr
->sampler_dim
< GLSL_SAMPLER_DIM_RECT
&& ctx
->options
->chip_class
< GFX8
) {
8157 /* fix sampler aniso on SI/CI: samp[0] = samp[0] & img[7] */
8158 Builder
bld(ctx
->program
, ctx
->block
);
8160 /* to avoid unnecessary moves, we split and recombine sampler and image */
8161 Temp img
[8] = {bld
.tmp(s1
), bld
.tmp(s1
), bld
.tmp(s1
), bld
.tmp(s1
),
8162 bld
.tmp(s1
), bld
.tmp(s1
), bld
.tmp(s1
), bld
.tmp(s1
)};
8163 Temp samp
[4] = {bld
.tmp(s1
), bld
.tmp(s1
), bld
.tmp(s1
), bld
.tmp(s1
)};
8164 bld
.pseudo(aco_opcode::p_split_vector
, Definition(img
[0]), Definition(img
[1]),
8165 Definition(img
[2]), Definition(img
[3]), Definition(img
[4]),
8166 Definition(img
[5]), Definition(img
[6]), Definition(img
[7]), *res_ptr
);
8167 bld
.pseudo(aco_opcode::p_split_vector
, Definition(samp
[0]), Definition(samp
[1]),
8168 Definition(samp
[2]), Definition(samp
[3]), *samp_ptr
);
8170 samp
[0] = bld
.sop2(aco_opcode::s_and_b32
, bld
.def(s1
), bld
.def(s1
, scc
), samp
[0], img
[7]);
8171 *res_ptr
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s8
),
8172 img
[0], img
[1], img
[2], img
[3],
8173 img
[4], img
[5], img
[6], img
[7]);
8174 *samp_ptr
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s4
),
8175 samp
[0], samp
[1], samp
[2], samp
[3]);
8178 if (fmask_ptr
&& (instr
->op
== nir_texop_txf_ms
||
8179 instr
->op
== nir_texop_samples_identical
))
8180 *fmask_ptr
= get_sampler_desc(ctx
, texture_deref_instr
, ACO_DESC_FMASK
, instr
, false, false);
8183 void build_cube_select(isel_context
*ctx
, Temp ma
, Temp id
, Temp deriv
,
8184 Temp
*out_ma
, Temp
*out_sc
, Temp
*out_tc
)
8186 Builder
bld(ctx
->program
, ctx
->block
);
8188 Temp deriv_x
= emit_extract_vector(ctx
, deriv
, 0, v1
);
8189 Temp deriv_y
= emit_extract_vector(ctx
, deriv
, 1, v1
);
8190 Temp deriv_z
= emit_extract_vector(ctx
, deriv
, 2, v1
);
8192 Operand
neg_one(0xbf800000u
);
8193 Operand
one(0x3f800000u
);
8194 Operand
two(0x40000000u
);
8195 Operand
four(0x40800000u
);
8197 Temp is_ma_positive
= bld
.vopc(aco_opcode::v_cmp_le_f32
, bld
.hint_vcc(bld
.def(bld
.lm
)), Operand(0u), ma
);
8198 Temp sgn_ma
= bld
.vop2_e64(aco_opcode::v_cndmask_b32
, bld
.def(v1
), neg_one
, one
, is_ma_positive
);
8199 Temp neg_sgn_ma
= bld
.vop2(aco_opcode::v_sub_f32
, bld
.def(v1
), Operand(0u), sgn_ma
);
8201 Temp is_ma_z
= bld
.vopc(aco_opcode::v_cmp_le_f32
, bld
.hint_vcc(bld
.def(bld
.lm
)), four
, id
);
8202 Temp is_ma_y
= bld
.vopc(aco_opcode::v_cmp_le_f32
, bld
.def(bld
.lm
), two
, id
);
8203 is_ma_y
= bld
.sop2(Builder::s_andn2
, bld
.hint_vcc(bld
.def(bld
.lm
)), is_ma_y
, is_ma_z
);
8204 Temp is_not_ma_x
= bld
.sop2(aco_opcode::s_or_b64
, bld
.hint_vcc(bld
.def(bld
.lm
)), bld
.def(s1
, scc
), is_ma_z
, is_ma_y
);
8207 Temp tmp
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), deriv_z
, deriv_x
, is_not_ma_x
);
8208 Temp sgn
= bld
.vop2_e64(aco_opcode::v_cndmask_b32
, bld
.def(v1
),
8209 bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), neg_sgn_ma
, sgn_ma
, is_ma_z
),
8211 *out_sc
= bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), tmp
, sgn
);
8214 tmp
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), deriv_y
, deriv_z
, is_ma_y
);
8215 sgn
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), neg_one
, sgn_ma
, is_ma_y
);
8216 *out_tc
= bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), tmp
, sgn
);
8219 tmp
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
),
8220 bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), deriv_x
, deriv_y
, is_ma_y
),
8222 tmp
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(0x7fffffffu
), tmp
);
8223 *out_ma
= bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), two
, tmp
);
8226 void prepare_cube_coords(isel_context
*ctx
, std::vector
<Temp
>& coords
, Temp
* ddx
, Temp
* ddy
, bool is_deriv
, bool is_array
)
8228 Builder
bld(ctx
->program
, ctx
->block
);
8229 Temp ma
, tc
, sc
, id
;
8232 coords
[3] = bld
.vop1(aco_opcode::v_rndne_f32
, bld
.def(v1
), coords
[3]);
8234 // see comment in ac_prepare_cube_coords()
8235 if (ctx
->options
->chip_class
<= GFX8
)
8236 coords
[3] = bld
.vop2(aco_opcode::v_max_f32
, bld
.def(v1
), Operand(0u), coords
[3]);
8239 ma
= bld
.vop3(aco_opcode::v_cubema_f32
, bld
.def(v1
), coords
[0], coords
[1], coords
[2]);
8241 aco_ptr
<VOP3A_instruction
> vop3a
{create_instruction
<VOP3A_instruction
>(aco_opcode::v_rcp_f32
, asVOP3(Format::VOP1
), 1, 1)};
8242 vop3a
->operands
[0] = Operand(ma
);
8243 vop3a
->abs
[0] = true;
8244 Temp invma
= bld
.tmp(v1
);
8245 vop3a
->definitions
[0] = Definition(invma
);
8246 ctx
->block
->instructions
.emplace_back(std::move(vop3a
));
8248 sc
= bld
.vop3(aco_opcode::v_cubesc_f32
, bld
.def(v1
), coords
[0], coords
[1], coords
[2]);
8250 sc
= bld
.vop2(aco_opcode::v_madak_f32
, bld
.def(v1
), sc
, invma
, Operand(0x3fc00000u
/*1.5*/));
8252 tc
= bld
.vop3(aco_opcode::v_cubetc_f32
, bld
.def(v1
), coords
[0], coords
[1], coords
[2]);
8254 tc
= bld
.vop2(aco_opcode::v_madak_f32
, bld
.def(v1
), tc
, invma
, Operand(0x3fc00000u
/*1.5*/));
8256 id
= bld
.vop3(aco_opcode::v_cubeid_f32
, bld
.def(v1
), coords
[0], coords
[1], coords
[2]);
8259 sc
= bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), sc
, invma
);
8260 tc
= bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), tc
, invma
);
8262 for (unsigned i
= 0; i
< 2; i
++) {
8263 // see comment in ac_prepare_cube_coords()
8265 Temp deriv_sc
, deriv_tc
;
8266 build_cube_select(ctx
, ma
, id
, i
? *ddy
: *ddx
,
8267 &deriv_ma
, &deriv_sc
, &deriv_tc
);
8269 deriv_ma
= bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), deriv_ma
, invma
);
8271 Temp x
= bld
.vop2(aco_opcode::v_sub_f32
, bld
.def(v1
),
8272 bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), deriv_sc
, invma
),
8273 bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), deriv_ma
, sc
));
8274 Temp y
= bld
.vop2(aco_opcode::v_sub_f32
, bld
.def(v1
),
8275 bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), deriv_tc
, invma
),
8276 bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), deriv_ma
, tc
));
8277 *(i
? ddy
: ddx
) = bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), x
, y
);
8280 sc
= bld
.vop2(aco_opcode::v_add_f32
, bld
.def(v1
), Operand(0x3fc00000u
/*1.5*/), sc
);
8281 tc
= bld
.vop2(aco_opcode::v_add_f32
, bld
.def(v1
), Operand(0x3fc00000u
/*1.5*/), tc
);
8285 id
= bld
.vop2(aco_opcode::v_madmk_f32
, bld
.def(v1
), coords
[3], id
, Operand(0x41000000u
/*8.0*/));
8292 void get_const_vec(nir_ssa_def
*vec
, nir_const_value
*cv
[4])
8294 if (vec
->parent_instr
->type
!= nir_instr_type_alu
)
8296 nir_alu_instr
*vec_instr
= nir_instr_as_alu(vec
->parent_instr
);
8297 if (vec_instr
->op
!= nir_op_vec(vec
->num_components
))
8300 for (unsigned i
= 0; i
< vec
->num_components
; i
++) {
8301 cv
[i
] = vec_instr
->src
[i
].swizzle
[0] == 0 ?
8302 nir_src_as_const_value(vec_instr
->src
[i
].src
) : NULL
;
8306 void visit_tex(isel_context
*ctx
, nir_tex_instr
*instr
)
8308 Builder
bld(ctx
->program
, ctx
->block
);
8309 bool has_bias
= false, has_lod
= false, level_zero
= false, has_compare
= false,
8310 has_offset
= false, has_ddx
= false, has_ddy
= false, has_derivs
= false, has_sample_index
= false,
8311 has_clamped_lod
= false;
8312 Temp resource
, sampler
, fmask_ptr
, bias
= Temp(), compare
= Temp(), sample_index
= Temp(),
8313 lod
= Temp(), offset
= Temp(), ddx
= Temp(), ddy
= Temp(),
8314 clamped_lod
= Temp();
8315 std::vector
<Temp
> coords
;
8316 std::vector
<Temp
> derivs
;
8317 nir_const_value
*sample_index_cv
= NULL
;
8318 nir_const_value
*const_offset
[4] = {NULL
, NULL
, NULL
, NULL
};
8319 enum glsl_base_type stype
;
8320 tex_fetch_ptrs(ctx
, instr
, &resource
, &sampler
, &fmask_ptr
, &stype
);
8322 bool tg4_integer_workarounds
= ctx
->options
->chip_class
<= GFX8
&& instr
->op
== nir_texop_tg4
&&
8323 (stype
== GLSL_TYPE_UINT
|| stype
== GLSL_TYPE_INT
);
8324 bool tg4_integer_cube_workaround
= tg4_integer_workarounds
&&
8325 instr
->sampler_dim
== GLSL_SAMPLER_DIM_CUBE
;
8327 for (unsigned i
= 0; i
< instr
->num_srcs
; i
++) {
8328 switch (instr
->src
[i
].src_type
) {
8329 case nir_tex_src_coord
: {
8330 Temp coord
= get_ssa_temp(ctx
, instr
->src
[i
].src
.ssa
);
8331 for (unsigned i
= 0; i
< coord
.size(); i
++)
8332 coords
.emplace_back(emit_extract_vector(ctx
, coord
, i
, v1
));
8335 case nir_tex_src_bias
:
8336 bias
= get_ssa_temp(ctx
, instr
->src
[i
].src
.ssa
);
8339 case nir_tex_src_lod
: {
8340 nir_const_value
*val
= nir_src_as_const_value(instr
->src
[i
].src
);
8342 if (val
&& val
->f32
<= 0.0) {
8345 lod
= get_ssa_temp(ctx
, instr
->src
[i
].src
.ssa
);
8350 case nir_tex_src_min_lod
:
8351 clamped_lod
= get_ssa_temp(ctx
, instr
->src
[i
].src
.ssa
);
8352 has_clamped_lod
= true;
8354 case nir_tex_src_comparator
:
8355 if (instr
->is_shadow
) {
8356 compare
= get_ssa_temp(ctx
, instr
->src
[i
].src
.ssa
);
8360 case nir_tex_src_offset
:
8361 offset
= get_ssa_temp(ctx
, instr
->src
[i
].src
.ssa
);
8362 get_const_vec(instr
->src
[i
].src
.ssa
, const_offset
);
8365 case nir_tex_src_ddx
:
8366 ddx
= get_ssa_temp(ctx
, instr
->src
[i
].src
.ssa
);
8369 case nir_tex_src_ddy
:
8370 ddy
= get_ssa_temp(ctx
, instr
->src
[i
].src
.ssa
);
8373 case nir_tex_src_ms_index
:
8374 sample_index
= get_ssa_temp(ctx
, instr
->src
[i
].src
.ssa
);
8375 sample_index_cv
= nir_src_as_const_value(instr
->src
[i
].src
);
8376 has_sample_index
= true;
8378 case nir_tex_src_texture_offset
:
8379 case nir_tex_src_sampler_offset
:
8385 if (instr
->op
== nir_texop_txs
&& instr
->sampler_dim
== GLSL_SAMPLER_DIM_BUF
)
8386 return get_buffer_size(ctx
, resource
, get_ssa_temp(ctx
, &instr
->dest
.ssa
), true);
8388 if (instr
->op
== nir_texop_texture_samples
) {
8389 Temp dword3
= emit_extract_vector(ctx
, resource
, 3, s1
);
8391 Temp samples_log2
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
), dword3
, Operand(16u | 4u<<16));
8392 Temp samples
= bld
.sop2(aco_opcode::s_lshl_b32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(1u), samples_log2
);
8393 Temp type
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
), dword3
, Operand(28u | 4u<<16 /* offset=28, width=4 */));
8395 Operand default_sample
= Operand(1u);
8396 if (ctx
->options
->robust_buffer_access
) {
8397 /* Extract the second dword of the descriptor, if it's
8398 * all zero, then it's a null descriptor.
8400 Temp dword1
= emit_extract_vector(ctx
, resource
, 1, s1
);
8401 Temp is_non_null_descriptor
= bld
.sopc(aco_opcode::s_cmp_gt_u32
, bld
.def(s1
, scc
), dword1
, Operand(0u));
8402 default_sample
= Operand(is_non_null_descriptor
);
8405 Temp is_msaa
= bld
.sopc(aco_opcode::s_cmp_ge_u32
, bld
.def(s1
, scc
), type
, Operand(14u));
8406 bld
.sop2(aco_opcode::s_cselect_b32
, Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
)),
8407 samples
, default_sample
, bld
.scc(is_msaa
));
8411 if (has_offset
&& instr
->op
!= nir_texop_txf
&& instr
->op
!= nir_texop_txf_ms
) {
8412 aco_ptr
<Instruction
> tmp_instr
;
8413 Temp acc
, pack
= Temp();
8415 uint32_t pack_const
= 0;
8416 for (unsigned i
= 0; i
< offset
.size(); i
++) {
8417 if (!const_offset
[i
])
8419 pack_const
|= (const_offset
[i
]->u32
& 0x3Fu
) << (8u * i
);
8422 if (offset
.type() == RegType::sgpr
) {
8423 for (unsigned i
= 0; i
< offset
.size(); i
++) {
8424 if (const_offset
[i
])
8427 acc
= emit_extract_vector(ctx
, offset
, i
, s1
);
8428 acc
= bld
.sop2(aco_opcode::s_and_b32
, bld
.def(s1
), bld
.def(s1
, scc
), acc
, Operand(0x3Fu
));
8431 acc
= bld
.sop2(aco_opcode::s_lshl_b32
, bld
.def(s1
), bld
.def(s1
, scc
), acc
, Operand(8u * i
));
8434 if (pack
== Temp()) {
8437 pack
= bld
.sop2(aco_opcode::s_or_b32
, bld
.def(s1
), bld
.def(s1
, scc
), pack
, acc
);
8441 if (pack_const
&& pack
!= Temp())
8442 pack
= bld
.sop2(aco_opcode::s_or_b32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(pack_const
), pack
);
8444 for (unsigned i
= 0; i
< offset
.size(); i
++) {
8445 if (const_offset
[i
])
8448 acc
= emit_extract_vector(ctx
, offset
, i
, v1
);
8449 acc
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(0x3Fu
), acc
);
8452 acc
= bld
.vop2(aco_opcode::v_lshlrev_b32
, bld
.def(v1
), Operand(8u * i
), acc
);
8455 if (pack
== Temp()) {
8458 pack
= bld
.vop2(aco_opcode::v_or_b32
, bld
.def(v1
), pack
, acc
);
8462 if (pack_const
&& pack
!= Temp())
8463 pack
= bld
.sop2(aco_opcode::v_or_b32
, bld
.def(v1
), Operand(pack_const
), pack
);
8465 if (pack_const
&& pack
== Temp())
8466 offset
= bld
.vop1(aco_opcode::v_mov_b32
, bld
.def(v1
), Operand(pack_const
));
8467 else if (pack
== Temp())
8473 if (instr
->sampler_dim
== GLSL_SAMPLER_DIM_CUBE
&& instr
->coord_components
)
8474 prepare_cube_coords(ctx
, coords
, &ddx
, &ddy
, instr
->op
== nir_texop_txd
, instr
->is_array
&& instr
->op
!= nir_texop_lod
);
8476 /* pack derivatives */
8477 if (has_ddx
|| has_ddy
) {
8478 if (instr
->sampler_dim
== GLSL_SAMPLER_DIM_1D
&& ctx
->options
->chip_class
== GFX9
) {
8479 assert(has_ddx
&& has_ddy
&& ddx
.size() == 1 && ddy
.size() == 1);
8480 Temp zero
= bld
.copy(bld
.def(v1
), Operand(0u));
8481 derivs
= {ddx
, zero
, ddy
, zero
};
8483 for (unsigned i
= 0; has_ddx
&& i
< ddx
.size(); i
++)
8484 derivs
.emplace_back(emit_extract_vector(ctx
, ddx
, i
, v1
));
8485 for (unsigned i
= 0; has_ddy
&& i
< ddy
.size(); i
++)
8486 derivs
.emplace_back(emit_extract_vector(ctx
, ddy
, i
, v1
));
8491 if (instr
->coord_components
> 1 &&
8492 instr
->sampler_dim
== GLSL_SAMPLER_DIM_1D
&&
8494 instr
->op
!= nir_texop_txf
)
8495 coords
[1] = bld
.vop1(aco_opcode::v_rndne_f32
, bld
.def(v1
), coords
[1]);
8497 if (instr
->coord_components
> 2 &&
8498 (instr
->sampler_dim
== GLSL_SAMPLER_DIM_2D
||
8499 instr
->sampler_dim
== GLSL_SAMPLER_DIM_MS
||
8500 instr
->sampler_dim
== GLSL_SAMPLER_DIM_SUBPASS
||
8501 instr
->sampler_dim
== GLSL_SAMPLER_DIM_SUBPASS_MS
) &&
8503 instr
->op
!= nir_texop_txf
&&
8504 instr
->op
!= nir_texop_txf_ms
&&
8505 instr
->op
!= nir_texop_fragment_fetch
&&
8506 instr
->op
!= nir_texop_fragment_mask_fetch
)
8507 coords
[2] = bld
.vop1(aco_opcode::v_rndne_f32
, bld
.def(v1
), coords
[2]);
8509 if (ctx
->options
->chip_class
== GFX9
&&
8510 instr
->sampler_dim
== GLSL_SAMPLER_DIM_1D
&&
8511 instr
->op
!= nir_texop_lod
&& instr
->coord_components
) {
8512 assert(coords
.size() > 0 && coords
.size() < 3);
8514 coords
.insert(std::next(coords
.begin()), bld
.copy(bld
.def(v1
), instr
->op
== nir_texop_txf
?
8515 Operand((uint32_t) 0) :
8516 Operand((uint32_t) 0x3f000000)));
8519 bool da
= should_declare_array(ctx
, instr
->sampler_dim
, instr
->is_array
);
8521 if (instr
->op
== nir_texop_samples_identical
)
8522 resource
= fmask_ptr
;
8524 else if ((instr
->sampler_dim
== GLSL_SAMPLER_DIM_MS
||
8525 instr
->sampler_dim
== GLSL_SAMPLER_DIM_SUBPASS_MS
) &&
8526 instr
->op
!= nir_texop_txs
&&
8527 instr
->op
!= nir_texop_fragment_fetch
&&
8528 instr
->op
!= nir_texop_fragment_mask_fetch
) {
8529 assert(has_sample_index
);
8530 Operand
op(sample_index
);
8531 if (sample_index_cv
)
8532 op
= Operand(sample_index_cv
->u32
);
8533 sample_index
= adjust_sample_index_using_fmask(ctx
, da
, coords
, op
, fmask_ptr
);
8536 if (has_offset
&& (instr
->op
== nir_texop_txf
|| instr
->op
== nir_texop_txf_ms
)) {
8537 for (unsigned i
= 0; i
< std::min(offset
.size(), instr
->coord_components
); i
++) {
8538 Temp off
= emit_extract_vector(ctx
, offset
, i
, v1
);
8539 coords
[i
] = bld
.vadd32(bld
.def(v1
), coords
[i
], off
);
8544 /* Build tex instruction */
8545 unsigned dmask
= nir_ssa_def_components_read(&instr
->dest
.ssa
);
8546 unsigned dim
= ctx
->options
->chip_class
>= GFX10
&& instr
->sampler_dim
!= GLSL_SAMPLER_DIM_BUF
8547 ? ac_get_sampler_dim(ctx
->options
->chip_class
, instr
->sampler_dim
, instr
->is_array
)
8549 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
8552 /* gather4 selects the component by dmask and always returns vec4 */
8553 if (instr
->op
== nir_texop_tg4
) {
8554 assert(instr
->dest
.ssa
.num_components
== 4);
8555 if (instr
->is_shadow
)
8558 dmask
= 1 << instr
->component
;
8559 if (tg4_integer_cube_workaround
|| dst
.type() == RegType::sgpr
)
8560 tmp_dst
= bld
.tmp(v4
);
8561 } else if (instr
->op
== nir_texop_samples_identical
) {
8562 tmp_dst
= bld
.tmp(v1
);
8563 } else if (util_bitcount(dmask
) != instr
->dest
.ssa
.num_components
|| dst
.type() == RegType::sgpr
) {
8564 tmp_dst
= bld
.tmp(RegClass(RegType::vgpr
, util_bitcount(dmask
)));
8567 aco_ptr
<MIMG_instruction
> tex
;
8568 if (instr
->op
== nir_texop_txs
|| instr
->op
== nir_texop_query_levels
) {
8570 lod
= bld
.vop1(aco_opcode::v_mov_b32
, bld
.def(v1
), Operand(0u));
8572 bool div_by_6
= instr
->op
== nir_texop_txs
&&
8573 instr
->sampler_dim
== GLSL_SAMPLER_DIM_CUBE
&&
8576 if (tmp_dst
.id() == dst
.id() && div_by_6
)
8577 tmp_dst
= bld
.tmp(tmp_dst
.regClass());
8579 tex
.reset(create_instruction
<MIMG_instruction
>(aco_opcode::image_get_resinfo
, Format::MIMG
, 3, 1));
8580 tex
->operands
[0] = Operand(resource
);
8581 tex
->operands
[1] = Operand(s4
); /* no sampler */
8582 tex
->operands
[2] = Operand(as_vgpr(ctx
,lod
));
8583 if (ctx
->options
->chip_class
== GFX9
&&
8584 instr
->op
== nir_texop_txs
&&
8585 instr
->sampler_dim
== GLSL_SAMPLER_DIM_1D
&&
8587 tex
->dmask
= (dmask
& 0x1) | ((dmask
& 0x2) << 1);
8588 } else if (instr
->op
== nir_texop_query_levels
) {
8589 tex
->dmask
= 1 << 3;
8594 tex
->definitions
[0] = Definition(tmp_dst
);
8596 tex
->can_reorder
= true;
8597 ctx
->block
->instructions
.emplace_back(std::move(tex
));
8600 /* divide 3rd value by 6 by multiplying with magic number */
8601 emit_split_vector(ctx
, tmp_dst
, tmp_dst
.size());
8602 Temp c
= bld
.copy(bld
.def(s1
), Operand((uint32_t) 0x2AAAAAAB));
8603 Temp by_6
= bld
.vop3(aco_opcode::v_mul_hi_i32
, bld
.def(v1
), emit_extract_vector(ctx
, tmp_dst
, 2, v1
), c
);
8604 assert(instr
->dest
.ssa
.num_components
== 3);
8605 Temp tmp
= dst
.type() == RegType::vgpr
? dst
: bld
.tmp(v3
);
8606 tmp_dst
= bld
.pseudo(aco_opcode::p_create_vector
, Definition(tmp
),
8607 emit_extract_vector(ctx
, tmp_dst
, 0, v1
),
8608 emit_extract_vector(ctx
, tmp_dst
, 1, v1
),
8613 expand_vector(ctx
, tmp_dst
, dst
, instr
->dest
.ssa
.num_components
, dmask
);
8617 Temp tg4_compare_cube_wa64
= Temp();
8619 if (tg4_integer_workarounds
) {
8620 tex
.reset(create_instruction
<MIMG_instruction
>(aco_opcode::image_get_resinfo
, Format::MIMG
, 3, 1));
8621 tex
->operands
[0] = Operand(resource
);
8622 tex
->operands
[1] = Operand(s4
); /* no sampler */
8623 tex
->operands
[2] = bld
.vop1(aco_opcode::v_mov_b32
, bld
.def(v1
), Operand(0u));
8627 Temp size
= bld
.tmp(v2
);
8628 tex
->definitions
[0] = Definition(size
);
8629 tex
->can_reorder
= true;
8630 ctx
->block
->instructions
.emplace_back(std::move(tex
));
8631 emit_split_vector(ctx
, size
, size
.size());
8634 for (unsigned i
= 0; i
< 2; i
++) {
8635 half_texel
[i
] = emit_extract_vector(ctx
, size
, i
, v1
);
8636 half_texel
[i
] = bld
.vop1(aco_opcode::v_cvt_f32_i32
, bld
.def(v1
), half_texel
[i
]);
8637 half_texel
[i
] = bld
.vop1(aco_opcode::v_rcp_iflag_f32
, bld
.def(v1
), half_texel
[i
]);
8638 half_texel
[i
] = bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), Operand(0xbf000000/*-0.5*/), half_texel
[i
]);
8641 Temp new_coords
[2] = {
8642 bld
.vop2(aco_opcode::v_add_f32
, bld
.def(v1
), coords
[0], half_texel
[0]),
8643 bld
.vop2(aco_opcode::v_add_f32
, bld
.def(v1
), coords
[1], half_texel
[1])
8646 if (tg4_integer_cube_workaround
) {
8647 // see comment in ac_nir_to_llvm.c's lower_gather4_integer()
8648 Temp desc
[resource
.size()];
8649 aco_ptr
<Instruction
> split
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_split_vector
,
8650 Format::PSEUDO
, 1, resource
.size())};
8651 split
->operands
[0] = Operand(resource
);
8652 for (unsigned i
= 0; i
< resource
.size(); i
++) {
8653 desc
[i
] = bld
.tmp(s1
);
8654 split
->definitions
[i
] = Definition(desc
[i
]);
8656 ctx
->block
->instructions
.emplace_back(std::move(split
));
8658 Temp dfmt
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
), desc
[1], Operand(20u | (6u << 16)));
8659 Temp compare_cube_wa
= bld
.sopc(aco_opcode::s_cmp_eq_u32
, bld
.def(s1
, scc
), dfmt
,
8660 Operand((uint32_t)V_008F14_IMG_DATA_FORMAT_8_8_8_8
));
8663 if (stype
== GLSL_TYPE_UINT
) {
8664 nfmt
= bld
.sop2(aco_opcode::s_cselect_b32
, bld
.def(s1
),
8665 Operand((uint32_t)V_008F14_IMG_NUM_FORMAT_USCALED
),
8666 Operand((uint32_t)V_008F14_IMG_NUM_FORMAT_UINT
),
8667 bld
.scc(compare_cube_wa
));
8669 nfmt
= bld
.sop2(aco_opcode::s_cselect_b32
, bld
.def(s1
),
8670 Operand((uint32_t)V_008F14_IMG_NUM_FORMAT_SSCALED
),
8671 Operand((uint32_t)V_008F14_IMG_NUM_FORMAT_SINT
),
8672 bld
.scc(compare_cube_wa
));
8674 tg4_compare_cube_wa64
= bld
.tmp(bld
.lm
);
8675 bool_to_vector_condition(ctx
, compare_cube_wa
, tg4_compare_cube_wa64
);
8677 nfmt
= bld
.sop2(aco_opcode::s_lshl_b32
, bld
.def(s1
), bld
.def(s1
, scc
), nfmt
, Operand(26u));
8679 desc
[1] = bld
.sop2(aco_opcode::s_and_b32
, bld
.def(s1
), bld
.def(s1
, scc
), desc
[1],
8680 Operand((uint32_t)C_008F14_NUM_FORMAT
));
8681 desc
[1] = bld
.sop2(aco_opcode::s_or_b32
, bld
.def(s1
), bld
.def(s1
, scc
), desc
[1], nfmt
);
8683 aco_ptr
<Instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
,
8684 Format::PSEUDO
, resource
.size(), 1)};
8685 for (unsigned i
= 0; i
< resource
.size(); i
++)
8686 vec
->operands
[i
] = Operand(desc
[i
]);
8687 resource
= bld
.tmp(resource
.regClass());
8688 vec
->definitions
[0] = Definition(resource
);
8689 ctx
->block
->instructions
.emplace_back(std::move(vec
));
8691 new_coords
[0] = bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
),
8692 new_coords
[0], coords
[0], tg4_compare_cube_wa64
);
8693 new_coords
[1] = bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
),
8694 new_coords
[1], coords
[1], tg4_compare_cube_wa64
);
8696 coords
[0] = new_coords
[0];
8697 coords
[1] = new_coords
[1];
8700 if (instr
->sampler_dim
== GLSL_SAMPLER_DIM_BUF
) {
8701 //FIXME: if (ctx->abi->gfx9_stride_size_workaround) return ac_build_buffer_load_format_gfx9_safe()
8703 assert(coords
.size() == 1);
8704 unsigned last_bit
= util_last_bit(nir_ssa_def_components_read(&instr
->dest
.ssa
));
8708 op
= aco_opcode::buffer_load_format_x
; break;
8710 op
= aco_opcode::buffer_load_format_xy
; break;
8712 op
= aco_opcode::buffer_load_format_xyz
; break;
8714 op
= aco_opcode::buffer_load_format_xyzw
; break;
8716 unreachable("Tex instruction loads more than 4 components.");
8719 /* if the instruction return value matches exactly the nir dest ssa, we can use it directly */
8720 if (last_bit
== instr
->dest
.ssa
.num_components
&& dst
.type() == RegType::vgpr
)
8723 tmp_dst
= bld
.tmp(RegType::vgpr
, last_bit
);
8725 aco_ptr
<MUBUF_instruction
> mubuf
{create_instruction
<MUBUF_instruction
>(op
, Format::MUBUF
, 3, 1)};
8726 mubuf
->operands
[0] = Operand(resource
);
8727 mubuf
->operands
[1] = Operand(coords
[0]);
8728 mubuf
->operands
[2] = Operand((uint32_t) 0);
8729 mubuf
->definitions
[0] = Definition(tmp_dst
);
8730 mubuf
->idxen
= true;
8731 mubuf
->can_reorder
= true;
8732 ctx
->block
->instructions
.emplace_back(std::move(mubuf
));
8734 expand_vector(ctx
, tmp_dst
, dst
, instr
->dest
.ssa
.num_components
, (1 << last_bit
) - 1);
8738 /* gather MIMG address components */
8739 std::vector
<Temp
> args
;
8741 args
.emplace_back(offset
);
8743 args
.emplace_back(bias
);
8745 args
.emplace_back(compare
);
8747 args
.insert(args
.end(), derivs
.begin(), derivs
.end());
8749 args
.insert(args
.end(), coords
.begin(), coords
.end());
8750 if (has_sample_index
)
8751 args
.emplace_back(sample_index
);
8753 args
.emplace_back(lod
);
8754 if (has_clamped_lod
)
8755 args
.emplace_back(clamped_lod
);
8757 Temp arg
= bld
.tmp(RegClass(RegType::vgpr
, args
.size()));
8758 aco_ptr
<Instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, args
.size(), 1)};
8759 vec
->definitions
[0] = Definition(arg
);
8760 for (unsigned i
= 0; i
< args
.size(); i
++)
8761 vec
->operands
[i
] = Operand(args
[i
]);
8762 ctx
->block
->instructions
.emplace_back(std::move(vec
));
8765 if (instr
->op
== nir_texop_txf
||
8766 instr
->op
== nir_texop_txf_ms
||
8767 instr
->op
== nir_texop_samples_identical
||
8768 instr
->op
== nir_texop_fragment_fetch
||
8769 instr
->op
== nir_texop_fragment_mask_fetch
) {
8770 aco_opcode op
= level_zero
|| instr
->sampler_dim
== GLSL_SAMPLER_DIM_MS
|| instr
->sampler_dim
== GLSL_SAMPLER_DIM_SUBPASS_MS
? aco_opcode::image_load
: aco_opcode::image_load_mip
;
8771 tex
.reset(create_instruction
<MIMG_instruction
>(op
, Format::MIMG
, 3, 1));
8772 tex
->operands
[0] = Operand(resource
);
8773 tex
->operands
[1] = Operand(s4
); /* no sampler */
8774 tex
->operands
[2] = Operand(arg
);
8779 tex
->definitions
[0] = Definition(tmp_dst
);
8780 tex
->can_reorder
= true;
8781 ctx
->block
->instructions
.emplace_back(std::move(tex
));
8783 if (instr
->op
== nir_texop_samples_identical
) {
8784 assert(dmask
== 1 && dst
.regClass() == v1
);
8785 assert(dst
.id() != tmp_dst
.id());
8787 Temp tmp
= bld
.tmp(bld
.lm
);
8788 bld
.vopc(aco_opcode::v_cmp_eq_u32
, Definition(tmp
), Operand(0u), tmp_dst
).def(0).setHint(vcc
);
8789 bld
.vop2_e64(aco_opcode::v_cndmask_b32
, Definition(dst
), Operand(0u), Operand((uint32_t)-1), tmp
);
8792 expand_vector(ctx
, tmp_dst
, dst
, instr
->dest
.ssa
.num_components
, dmask
);
8797 // TODO: would be better to do this by adding offsets, but needs the opcodes ordered.
8798 aco_opcode opcode
= aco_opcode::image_sample
;
8799 if (has_offset
) { /* image_sample_*_o */
8800 if (has_clamped_lod
) {
8802 opcode
= aco_opcode::image_sample_c_cl_o
;
8804 opcode
= aco_opcode::image_sample_c_d_cl_o
;
8806 opcode
= aco_opcode::image_sample_c_b_cl_o
;
8808 opcode
= aco_opcode::image_sample_cl_o
;
8810 opcode
= aco_opcode::image_sample_d_cl_o
;
8812 opcode
= aco_opcode::image_sample_b_cl_o
;
8814 } else if (has_compare
) {
8815 opcode
= aco_opcode::image_sample_c_o
;
8817 opcode
= aco_opcode::image_sample_c_d_o
;
8819 opcode
= aco_opcode::image_sample_c_b_o
;
8821 opcode
= aco_opcode::image_sample_c_lz_o
;
8823 opcode
= aco_opcode::image_sample_c_l_o
;
8825 opcode
= aco_opcode::image_sample_o
;
8827 opcode
= aco_opcode::image_sample_d_o
;
8829 opcode
= aco_opcode::image_sample_b_o
;
8831 opcode
= aco_opcode::image_sample_lz_o
;
8833 opcode
= aco_opcode::image_sample_l_o
;
8835 } else if (has_clamped_lod
) { /* image_sample_*_cl */
8837 opcode
= aco_opcode::image_sample_c_cl
;
8839 opcode
= aco_opcode::image_sample_c_d_cl
;
8841 opcode
= aco_opcode::image_sample_c_b_cl
;
8843 opcode
= aco_opcode::image_sample_cl
;
8845 opcode
= aco_opcode::image_sample_d_cl
;
8847 opcode
= aco_opcode::image_sample_b_cl
;
8849 } else { /* no offset */
8851 opcode
= aco_opcode::image_sample_c
;
8853 opcode
= aco_opcode::image_sample_c_d
;
8855 opcode
= aco_opcode::image_sample_c_b
;
8857 opcode
= aco_opcode::image_sample_c_lz
;
8859 opcode
= aco_opcode::image_sample_c_l
;
8861 opcode
= aco_opcode::image_sample
;
8863 opcode
= aco_opcode::image_sample_d
;
8865 opcode
= aco_opcode::image_sample_b
;
8867 opcode
= aco_opcode::image_sample_lz
;
8869 opcode
= aco_opcode::image_sample_l
;
8873 if (instr
->op
== nir_texop_tg4
) {
8874 if (has_offset
) { /* image_gather4_*_o */
8876 opcode
= aco_opcode::image_gather4_c_lz_o
;
8878 opcode
= aco_opcode::image_gather4_c_l_o
;
8880 opcode
= aco_opcode::image_gather4_c_b_o
;
8882 opcode
= aco_opcode::image_gather4_lz_o
;
8884 opcode
= aco_opcode::image_gather4_l_o
;
8886 opcode
= aco_opcode::image_gather4_b_o
;
8890 opcode
= aco_opcode::image_gather4_c_lz
;
8892 opcode
= aco_opcode::image_gather4_c_l
;
8894 opcode
= aco_opcode::image_gather4_c_b
;
8896 opcode
= aco_opcode::image_gather4_lz
;
8898 opcode
= aco_opcode::image_gather4_l
;
8900 opcode
= aco_opcode::image_gather4_b
;
8903 } else if (instr
->op
== nir_texop_lod
) {
8904 opcode
= aco_opcode::image_get_lod
;
8907 /* we don't need the bias, sample index, compare value or offset to be
8908 * computed in WQM but if the p_create_vector copies the coordinates, then it
8909 * needs to be in WQM */
8910 if (ctx
->stage
== fragment_fs
&&
8911 !has_derivs
&& !has_lod
&& !level_zero
&&
8912 instr
->sampler_dim
!= GLSL_SAMPLER_DIM_MS
&&
8913 instr
->sampler_dim
!= GLSL_SAMPLER_DIM_SUBPASS_MS
)
8914 arg
= emit_wqm(ctx
, arg
, bld
.tmp(arg
.regClass()), true);
8916 tex
.reset(create_instruction
<MIMG_instruction
>(opcode
, Format::MIMG
, 3, 1));
8917 tex
->operands
[0] = Operand(resource
);
8918 tex
->operands
[1] = Operand(sampler
);
8919 tex
->operands
[2] = Operand(arg
);
8923 tex
->definitions
[0] = Definition(tmp_dst
);
8924 tex
->can_reorder
= true;
8925 ctx
->block
->instructions
.emplace_back(std::move(tex
));
8927 if (tg4_integer_cube_workaround
) {
8928 assert(tmp_dst
.id() != dst
.id());
8929 assert(tmp_dst
.size() == dst
.size() && dst
.size() == 4);
8931 emit_split_vector(ctx
, tmp_dst
, tmp_dst
.size());
8933 for (unsigned i
= 0; i
< dst
.size(); i
++) {
8934 val
[i
] = emit_extract_vector(ctx
, tmp_dst
, i
, v1
);
8936 if (stype
== GLSL_TYPE_UINT
)
8937 cvt_val
= bld
.vop1(aco_opcode::v_cvt_u32_f32
, bld
.def(v1
), val
[i
]);
8939 cvt_val
= bld
.vop1(aco_opcode::v_cvt_i32_f32
, bld
.def(v1
), val
[i
]);
8940 val
[i
] = bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), val
[i
], cvt_val
, tg4_compare_cube_wa64
);
8942 Temp tmp
= dst
.regClass() == v4
? dst
: bld
.tmp(v4
);
8943 tmp_dst
= bld
.pseudo(aco_opcode::p_create_vector
, Definition(tmp
),
8944 val
[0], val
[1], val
[2], val
[3]);
8946 unsigned mask
= instr
->op
== nir_texop_tg4
? 0xF : dmask
;
8947 expand_vector(ctx
, tmp_dst
, dst
, instr
->dest
.ssa
.num_components
, mask
);
8952 Operand
get_phi_operand(isel_context
*ctx
, nir_ssa_def
*ssa
, RegClass rc
)
8954 Temp tmp
= get_ssa_temp(ctx
, ssa
);
8955 if (ssa
->parent_instr
->type
== nir_instr_type_ssa_undef
)
8958 return Operand(tmp
);
8961 void visit_phi(isel_context
*ctx
, nir_phi_instr
*instr
)
8963 aco_ptr
<Pseudo_instruction
> phi
;
8964 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
8965 assert(instr
->dest
.ssa
.bit_size
!= 1 || dst
.regClass() == ctx
->program
->lane_mask
);
8967 bool logical
= !dst
.is_linear() || nir_dest_is_divergent(instr
->dest
);
8968 logical
|= ctx
->block
->kind
& block_kind_merge
;
8969 aco_opcode opcode
= logical
? aco_opcode::p_phi
: aco_opcode::p_linear_phi
;
8971 /* we want a sorted list of sources, since the predecessor list is also sorted */
8972 std::map
<unsigned, nir_ssa_def
*> phi_src
;
8973 nir_foreach_phi_src(src
, instr
)
8974 phi_src
[src
->pred
->index
] = src
->src
.ssa
;
8976 std::vector
<unsigned>& preds
= logical
? ctx
->block
->logical_preds
: ctx
->block
->linear_preds
;
8977 unsigned num_operands
= 0;
8978 Operand operands
[std::max(exec_list_length(&instr
->srcs
), (unsigned)preds
.size()) + 1];
8979 unsigned num_defined
= 0;
8980 unsigned cur_pred_idx
= 0;
8981 for (std::pair
<unsigned, nir_ssa_def
*> src
: phi_src
) {
8982 if (cur_pred_idx
< preds
.size()) {
8983 /* handle missing preds (IF merges with discard/break) and extra preds (loop exit with discard) */
8984 unsigned block
= ctx
->cf_info
.nir_to_aco
[src
.first
];
8985 unsigned skipped
= 0;
8986 while (cur_pred_idx
+ skipped
< preds
.size() && preds
[cur_pred_idx
+ skipped
] != block
)
8988 if (cur_pred_idx
+ skipped
< preds
.size()) {
8989 for (unsigned i
= 0; i
< skipped
; i
++)
8990 operands
[num_operands
++] = Operand(dst
.regClass());
8991 cur_pred_idx
+= skipped
;
8996 /* Handle missing predecessors at the end. This shouldn't happen with loop
8997 * headers and we can't ignore these sources for loop header phis. */
8998 if (!(ctx
->block
->kind
& block_kind_loop_header
) && cur_pred_idx
>= preds
.size())
9001 Operand op
= get_phi_operand(ctx
, src
.second
, dst
.regClass());
9002 operands
[num_operands
++] = op
;
9003 num_defined
+= !op
.isUndefined();
9005 /* handle block_kind_continue_or_break at loop exit blocks */
9006 while (cur_pred_idx
++ < preds
.size())
9007 operands
[num_operands
++] = Operand(dst
.regClass());
9009 /* If the loop ends with a break, still add a linear continue edge in case
9010 * that break is divergent or continue_or_break is used. We'll either remove
9011 * this operand later in visit_loop() if it's not necessary or replace the
9012 * undef with something correct. */
9013 if (!logical
&& ctx
->block
->kind
& block_kind_loop_header
) {
9014 nir_loop
*loop
= nir_cf_node_as_loop(instr
->instr
.block
->cf_node
.parent
);
9015 nir_block
*last
= nir_loop_last_block(loop
);
9016 if (last
->successors
[0] != instr
->instr
.block
)
9017 operands
[num_operands
++] = Operand(RegClass());
9020 if (num_defined
== 0) {
9021 Builder
bld(ctx
->program
, ctx
->block
);
9022 if (dst
.regClass() == s1
) {
9023 bld
.sop1(aco_opcode::s_mov_b32
, Definition(dst
), Operand(0u));
9024 } else if (dst
.regClass() == v1
) {
9025 bld
.vop1(aco_opcode::v_mov_b32
, Definition(dst
), Operand(0u));
9027 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, dst
.size(), 1)};
9028 for (unsigned i
= 0; i
< dst
.size(); i
++)
9029 vec
->operands
[i
] = Operand(0u);
9030 vec
->definitions
[0] = Definition(dst
);
9031 ctx
->block
->instructions
.emplace_back(std::move(vec
));
9036 /* we can use a linear phi in some cases if one src is undef */
9037 if (dst
.is_linear() && ctx
->block
->kind
& block_kind_merge
&& num_defined
== 1) {
9038 phi
.reset(create_instruction
<Pseudo_instruction
>(aco_opcode::p_linear_phi
, Format::PSEUDO
, num_operands
, 1));
9040 Block
*linear_else
= &ctx
->program
->blocks
[ctx
->block
->linear_preds
[1]];
9041 Block
*invert
= &ctx
->program
->blocks
[linear_else
->linear_preds
[0]];
9042 assert(invert
->kind
& block_kind_invert
);
9044 unsigned then_block
= invert
->linear_preds
[0];
9046 Block
* insert_block
= NULL
;
9047 for (unsigned i
= 0; i
< num_operands
; i
++) {
9048 Operand op
= operands
[i
];
9049 if (op
.isUndefined())
9051 insert_block
= ctx
->block
->logical_preds
[i
] == then_block
? invert
: ctx
->block
;
9052 phi
->operands
[0] = op
;
9055 assert(insert_block
); /* should be handled by the "num_defined == 0" case above */
9056 phi
->operands
[1] = Operand(dst
.regClass());
9057 phi
->definitions
[0] = Definition(dst
);
9058 insert_block
->instructions
.emplace(insert_block
->instructions
.begin(), std::move(phi
));
9062 /* try to scalarize vector phis */
9063 if (instr
->dest
.ssa
.bit_size
!= 1 && dst
.size() > 1) {
9064 // TODO: scalarize linear phis on divergent ifs
9065 bool can_scalarize
= (opcode
== aco_opcode::p_phi
|| !(ctx
->block
->kind
& block_kind_merge
));
9066 std::array
<Temp
, NIR_MAX_VEC_COMPONENTS
> new_vec
;
9067 for (unsigned i
= 0; can_scalarize
&& (i
< num_operands
); i
++) {
9068 Operand src
= operands
[i
];
9069 if (src
.isTemp() && ctx
->allocated_vec
.find(src
.tempId()) == ctx
->allocated_vec
.end())
9070 can_scalarize
= false;
9072 if (can_scalarize
) {
9073 unsigned num_components
= instr
->dest
.ssa
.num_components
;
9074 assert(dst
.size() % num_components
== 0);
9075 RegClass rc
= RegClass(dst
.type(), dst
.size() / num_components
);
9077 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, num_components
, 1)};
9078 for (unsigned k
= 0; k
< num_components
; k
++) {
9079 phi
.reset(create_instruction
<Pseudo_instruction
>(opcode
, Format::PSEUDO
, num_operands
, 1));
9080 for (unsigned i
= 0; i
< num_operands
; i
++) {
9081 Operand src
= operands
[i
];
9082 phi
->operands
[i
] = src
.isTemp() ? Operand(ctx
->allocated_vec
[src
.tempId()][k
]) : Operand(rc
);
9084 Temp phi_dst
= {ctx
->program
->allocateId(), rc
};
9085 phi
->definitions
[0] = Definition(phi_dst
);
9086 ctx
->block
->instructions
.emplace(ctx
->block
->instructions
.begin(), std::move(phi
));
9087 new_vec
[k
] = phi_dst
;
9088 vec
->operands
[k
] = Operand(phi_dst
);
9090 vec
->definitions
[0] = Definition(dst
);
9091 ctx
->block
->instructions
.emplace_back(std::move(vec
));
9092 ctx
->allocated_vec
.emplace(dst
.id(), new_vec
);
9097 phi
.reset(create_instruction
<Pseudo_instruction
>(opcode
, Format::PSEUDO
, num_operands
, 1));
9098 for (unsigned i
= 0; i
< num_operands
; i
++)
9099 phi
->operands
[i
] = operands
[i
];
9100 phi
->definitions
[0] = Definition(dst
);
9101 ctx
->block
->instructions
.emplace(ctx
->block
->instructions
.begin(), std::move(phi
));
9105 void visit_undef(isel_context
*ctx
, nir_ssa_undef_instr
*instr
)
9107 Temp dst
= get_ssa_temp(ctx
, &instr
->def
);
9109 assert(dst
.type() == RegType::sgpr
);
9111 if (dst
.size() == 1) {
9112 Builder(ctx
->program
, ctx
->block
).copy(Definition(dst
), Operand(0u));
9114 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, dst
.size(), 1)};
9115 for (unsigned i
= 0; i
< dst
.size(); i
++)
9116 vec
->operands
[i
] = Operand(0u);
9117 vec
->definitions
[0] = Definition(dst
);
9118 ctx
->block
->instructions
.emplace_back(std::move(vec
));
9122 void visit_jump(isel_context
*ctx
, nir_jump_instr
*instr
)
9124 Builder
bld(ctx
->program
, ctx
->block
);
9125 Block
*logical_target
;
9126 append_logical_end(ctx
->block
);
9127 unsigned idx
= ctx
->block
->index
;
9129 switch (instr
->type
) {
9130 case nir_jump_break
:
9131 logical_target
= ctx
->cf_info
.parent_loop
.exit
;
9132 add_logical_edge(idx
, logical_target
);
9133 ctx
->block
->kind
|= block_kind_break
;
9135 if (!ctx
->cf_info
.parent_if
.is_divergent
&&
9136 !ctx
->cf_info
.parent_loop
.has_divergent_continue
) {
9137 /* uniform break - directly jump out of the loop */
9138 ctx
->block
->kind
|= block_kind_uniform
;
9139 ctx
->cf_info
.has_branch
= true;
9140 bld
.branch(aco_opcode::p_branch
);
9141 add_linear_edge(idx
, logical_target
);
9144 ctx
->cf_info
.parent_loop
.has_divergent_branch
= true;
9145 ctx
->cf_info
.nir_to_aco
[instr
->instr
.block
->index
] = ctx
->block
->index
;
9147 case nir_jump_continue
:
9148 logical_target
= &ctx
->program
->blocks
[ctx
->cf_info
.parent_loop
.header_idx
];
9149 add_logical_edge(idx
, logical_target
);
9150 ctx
->block
->kind
|= block_kind_continue
;
9152 if (ctx
->cf_info
.parent_if
.is_divergent
) {
9153 /* for potential uniform breaks after this continue,
9154 we must ensure that they are handled correctly */
9155 ctx
->cf_info
.parent_loop
.has_divergent_continue
= true;
9156 ctx
->cf_info
.parent_loop
.has_divergent_branch
= true;
9157 ctx
->cf_info
.nir_to_aco
[instr
->instr
.block
->index
] = ctx
->block
->index
;
9159 /* uniform continue - directly jump to the loop header */
9160 ctx
->block
->kind
|= block_kind_uniform
;
9161 ctx
->cf_info
.has_branch
= true;
9162 bld
.branch(aco_opcode::p_branch
);
9163 add_linear_edge(idx
, logical_target
);
9168 fprintf(stderr
, "Unknown NIR jump instr: ");
9169 nir_print_instr(&instr
->instr
, stderr
);
9170 fprintf(stderr
, "\n");
9174 if (ctx
->cf_info
.parent_if
.is_divergent
&& !ctx
->cf_info
.exec_potentially_empty_break
) {
9175 ctx
->cf_info
.exec_potentially_empty_break
= true;
9176 ctx
->cf_info
.exec_potentially_empty_break_depth
= ctx
->cf_info
.loop_nest_depth
;
9179 /* remove critical edges from linear CFG */
9180 bld
.branch(aco_opcode::p_branch
);
9181 Block
* break_block
= ctx
->program
->create_and_insert_block();
9182 break_block
->loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
9183 break_block
->kind
|= block_kind_uniform
;
9184 add_linear_edge(idx
, break_block
);
9185 /* the loop_header pointer might be invalidated by this point */
9186 if (instr
->type
== nir_jump_continue
)
9187 logical_target
= &ctx
->program
->blocks
[ctx
->cf_info
.parent_loop
.header_idx
];
9188 add_linear_edge(break_block
->index
, logical_target
);
9189 bld
.reset(break_block
);
9190 bld
.branch(aco_opcode::p_branch
);
9192 Block
* continue_block
= ctx
->program
->create_and_insert_block();
9193 continue_block
->loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
9194 add_linear_edge(idx
, continue_block
);
9195 append_logical_start(continue_block
);
9196 ctx
->block
= continue_block
;
9200 void visit_block(isel_context
*ctx
, nir_block
*block
)
9202 nir_foreach_instr(instr
, block
) {
9203 switch (instr
->type
) {
9204 case nir_instr_type_alu
:
9205 visit_alu_instr(ctx
, nir_instr_as_alu(instr
));
9207 case nir_instr_type_load_const
:
9208 visit_load_const(ctx
, nir_instr_as_load_const(instr
));
9210 case nir_instr_type_intrinsic
:
9211 visit_intrinsic(ctx
, nir_instr_as_intrinsic(instr
));
9213 case nir_instr_type_tex
:
9214 visit_tex(ctx
, nir_instr_as_tex(instr
));
9216 case nir_instr_type_phi
:
9217 visit_phi(ctx
, nir_instr_as_phi(instr
));
9219 case nir_instr_type_ssa_undef
:
9220 visit_undef(ctx
, nir_instr_as_ssa_undef(instr
));
9222 case nir_instr_type_deref
:
9224 case nir_instr_type_jump
:
9225 visit_jump(ctx
, nir_instr_as_jump(instr
));
9228 fprintf(stderr
, "Unknown NIR instr type: ");
9229 nir_print_instr(instr
, stderr
);
9230 fprintf(stderr
, "\n");
9235 if (!ctx
->cf_info
.parent_loop
.has_divergent_branch
)
9236 ctx
->cf_info
.nir_to_aco
[block
->index
] = ctx
->block
->index
;
9241 static Operand
create_continue_phis(isel_context
*ctx
, unsigned first
, unsigned last
,
9242 aco_ptr
<Instruction
>& header_phi
, Operand
*vals
)
9244 vals
[0] = Operand(header_phi
->definitions
[0].getTemp());
9245 RegClass rc
= vals
[0].regClass();
9247 unsigned loop_nest_depth
= ctx
->program
->blocks
[first
].loop_nest_depth
;
9249 unsigned next_pred
= 1;
9251 for (unsigned idx
= first
+ 1; idx
<= last
; idx
++) {
9252 Block
& block
= ctx
->program
->blocks
[idx
];
9253 if (block
.loop_nest_depth
!= loop_nest_depth
) {
9254 vals
[idx
- first
] = vals
[idx
- 1 - first
];
9258 if (block
.kind
& block_kind_continue
) {
9259 vals
[idx
- first
] = header_phi
->operands
[next_pred
];
9264 bool all_same
= true;
9265 for (unsigned i
= 1; all_same
&& (i
< block
.linear_preds
.size()); i
++)
9266 all_same
= vals
[block
.linear_preds
[i
] - first
] == vals
[block
.linear_preds
[0] - first
];
9270 val
= vals
[block
.linear_preds
[0] - first
];
9272 aco_ptr
<Instruction
> phi(create_instruction
<Pseudo_instruction
>(
9273 aco_opcode::p_linear_phi
, Format::PSEUDO
, block
.linear_preds
.size(), 1));
9274 for (unsigned i
= 0; i
< block
.linear_preds
.size(); i
++)
9275 phi
->operands
[i
] = vals
[block
.linear_preds
[i
] - first
];
9276 val
= Operand(Temp(ctx
->program
->allocateId(), rc
));
9277 phi
->definitions
[0] = Definition(val
.getTemp());
9278 block
.instructions
.emplace(block
.instructions
.begin(), std::move(phi
));
9280 vals
[idx
- first
] = val
;
9283 return vals
[last
- first
];
9286 static void visit_loop(isel_context
*ctx
, nir_loop
*loop
)
9288 //TODO: we might want to wrap the loop around a branch if exec_potentially_empty=true
9289 append_logical_end(ctx
->block
);
9290 ctx
->block
->kind
|= block_kind_loop_preheader
| block_kind_uniform
;
9291 Builder
bld(ctx
->program
, ctx
->block
);
9292 bld
.branch(aco_opcode::p_branch
);
9293 unsigned loop_preheader_idx
= ctx
->block
->index
;
9295 Block loop_exit
= Block();
9296 loop_exit
.loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
9297 loop_exit
.kind
|= (block_kind_loop_exit
| (ctx
->block
->kind
& block_kind_top_level
));
9299 Block
* loop_header
= ctx
->program
->create_and_insert_block();
9300 loop_header
->loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
+ 1;
9301 loop_header
->kind
|= block_kind_loop_header
;
9302 add_edge(loop_preheader_idx
, loop_header
);
9303 ctx
->block
= loop_header
;
9305 /* emit loop body */
9306 unsigned loop_header_idx
= loop_header
->index
;
9307 loop_info_RAII
loop_raii(ctx
, loop_header_idx
, &loop_exit
);
9308 append_logical_start(ctx
->block
);
9309 bool unreachable
= visit_cf_list(ctx
, &loop
->body
);
9311 //TODO: what if a loop ends with a unconditional or uniformly branched continue and this branch is never taken?
9312 if (!ctx
->cf_info
.has_branch
) {
9313 append_logical_end(ctx
->block
);
9314 if (ctx
->cf_info
.exec_potentially_empty_discard
|| ctx
->cf_info
.exec_potentially_empty_break
) {
9315 /* Discards can result in code running with an empty exec mask.
9316 * This would result in divergent breaks not ever being taken. As a
9317 * workaround, break the loop when the loop mask is empty instead of
9318 * always continuing. */
9319 ctx
->block
->kind
|= (block_kind_continue_or_break
| block_kind_uniform
);
9320 unsigned block_idx
= ctx
->block
->index
;
9322 /* create helper blocks to avoid critical edges */
9323 Block
*break_block
= ctx
->program
->create_and_insert_block();
9324 break_block
->loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
9325 break_block
->kind
= block_kind_uniform
;
9326 bld
.reset(break_block
);
9327 bld
.branch(aco_opcode::p_branch
);
9328 add_linear_edge(block_idx
, break_block
);
9329 add_linear_edge(break_block
->index
, &loop_exit
);
9331 Block
*continue_block
= ctx
->program
->create_and_insert_block();
9332 continue_block
->loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
9333 continue_block
->kind
= block_kind_uniform
;
9334 bld
.reset(continue_block
);
9335 bld
.branch(aco_opcode::p_branch
);
9336 add_linear_edge(block_idx
, continue_block
);
9337 add_linear_edge(continue_block
->index
, &ctx
->program
->blocks
[loop_header_idx
]);
9339 if (!ctx
->cf_info
.parent_loop
.has_divergent_branch
)
9340 add_logical_edge(block_idx
, &ctx
->program
->blocks
[loop_header_idx
]);
9341 ctx
->block
= &ctx
->program
->blocks
[block_idx
];
9343 ctx
->block
->kind
|= (block_kind_continue
| block_kind_uniform
);
9344 if (!ctx
->cf_info
.parent_loop
.has_divergent_branch
)
9345 add_edge(ctx
->block
->index
, &ctx
->program
->blocks
[loop_header_idx
]);
9347 add_linear_edge(ctx
->block
->index
, &ctx
->program
->blocks
[loop_header_idx
]);
9350 bld
.reset(ctx
->block
);
9351 bld
.branch(aco_opcode::p_branch
);
9354 /* Fixup phis in loop header from unreachable blocks.
9355 * has_branch/has_divergent_branch also indicates if the loop ends with a
9356 * break/continue instruction, but we don't emit those if unreachable=true */
9358 assert(ctx
->cf_info
.has_branch
|| ctx
->cf_info
.parent_loop
.has_divergent_branch
);
9359 bool linear
= ctx
->cf_info
.has_branch
;
9360 bool logical
= ctx
->cf_info
.has_branch
|| ctx
->cf_info
.parent_loop
.has_divergent_branch
;
9361 for (aco_ptr
<Instruction
>& instr
: ctx
->program
->blocks
[loop_header_idx
].instructions
) {
9362 if ((logical
&& instr
->opcode
== aco_opcode::p_phi
) ||
9363 (linear
&& instr
->opcode
== aco_opcode::p_linear_phi
)) {
9364 /* the last operand should be the one that needs to be removed */
9365 instr
->operands
.pop_back();
9366 } else if (!is_phi(instr
)) {
9372 /* Fixup linear phis in loop header from expecting a continue. Both this fixup
9373 * and the previous one shouldn't both happen at once because a break in the
9374 * merge block would get CSE'd */
9375 if (nir_loop_last_block(loop
)->successors
[0] != nir_loop_first_block(loop
)) {
9376 unsigned num_vals
= ctx
->cf_info
.has_branch
? 1 : (ctx
->block
->index
- loop_header_idx
+ 1);
9377 Operand vals
[num_vals
];
9378 for (aco_ptr
<Instruction
>& instr
: ctx
->program
->blocks
[loop_header_idx
].instructions
) {
9379 if (instr
->opcode
== aco_opcode::p_linear_phi
) {
9380 if (ctx
->cf_info
.has_branch
)
9381 instr
->operands
.pop_back();
9383 instr
->operands
.back() = create_continue_phis(ctx
, loop_header_idx
, ctx
->block
->index
, instr
, vals
);
9384 } else if (!is_phi(instr
)) {
9390 ctx
->cf_info
.has_branch
= false;
9392 // TODO: if the loop has not a single exit, we must add one °°
9393 /* emit loop successor block */
9394 ctx
->block
= ctx
->program
->insert_block(std::move(loop_exit
));
9395 append_logical_start(ctx
->block
);
9398 // TODO: check if it is beneficial to not branch on continues
9399 /* trim linear phis in loop header */
9400 for (auto&& instr
: loop_entry
->instructions
) {
9401 if (instr
->opcode
== aco_opcode::p_linear_phi
) {
9402 aco_ptr
<Pseudo_instruction
> new_phi
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_linear_phi
, Format::PSEUDO
, loop_entry
->linear_predecessors
.size(), 1)};
9403 new_phi
->definitions
[0] = instr
->definitions
[0];
9404 for (unsigned i
= 0; i
< new_phi
->operands
.size(); i
++)
9405 new_phi
->operands
[i
] = instr
->operands
[i
];
9406 /* check that the remaining operands are all the same */
9407 for (unsigned i
= new_phi
->operands
.size(); i
< instr
->operands
.size(); i
++)
9408 assert(instr
->operands
[i
].tempId() == instr
->operands
.back().tempId());
9409 instr
.swap(new_phi
);
9410 } else if (instr
->opcode
== aco_opcode::p_phi
) {
9419 static void begin_divergent_if_then(isel_context
*ctx
, if_context
*ic
, Temp cond
)
9423 append_logical_end(ctx
->block
);
9424 ctx
->block
->kind
|= block_kind_branch
;
9426 /* branch to linear then block */
9427 assert(cond
.regClass() == ctx
->program
->lane_mask
);
9428 aco_ptr
<Pseudo_branch_instruction
> branch
;
9429 branch
.reset(create_instruction
<Pseudo_branch_instruction
>(aco_opcode::p_cbranch_z
, Format::PSEUDO_BRANCH
, 1, 0));
9430 branch
->operands
[0] = Operand(cond
);
9431 ctx
->block
->instructions
.push_back(std::move(branch
));
9433 ic
->BB_if_idx
= ctx
->block
->index
;
9434 ic
->BB_invert
= Block();
9435 ic
->BB_invert
.loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
9436 /* Invert blocks are intentionally not marked as top level because they
9437 * are not part of the logical cfg. */
9438 ic
->BB_invert
.kind
|= block_kind_invert
;
9439 ic
->BB_endif
= Block();
9440 ic
->BB_endif
.loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
9441 ic
->BB_endif
.kind
|= (block_kind_merge
| (ctx
->block
->kind
& block_kind_top_level
));
9443 ic
->exec_potentially_empty_discard_old
= ctx
->cf_info
.exec_potentially_empty_discard
;
9444 ic
->exec_potentially_empty_break_old
= ctx
->cf_info
.exec_potentially_empty_break
;
9445 ic
->exec_potentially_empty_break_depth_old
= ctx
->cf_info
.exec_potentially_empty_break_depth
;
9446 ic
->divergent_old
= ctx
->cf_info
.parent_if
.is_divergent
;
9447 ctx
->cf_info
.parent_if
.is_divergent
= true;
9449 /* divergent branches use cbranch_execz */
9450 ctx
->cf_info
.exec_potentially_empty_discard
= false;
9451 ctx
->cf_info
.exec_potentially_empty_break
= false;
9452 ctx
->cf_info
.exec_potentially_empty_break_depth
= UINT16_MAX
;
9454 /** emit logical then block */
9455 Block
* BB_then_logical
= ctx
->program
->create_and_insert_block();
9456 BB_then_logical
->loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
9457 add_edge(ic
->BB_if_idx
, BB_then_logical
);
9458 ctx
->block
= BB_then_logical
;
9459 append_logical_start(BB_then_logical
);
9462 static void begin_divergent_if_else(isel_context
*ctx
, if_context
*ic
)
9464 Block
*BB_then_logical
= ctx
->block
;
9465 append_logical_end(BB_then_logical
);
9466 /* branch from logical then block to invert block */
9467 aco_ptr
<Pseudo_branch_instruction
> branch
;
9468 branch
.reset(create_instruction
<Pseudo_branch_instruction
>(aco_opcode::p_branch
, Format::PSEUDO_BRANCH
, 0, 0));
9469 BB_then_logical
->instructions
.emplace_back(std::move(branch
));
9470 add_linear_edge(BB_then_logical
->index
, &ic
->BB_invert
);
9471 if (!ctx
->cf_info
.parent_loop
.has_divergent_branch
)
9472 add_logical_edge(BB_then_logical
->index
, &ic
->BB_endif
);
9473 BB_then_logical
->kind
|= block_kind_uniform
;
9474 assert(!ctx
->cf_info
.has_branch
);
9475 ic
->then_branch_divergent
= ctx
->cf_info
.parent_loop
.has_divergent_branch
;
9476 ctx
->cf_info
.parent_loop
.has_divergent_branch
= false;
9478 /** emit linear then block */
9479 Block
* BB_then_linear
= ctx
->program
->create_and_insert_block();
9480 BB_then_linear
->loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
9481 BB_then_linear
->kind
|= block_kind_uniform
;
9482 add_linear_edge(ic
->BB_if_idx
, BB_then_linear
);
9483 /* branch from linear then block to invert block */
9484 branch
.reset(create_instruction
<Pseudo_branch_instruction
>(aco_opcode::p_branch
, Format::PSEUDO_BRANCH
, 0, 0));
9485 BB_then_linear
->instructions
.emplace_back(std::move(branch
));
9486 add_linear_edge(BB_then_linear
->index
, &ic
->BB_invert
);
9488 /** emit invert merge block */
9489 ctx
->block
= ctx
->program
->insert_block(std::move(ic
->BB_invert
));
9490 ic
->invert_idx
= ctx
->block
->index
;
9492 /* branch to linear else block (skip else) */
9493 branch
.reset(create_instruction
<Pseudo_branch_instruction
>(aco_opcode::p_cbranch_nz
, Format::PSEUDO_BRANCH
, 1, 0));
9494 branch
->operands
[0] = Operand(ic
->cond
);
9495 ctx
->block
->instructions
.push_back(std::move(branch
));
9497 ic
->exec_potentially_empty_discard_old
|= ctx
->cf_info
.exec_potentially_empty_discard
;
9498 ic
->exec_potentially_empty_break_old
|= ctx
->cf_info
.exec_potentially_empty_break
;
9499 ic
->exec_potentially_empty_break_depth_old
=
9500 std::min(ic
->exec_potentially_empty_break_depth_old
, ctx
->cf_info
.exec_potentially_empty_break_depth
);
9501 /* divergent branches use cbranch_execz */
9502 ctx
->cf_info
.exec_potentially_empty_discard
= false;
9503 ctx
->cf_info
.exec_potentially_empty_break
= false;
9504 ctx
->cf_info
.exec_potentially_empty_break_depth
= UINT16_MAX
;
9506 /** emit logical else block */
9507 Block
* BB_else_logical
= ctx
->program
->create_and_insert_block();
9508 BB_else_logical
->loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
9509 add_logical_edge(ic
->BB_if_idx
, BB_else_logical
);
9510 add_linear_edge(ic
->invert_idx
, BB_else_logical
);
9511 ctx
->block
= BB_else_logical
;
9512 append_logical_start(BB_else_logical
);
9515 static void end_divergent_if(isel_context
*ctx
, if_context
*ic
)
9517 Block
*BB_else_logical
= ctx
->block
;
9518 append_logical_end(BB_else_logical
);
9520 /* branch from logical else block to endif block */
9521 aco_ptr
<Pseudo_branch_instruction
> branch
;
9522 branch
.reset(create_instruction
<Pseudo_branch_instruction
>(aco_opcode::p_branch
, Format::PSEUDO_BRANCH
, 0, 0));
9523 BB_else_logical
->instructions
.emplace_back(std::move(branch
));
9524 add_linear_edge(BB_else_logical
->index
, &ic
->BB_endif
);
9525 if (!ctx
->cf_info
.parent_loop
.has_divergent_branch
)
9526 add_logical_edge(BB_else_logical
->index
, &ic
->BB_endif
);
9527 BB_else_logical
->kind
|= block_kind_uniform
;
9529 assert(!ctx
->cf_info
.has_branch
);
9530 ctx
->cf_info
.parent_loop
.has_divergent_branch
&= ic
->then_branch_divergent
;
9533 /** emit linear else block */
9534 Block
* BB_else_linear
= ctx
->program
->create_and_insert_block();
9535 BB_else_linear
->loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
9536 BB_else_linear
->kind
|= block_kind_uniform
;
9537 add_linear_edge(ic
->invert_idx
, BB_else_linear
);
9539 /* branch from linear else block to endif block */
9540 branch
.reset(create_instruction
<Pseudo_branch_instruction
>(aco_opcode::p_branch
, Format::PSEUDO_BRANCH
, 0, 0));
9541 BB_else_linear
->instructions
.emplace_back(std::move(branch
));
9542 add_linear_edge(BB_else_linear
->index
, &ic
->BB_endif
);
9545 /** emit endif merge block */
9546 ctx
->block
= ctx
->program
->insert_block(std::move(ic
->BB_endif
));
9547 append_logical_start(ctx
->block
);
9550 ctx
->cf_info
.parent_if
.is_divergent
= ic
->divergent_old
;
9551 ctx
->cf_info
.exec_potentially_empty_discard
|= ic
->exec_potentially_empty_discard_old
;
9552 ctx
->cf_info
.exec_potentially_empty_break
|= ic
->exec_potentially_empty_break_old
;
9553 ctx
->cf_info
.exec_potentially_empty_break_depth
=
9554 std::min(ic
->exec_potentially_empty_break_depth_old
, ctx
->cf_info
.exec_potentially_empty_break_depth
);
9555 if (ctx
->cf_info
.loop_nest_depth
== ctx
->cf_info
.exec_potentially_empty_break_depth
&&
9556 !ctx
->cf_info
.parent_if
.is_divergent
) {
9557 ctx
->cf_info
.exec_potentially_empty_break
= false;
9558 ctx
->cf_info
.exec_potentially_empty_break_depth
= UINT16_MAX
;
9560 /* uniform control flow never has an empty exec-mask */
9561 if (!ctx
->cf_info
.loop_nest_depth
&& !ctx
->cf_info
.parent_if
.is_divergent
) {
9562 ctx
->cf_info
.exec_potentially_empty_discard
= false;
9563 ctx
->cf_info
.exec_potentially_empty_break
= false;
9564 ctx
->cf_info
.exec_potentially_empty_break_depth
= UINT16_MAX
;
9568 static void begin_uniform_if_then(isel_context
*ctx
, if_context
*ic
, Temp cond
)
9570 assert(cond
.regClass() == s1
);
9572 append_logical_end(ctx
->block
);
9573 ctx
->block
->kind
|= block_kind_uniform
;
9575 aco_ptr
<Pseudo_branch_instruction
> branch
;
9576 aco_opcode branch_opcode
= aco_opcode::p_cbranch_z
;
9577 branch
.reset(create_instruction
<Pseudo_branch_instruction
>(branch_opcode
, Format::PSEUDO_BRANCH
, 1, 0));
9578 branch
->operands
[0] = Operand(cond
);
9579 branch
->operands
[0].setFixed(scc
);
9580 ctx
->block
->instructions
.emplace_back(std::move(branch
));
9582 ic
->BB_if_idx
= ctx
->block
->index
;
9583 ic
->BB_endif
= Block();
9584 ic
->BB_endif
.loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
9585 ic
->BB_endif
.kind
|= ctx
->block
->kind
& block_kind_top_level
;
9587 ctx
->cf_info
.has_branch
= false;
9588 ctx
->cf_info
.parent_loop
.has_divergent_branch
= false;
9590 /** emit then block */
9591 Block
* BB_then
= ctx
->program
->create_and_insert_block();
9592 BB_then
->loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
9593 add_edge(ic
->BB_if_idx
, BB_then
);
9594 append_logical_start(BB_then
);
9595 ctx
->block
= BB_then
;
9598 static void begin_uniform_if_else(isel_context
*ctx
, if_context
*ic
)
9600 Block
*BB_then
= ctx
->block
;
9602 ic
->uniform_has_then_branch
= ctx
->cf_info
.has_branch
;
9603 ic
->then_branch_divergent
= ctx
->cf_info
.parent_loop
.has_divergent_branch
;
9605 if (!ic
->uniform_has_then_branch
) {
9606 append_logical_end(BB_then
);
9607 /* branch from then block to endif block */
9608 aco_ptr
<Pseudo_branch_instruction
> branch
;
9609 branch
.reset(create_instruction
<Pseudo_branch_instruction
>(aco_opcode::p_branch
, Format::PSEUDO_BRANCH
, 0, 0));
9610 BB_then
->instructions
.emplace_back(std::move(branch
));
9611 add_linear_edge(BB_then
->index
, &ic
->BB_endif
);
9612 if (!ic
->then_branch_divergent
)
9613 add_logical_edge(BB_then
->index
, &ic
->BB_endif
);
9614 BB_then
->kind
|= block_kind_uniform
;
9617 ctx
->cf_info
.has_branch
= false;
9618 ctx
->cf_info
.parent_loop
.has_divergent_branch
= false;
9620 /** emit else block */
9621 Block
* BB_else
= ctx
->program
->create_and_insert_block();
9622 BB_else
->loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
9623 add_edge(ic
->BB_if_idx
, BB_else
);
9624 append_logical_start(BB_else
);
9625 ctx
->block
= BB_else
;
9628 static void end_uniform_if(isel_context
*ctx
, if_context
*ic
)
9630 Block
*BB_else
= ctx
->block
;
9632 if (!ctx
->cf_info
.has_branch
) {
9633 append_logical_end(BB_else
);
9634 /* branch from then block to endif block */
9635 aco_ptr
<Pseudo_branch_instruction
> branch
;
9636 branch
.reset(create_instruction
<Pseudo_branch_instruction
>(aco_opcode::p_branch
, Format::PSEUDO_BRANCH
, 0, 0));
9637 BB_else
->instructions
.emplace_back(std::move(branch
));
9638 add_linear_edge(BB_else
->index
, &ic
->BB_endif
);
9639 if (!ctx
->cf_info
.parent_loop
.has_divergent_branch
)
9640 add_logical_edge(BB_else
->index
, &ic
->BB_endif
);
9641 BB_else
->kind
|= block_kind_uniform
;
9644 ctx
->cf_info
.has_branch
&= ic
->uniform_has_then_branch
;
9645 ctx
->cf_info
.parent_loop
.has_divergent_branch
&= ic
->then_branch_divergent
;
9647 /** emit endif merge block */
9648 if (!ctx
->cf_info
.has_branch
) {
9649 ctx
->block
= ctx
->program
->insert_block(std::move(ic
->BB_endif
));
9650 append_logical_start(ctx
->block
);
9654 static bool visit_if(isel_context
*ctx
, nir_if
*if_stmt
)
9656 Temp cond
= get_ssa_temp(ctx
, if_stmt
->condition
.ssa
);
9657 Builder
bld(ctx
->program
, ctx
->block
);
9658 aco_ptr
<Pseudo_branch_instruction
> branch
;
9661 if (!nir_src_is_divergent(if_stmt
->condition
)) { /* uniform condition */
9663 * Uniform conditionals are represented in the following way*) :
9665 * The linear and logical CFG:
9668 * BB_THEN (logical) BB_ELSE (logical)
9672 * *) Exceptions may be due to break and continue statements within loops
9673 * If a break/continue happens within uniform control flow, it branches
9674 * to the loop exit/entry block. Otherwise, it branches to the next
9678 // TODO: in a post-RA optimizer, we could check if the condition is in VCC and omit this instruction
9679 assert(cond
.regClass() == ctx
->program
->lane_mask
);
9680 cond
= bool_to_scalar_condition(ctx
, cond
);
9682 begin_uniform_if_then(ctx
, &ic
, cond
);
9683 visit_cf_list(ctx
, &if_stmt
->then_list
);
9685 begin_uniform_if_else(ctx
, &ic
);
9686 visit_cf_list(ctx
, &if_stmt
->else_list
);
9688 end_uniform_if(ctx
, &ic
);
9689 } else { /* non-uniform condition */
9691 * To maintain a logical and linear CFG without critical edges,
9692 * non-uniform conditionals are represented in the following way*) :
9697 * BB_THEN (logical) BB_THEN (linear)
9699 * BB_INVERT (linear)
9701 * BB_ELSE (logical) BB_ELSE (linear)
9708 * BB_THEN (logical) BB_ELSE (logical)
9712 * *) Exceptions may be due to break and continue statements within loops
9715 begin_divergent_if_then(ctx
, &ic
, cond
);
9716 visit_cf_list(ctx
, &if_stmt
->then_list
);
9718 begin_divergent_if_else(ctx
, &ic
);
9719 visit_cf_list(ctx
, &if_stmt
->else_list
);
9721 end_divergent_if(ctx
, &ic
);
9724 return !ctx
->cf_info
.has_branch
&& !ctx
->block
->logical_preds
.empty();
9727 static bool visit_cf_list(isel_context
*ctx
,
9728 struct exec_list
*list
)
9730 foreach_list_typed(nir_cf_node
, node
, node
, list
) {
9731 switch (node
->type
) {
9732 case nir_cf_node_block
:
9733 visit_block(ctx
, nir_cf_node_as_block(node
));
9735 case nir_cf_node_if
:
9736 if (!visit_if(ctx
, nir_cf_node_as_if(node
)))
9739 case nir_cf_node_loop
:
9740 visit_loop(ctx
, nir_cf_node_as_loop(node
));
9743 unreachable("unimplemented cf list type");
9749 static void create_null_export(isel_context
*ctx
)
9751 /* Some shader stages always need to have exports.
9752 * So when there is none, we need to add a null export.
9755 unsigned dest
= (ctx
->program
->stage
& hw_fs
) ? 9 /* NULL */ : V_008DFC_SQ_EXP_POS
;
9756 bool vm
= (ctx
->program
->stage
& hw_fs
) || ctx
->program
->chip_class
>= GFX10
;
9757 Builder
bld(ctx
->program
, ctx
->block
);
9758 bld
.exp(aco_opcode::exp
, Operand(v1
), Operand(v1
), Operand(v1
), Operand(v1
),
9759 /* enabled_mask */ 0, dest
, /* compr */ false, /* done */ true, vm
);
9762 static bool export_vs_varying(isel_context
*ctx
, int slot
, bool is_pos
, int *next_pos
)
9764 assert(ctx
->stage
== vertex_vs
||
9765 ctx
->stage
== tess_eval_vs
||
9766 ctx
->stage
== gs_copy_vs
||
9767 ctx
->stage
== ngg_vertex_gs
||
9768 ctx
->stage
== ngg_tess_eval_gs
);
9770 int offset
= (ctx
->stage
& sw_tes
)
9771 ? ctx
->program
->info
->tes
.outinfo
.vs_output_param_offset
[slot
]
9772 : ctx
->program
->info
->vs
.outinfo
.vs_output_param_offset
[slot
];
9773 uint64_t mask
= ctx
->outputs
.mask
[slot
];
9774 if (!is_pos
&& !mask
)
9776 if (!is_pos
&& offset
== AC_EXP_PARAM_UNDEFINED
)
9778 aco_ptr
<Export_instruction
> exp
{create_instruction
<Export_instruction
>(aco_opcode::exp
, Format::EXP
, 4, 0)};
9779 exp
->enabled_mask
= mask
;
9780 for (unsigned i
= 0; i
< 4; ++i
) {
9781 if (mask
& (1 << i
))
9782 exp
->operands
[i
] = Operand(ctx
->outputs
.temps
[slot
* 4u + i
]);
9784 exp
->operands
[i
] = Operand(v1
);
9786 /* Navi10-14 skip POS0 exports if EXEC=0 and DONE=0, causing a hang.
9787 * Setting valid_mask=1 prevents it and has no other effect.
9789 exp
->valid_mask
= ctx
->options
->chip_class
>= GFX10
&& is_pos
&& *next_pos
== 0;
9791 exp
->compressed
= false;
9793 exp
->dest
= V_008DFC_SQ_EXP_POS
+ (*next_pos
)++;
9795 exp
->dest
= V_008DFC_SQ_EXP_PARAM
+ offset
;
9796 ctx
->block
->instructions
.emplace_back(std::move(exp
));
9801 static void export_vs_psiz_layer_viewport(isel_context
*ctx
, int *next_pos
)
9803 aco_ptr
<Export_instruction
> exp
{create_instruction
<Export_instruction
>(aco_opcode::exp
, Format::EXP
, 4, 0)};
9804 exp
->enabled_mask
= 0;
9805 for (unsigned i
= 0; i
< 4; ++i
)
9806 exp
->operands
[i
] = Operand(v1
);
9807 if (ctx
->outputs
.mask
[VARYING_SLOT_PSIZ
]) {
9808 exp
->operands
[0] = Operand(ctx
->outputs
.temps
[VARYING_SLOT_PSIZ
* 4u]);
9809 exp
->enabled_mask
|= 0x1;
9811 if (ctx
->outputs
.mask
[VARYING_SLOT_LAYER
]) {
9812 exp
->operands
[2] = Operand(ctx
->outputs
.temps
[VARYING_SLOT_LAYER
* 4u]);
9813 exp
->enabled_mask
|= 0x4;
9815 if (ctx
->outputs
.mask
[VARYING_SLOT_VIEWPORT
]) {
9816 if (ctx
->options
->chip_class
< GFX9
) {
9817 exp
->operands
[3] = Operand(ctx
->outputs
.temps
[VARYING_SLOT_VIEWPORT
* 4u]);
9818 exp
->enabled_mask
|= 0x8;
9820 Builder
bld(ctx
->program
, ctx
->block
);
9822 Temp out
= bld
.vop2(aco_opcode::v_lshlrev_b32
, bld
.def(v1
), Operand(16u),
9823 Operand(ctx
->outputs
.temps
[VARYING_SLOT_VIEWPORT
* 4u]));
9824 if (exp
->operands
[2].isTemp())
9825 out
= bld
.vop2(aco_opcode::v_or_b32
, bld
.def(v1
), Operand(out
), exp
->operands
[2]);
9827 exp
->operands
[2] = Operand(out
);
9828 exp
->enabled_mask
|= 0x4;
9831 exp
->valid_mask
= ctx
->options
->chip_class
>= GFX10
&& *next_pos
== 0;
9833 exp
->compressed
= false;
9834 exp
->dest
= V_008DFC_SQ_EXP_POS
+ (*next_pos
)++;
9835 ctx
->block
->instructions
.emplace_back(std::move(exp
));
9838 static void create_export_phis(isel_context
*ctx
)
9840 /* Used when exports are needed, but the output temps are defined in a preceding block.
9841 * This function will set up phis in order to access the outputs in the next block.
9844 assert(ctx
->block
->instructions
.back()->opcode
== aco_opcode::p_logical_start
);
9845 aco_ptr
<Instruction
> logical_start
= aco_ptr
<Instruction
>(ctx
->block
->instructions
.back().release());
9846 ctx
->block
->instructions
.pop_back();
9848 Builder
bld(ctx
->program
, ctx
->block
);
9850 for (unsigned slot
= 0; slot
<= VARYING_SLOT_VAR31
; ++slot
) {
9851 uint64_t mask
= ctx
->outputs
.mask
[slot
];
9852 for (unsigned i
= 0; i
< 4; ++i
) {
9853 if (!(mask
& (1 << i
)))
9856 Temp old
= ctx
->outputs
.temps
[slot
* 4 + i
];
9857 Temp phi
= bld
.pseudo(aco_opcode::p_phi
, bld
.def(v1
), old
, Operand(v1
));
9858 ctx
->outputs
.temps
[slot
* 4 + i
] = phi
;
9862 bld
.insert(std::move(logical_start
));
9865 static void create_vs_exports(isel_context
*ctx
)
9867 assert(ctx
->stage
== vertex_vs
||
9868 ctx
->stage
== tess_eval_vs
||
9869 ctx
->stage
== gs_copy_vs
||
9870 ctx
->stage
== ngg_vertex_gs
||
9871 ctx
->stage
== ngg_tess_eval_gs
);
9873 radv_vs_output_info
*outinfo
= (ctx
->stage
& sw_tes
)
9874 ? &ctx
->program
->info
->tes
.outinfo
9875 : &ctx
->program
->info
->vs
.outinfo
;
9877 if (outinfo
->export_prim_id
&& !(ctx
->stage
& hw_ngg_gs
)) {
9878 ctx
->outputs
.mask
[VARYING_SLOT_PRIMITIVE_ID
] |= 0x1;
9879 ctx
->outputs
.temps
[VARYING_SLOT_PRIMITIVE_ID
* 4u] = get_arg(ctx
, ctx
->args
->vs_prim_id
);
9882 if (ctx
->options
->key
.has_multiview_view_index
) {
9883 ctx
->outputs
.mask
[VARYING_SLOT_LAYER
] |= 0x1;
9884 ctx
->outputs
.temps
[VARYING_SLOT_LAYER
* 4u] = as_vgpr(ctx
, get_arg(ctx
, ctx
->args
->ac
.view_index
));
9887 /* the order these position exports are created is important */
9889 bool exported_pos
= export_vs_varying(ctx
, VARYING_SLOT_POS
, true, &next_pos
);
9890 if (outinfo
->writes_pointsize
|| outinfo
->writes_layer
|| outinfo
->writes_viewport_index
) {
9891 export_vs_psiz_layer_viewport(ctx
, &next_pos
);
9892 exported_pos
= true;
9894 if (ctx
->num_clip_distances
+ ctx
->num_cull_distances
> 0)
9895 exported_pos
|= export_vs_varying(ctx
, VARYING_SLOT_CLIP_DIST0
, true, &next_pos
);
9896 if (ctx
->num_clip_distances
+ ctx
->num_cull_distances
> 4)
9897 exported_pos
|= export_vs_varying(ctx
, VARYING_SLOT_CLIP_DIST1
, true, &next_pos
);
9899 if (ctx
->export_clip_dists
) {
9900 if (ctx
->num_clip_distances
+ ctx
->num_cull_distances
> 0)
9901 export_vs_varying(ctx
, VARYING_SLOT_CLIP_DIST0
, false, &next_pos
);
9902 if (ctx
->num_clip_distances
+ ctx
->num_cull_distances
> 4)
9903 export_vs_varying(ctx
, VARYING_SLOT_CLIP_DIST1
, false, &next_pos
);
9906 for (unsigned i
= 0; i
<= VARYING_SLOT_VAR31
; ++i
) {
9907 if (i
< VARYING_SLOT_VAR0
&&
9908 i
!= VARYING_SLOT_LAYER
&&
9909 i
!= VARYING_SLOT_PRIMITIVE_ID
&&
9910 i
!= VARYING_SLOT_VIEWPORT
)
9913 export_vs_varying(ctx
, i
, false, NULL
);
9917 create_null_export(ctx
);
9920 static bool export_fs_mrt_z(isel_context
*ctx
)
9922 Builder
bld(ctx
->program
, ctx
->block
);
9923 unsigned enabled_channels
= 0;
9927 for (unsigned i
= 0; i
< 4; ++i
) {
9928 values
[i
] = Operand(v1
);
9931 /* Both stencil and sample mask only need 16-bits. */
9932 if (!ctx
->program
->info
->ps
.writes_z
&&
9933 (ctx
->program
->info
->ps
.writes_stencil
||
9934 ctx
->program
->info
->ps
.writes_sample_mask
)) {
9935 compr
= true; /* COMPR flag */
9937 if (ctx
->program
->info
->ps
.writes_stencil
) {
9938 /* Stencil should be in X[23:16]. */
9939 values
[0] = Operand(ctx
->outputs
.temps
[FRAG_RESULT_STENCIL
* 4u]);
9940 values
[0] = bld
.vop2(aco_opcode::v_lshlrev_b32
, bld
.def(v1
), Operand(16u), values
[0]);
9941 enabled_channels
|= 0x3;
9944 if (ctx
->program
->info
->ps
.writes_sample_mask
) {
9945 /* SampleMask should be in Y[15:0]. */
9946 values
[1] = Operand(ctx
->outputs
.temps
[FRAG_RESULT_SAMPLE_MASK
* 4u]);
9947 enabled_channels
|= 0xc;
9950 if (ctx
->program
->info
->ps
.writes_z
) {
9951 values
[0] = Operand(ctx
->outputs
.temps
[FRAG_RESULT_DEPTH
* 4u]);
9952 enabled_channels
|= 0x1;
9955 if (ctx
->program
->info
->ps
.writes_stencil
) {
9956 values
[1] = Operand(ctx
->outputs
.temps
[FRAG_RESULT_STENCIL
* 4u]);
9957 enabled_channels
|= 0x2;
9960 if (ctx
->program
->info
->ps
.writes_sample_mask
) {
9961 values
[2] = Operand(ctx
->outputs
.temps
[FRAG_RESULT_SAMPLE_MASK
* 4u]);
9962 enabled_channels
|= 0x4;
9966 /* GFX6 (except OLAND and HAINAN) has a bug that it only looks at the X
9967 * writemask component.
9969 if (ctx
->options
->chip_class
== GFX6
&&
9970 ctx
->options
->family
!= CHIP_OLAND
&&
9971 ctx
->options
->family
!= CHIP_HAINAN
) {
9972 enabled_channels
|= 0x1;
9975 bld
.exp(aco_opcode::exp
, values
[0], values
[1], values
[2], values
[3],
9976 enabled_channels
, V_008DFC_SQ_EXP_MRTZ
, compr
);
9981 static bool export_fs_mrt_color(isel_context
*ctx
, int slot
)
9983 Builder
bld(ctx
->program
, ctx
->block
);
9984 unsigned write_mask
= ctx
->outputs
.mask
[slot
];
9987 for (unsigned i
= 0; i
< 4; ++i
) {
9988 if (write_mask
& (1 << i
)) {
9989 values
[i
] = Operand(ctx
->outputs
.temps
[slot
* 4u + i
]);
9991 values
[i
] = Operand(v1
);
9995 unsigned target
, col_format
;
9996 unsigned enabled_channels
= 0;
9997 aco_opcode compr_op
= (aco_opcode
)0;
9999 slot
-= FRAG_RESULT_DATA0
;
10000 target
= V_008DFC_SQ_EXP_MRT
+ slot
;
10001 col_format
= (ctx
->options
->key
.fs
.col_format
>> (4 * slot
)) & 0xf;
10003 bool is_int8
= (ctx
->options
->key
.fs
.is_int8
>> slot
) & 1;
10004 bool is_int10
= (ctx
->options
->key
.fs
.is_int10
>> slot
) & 1;
10005 bool is_16bit
= values
[0].regClass() == v2b
;
10007 switch (col_format
)
10009 case V_028714_SPI_SHADER_ZERO
:
10010 enabled_channels
= 0; /* writemask */
10011 target
= V_008DFC_SQ_EXP_NULL
;
10014 case V_028714_SPI_SHADER_32_R
:
10015 enabled_channels
= 1;
10018 case V_028714_SPI_SHADER_32_GR
:
10019 enabled_channels
= 0x3;
10022 case V_028714_SPI_SHADER_32_AR
:
10023 if (ctx
->options
->chip_class
>= GFX10
) {
10024 /* Special case: on GFX10, the outputs are different for 32_AR */
10025 enabled_channels
= 0x3;
10026 values
[1] = values
[3];
10027 values
[3] = Operand(v1
);
10029 enabled_channels
= 0x9;
10033 case V_028714_SPI_SHADER_FP16_ABGR
:
10034 enabled_channels
= 0x5;
10035 compr_op
= aco_opcode::v_cvt_pkrtz_f16_f32
;
10037 if (ctx
->options
->chip_class
>= GFX9
) {
10038 /* Pack the FP16 values together instead of converting them to
10039 * FP32 and back to FP16.
10040 * TODO: use p_create_vector and let the compiler optimizes.
10042 compr_op
= aco_opcode::v_pack_b32_f16
;
10044 for (unsigned i
= 0; i
< 4; i
++) {
10045 if ((write_mask
>> i
) & 1)
10046 values
[i
] = bld
.vop1(aco_opcode::v_cvt_f32_f16
, bld
.def(v1
), values
[i
]);
10052 case V_028714_SPI_SHADER_UNORM16_ABGR
:
10053 enabled_channels
= 0x5;
10054 if (is_16bit
&& ctx
->options
->chip_class
>= GFX9
) {
10055 compr_op
= aco_opcode::v_cvt_pknorm_u16_f16
;
10057 compr_op
= aco_opcode::v_cvt_pknorm_u16_f32
;
10061 case V_028714_SPI_SHADER_SNORM16_ABGR
:
10062 enabled_channels
= 0x5;
10063 if (is_16bit
&& ctx
->options
->chip_class
>= GFX9
) {
10064 compr_op
= aco_opcode::v_cvt_pknorm_i16_f16
;
10066 compr_op
= aco_opcode::v_cvt_pknorm_i16_f32
;
10070 case V_028714_SPI_SHADER_UINT16_ABGR
: {
10071 enabled_channels
= 0x5;
10072 compr_op
= aco_opcode::v_cvt_pk_u16_u32
;
10073 if (is_int8
|| is_int10
) {
10075 uint32_t max_rgb
= is_int8
? 255 : is_int10
? 1023 : 0;
10076 Temp max_rgb_val
= bld
.copy(bld
.def(s1
), Operand(max_rgb
));
10078 for (unsigned i
= 0; i
< 4; i
++) {
10079 if ((write_mask
>> i
) & 1) {
10080 values
[i
] = bld
.vop2(aco_opcode::v_min_u32
, bld
.def(v1
),
10081 i
== 3 && is_int10
? Operand(3u) : Operand(max_rgb_val
),
10085 } else if (is_16bit
) {
10086 for (unsigned i
= 0; i
< 4; i
++) {
10087 if ((write_mask
>> i
) & 1) {
10088 Temp tmp
= convert_int(ctx
, bld
, values
[i
].getTemp(), 16, 32, false);
10089 values
[i
] = Operand(tmp
);
10096 case V_028714_SPI_SHADER_SINT16_ABGR
:
10097 enabled_channels
= 0x5;
10098 compr_op
= aco_opcode::v_cvt_pk_i16_i32
;
10099 if (is_int8
|| is_int10
) {
10101 uint32_t max_rgb
= is_int8
? 127 : is_int10
? 511 : 0;
10102 uint32_t min_rgb
= is_int8
? -128 :is_int10
? -512 : 0;
10103 Temp max_rgb_val
= bld
.copy(bld
.def(s1
), Operand(max_rgb
));
10104 Temp min_rgb_val
= bld
.copy(bld
.def(s1
), Operand(min_rgb
));
10106 for (unsigned i
= 0; i
< 4; i
++) {
10107 if ((write_mask
>> i
) & 1) {
10108 values
[i
] = bld
.vop2(aco_opcode::v_min_i32
, bld
.def(v1
),
10109 i
== 3 && is_int10
? Operand(1u) : Operand(max_rgb_val
),
10111 values
[i
] = bld
.vop2(aco_opcode::v_max_i32
, bld
.def(v1
),
10112 i
== 3 && is_int10
? Operand(-2u) : Operand(min_rgb_val
),
10116 } else if (is_16bit
) {
10117 for (unsigned i
= 0; i
< 4; i
++) {
10118 if ((write_mask
>> i
) & 1) {
10119 Temp tmp
= convert_int(ctx
, bld
, values
[i
].getTemp(), 16, 32, true);
10120 values
[i
] = Operand(tmp
);
10126 case V_028714_SPI_SHADER_32_ABGR
:
10127 enabled_channels
= 0xF;
10134 if (target
== V_008DFC_SQ_EXP_NULL
)
10137 /* Replace NaN by zero (only 32-bit) to fix game bugs if requested. */
10138 if (ctx
->options
->enable_mrt_output_nan_fixup
&&
10140 (col_format
== V_028714_SPI_SHADER_32_R
||
10141 col_format
== V_028714_SPI_SHADER_32_GR
||
10142 col_format
== V_028714_SPI_SHADER_32_AR
||
10143 col_format
== V_028714_SPI_SHADER_32_ABGR
||
10144 col_format
== V_028714_SPI_SHADER_FP16_ABGR
)) {
10145 for (int i
= 0; i
< 4; i
++) {
10146 if (!(write_mask
& (1 << i
)))
10149 Temp isnan
= bld
.vopc(aco_opcode::v_cmp_class_f32
,
10150 bld
.hint_vcc(bld
.def(bld
.lm
)), values
[i
],
10151 bld
.copy(bld
.def(v1
), Operand(3u)));
10152 values
[i
] = bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), values
[i
],
10153 bld
.copy(bld
.def(v1
), Operand(0u)), isnan
);
10157 if ((bool) compr_op
) {
10158 for (int i
= 0; i
< 2; i
++) {
10159 /* check if at least one of the values to be compressed is enabled */
10160 unsigned enabled
= (write_mask
>> (i
*2) | write_mask
>> (i
*2+1)) & 0x1;
10162 enabled_channels
|= enabled
<< (i
*2);
10163 values
[i
] = bld
.vop3(compr_op
, bld
.def(v1
),
10164 values
[i
*2].isUndefined() ? Operand(0u) : values
[i
*2],
10165 values
[i
*2+1].isUndefined() ? Operand(0u): values
[i
*2+1]);
10167 values
[i
] = Operand(v1
);
10170 values
[2] = Operand(v1
);
10171 values
[3] = Operand(v1
);
10173 for (int i
= 0; i
< 4; i
++)
10174 values
[i
] = enabled_channels
& (1 << i
) ? values
[i
] : Operand(v1
);
10177 bld
.exp(aco_opcode::exp
, values
[0], values
[1], values
[2], values
[3],
10178 enabled_channels
, target
, (bool) compr_op
);
10182 static void create_fs_exports(isel_context
*ctx
)
10184 bool exported
= false;
10186 /* Export depth, stencil and sample mask. */
10187 if (ctx
->outputs
.mask
[FRAG_RESULT_DEPTH
] ||
10188 ctx
->outputs
.mask
[FRAG_RESULT_STENCIL
] ||
10189 ctx
->outputs
.mask
[FRAG_RESULT_SAMPLE_MASK
])
10190 exported
|= export_fs_mrt_z(ctx
);
10192 /* Export all color render targets. */
10193 for (unsigned i
= FRAG_RESULT_DATA0
; i
< FRAG_RESULT_DATA7
+ 1; ++i
)
10194 if (ctx
->outputs
.mask
[i
])
10195 exported
|= export_fs_mrt_color(ctx
, i
);
10198 create_null_export(ctx
);
10201 static void write_tcs_tess_factors(isel_context
*ctx
)
10203 unsigned outer_comps
;
10204 unsigned inner_comps
;
10206 switch (ctx
->args
->options
->key
.tcs
.primitive_mode
) {
10223 Builder
bld(ctx
->program
, ctx
->block
);
10225 bld
.barrier(aco_opcode::p_memory_barrier_shared
);
10226 if (unlikely(ctx
->program
->chip_class
!= GFX6
&& ctx
->program
->workgroup_size
> ctx
->program
->wave_size
))
10227 bld
.sopp(aco_opcode::s_barrier
);
10229 Temp tcs_rel_ids
= get_arg(ctx
, ctx
->args
->ac
.tcs_rel_ids
);
10230 Temp invocation_id
= bld
.vop3(aco_opcode::v_bfe_u32
, bld
.def(v1
), tcs_rel_ids
, Operand(8u), Operand(5u));
10232 Temp invocation_id_is_zero
= bld
.vopc(aco_opcode::v_cmp_eq_u32
, bld
.hint_vcc(bld
.def(bld
.lm
)), Operand(0u), invocation_id
);
10233 if_context ic_invocation_id_is_zero
;
10234 begin_divergent_if_then(ctx
, &ic_invocation_id_is_zero
, invocation_id_is_zero
);
10235 bld
.reset(ctx
->block
);
10237 Temp hs_ring_tess_factor
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), ctx
->program
->private_segment_buffer
, Operand(RING_HS_TESS_FACTOR
* 16u));
10239 std::pair
<Temp
, unsigned> lds_base
= get_tcs_output_lds_offset(ctx
);
10240 unsigned stride
= inner_comps
+ outer_comps
;
10241 unsigned lds_align
= calculate_lds_alignment(ctx
, lds_base
.second
);
10245 assert(stride
<= (sizeof(out
) / sizeof(Temp
)));
10247 if (ctx
->args
->options
->key
.tcs
.primitive_mode
== GL_ISOLINES
) {
10249 tf_outer_vec
= load_lds(ctx
, 4, bld
.tmp(v2
), lds_base
.first
, lds_base
.second
+ ctx
->tcs_tess_lvl_out_loc
, lds_align
);
10250 out
[1] = emit_extract_vector(ctx
, tf_outer_vec
, 0, v1
);
10251 out
[0] = emit_extract_vector(ctx
, tf_outer_vec
, 1, v1
);
10253 tf_outer_vec
= load_lds(ctx
, 4, bld
.tmp(RegClass(RegType::vgpr
, outer_comps
)), lds_base
.first
, lds_base
.second
+ ctx
->tcs_tess_lvl_out_loc
, lds_align
);
10254 tf_inner_vec
= load_lds(ctx
, 4, bld
.tmp(RegClass(RegType::vgpr
, inner_comps
)), lds_base
.first
, lds_base
.second
+ ctx
->tcs_tess_lvl_in_loc
, lds_align
);
10256 for (unsigned i
= 0; i
< outer_comps
; ++i
)
10257 out
[i
] = emit_extract_vector(ctx
, tf_outer_vec
, i
, v1
);
10258 for (unsigned i
= 0; i
< inner_comps
; ++i
)
10259 out
[outer_comps
+ i
] = emit_extract_vector(ctx
, tf_inner_vec
, i
, v1
);
10262 Temp rel_patch_id
= get_tess_rel_patch_id(ctx
);
10263 Temp tf_base
= get_arg(ctx
, ctx
->args
->tess_factor_offset
);
10264 Temp byte_offset
= bld
.v_mul24_imm(bld
.def(v1
), rel_patch_id
, stride
* 4u);
10265 unsigned tf_const_offset
= 0;
10267 if (ctx
->program
->chip_class
<= GFX8
) {
10268 Temp rel_patch_id_is_zero
= bld
.vopc(aco_opcode::v_cmp_eq_u32
, bld
.hint_vcc(bld
.def(bld
.lm
)), Operand(0u), rel_patch_id
);
10269 if_context ic_rel_patch_id_is_zero
;
10270 begin_divergent_if_then(ctx
, &ic_rel_patch_id_is_zero
, rel_patch_id_is_zero
);
10271 bld
.reset(ctx
->block
);
10273 /* Store the dynamic HS control word. */
10274 Temp control_word
= bld
.copy(bld
.def(v1
), Operand(0x80000000u
));
10275 bld
.mubuf(aco_opcode::buffer_store_dword
,
10276 /* SRSRC */ hs_ring_tess_factor
, /* VADDR */ Operand(v1
), /* SOFFSET */ tf_base
, /* VDATA */ control_word
,
10277 /* immediate OFFSET */ 0, /* OFFEN */ false, /* idxen*/ false, /* addr64 */ false,
10278 /* disable_wqm */ false, /* glc */ true);
10279 tf_const_offset
+= 4;
10281 begin_divergent_if_else(ctx
, &ic_rel_patch_id_is_zero
);
10282 end_divergent_if(ctx
, &ic_rel_patch_id_is_zero
);
10283 bld
.reset(ctx
->block
);
10286 assert(stride
== 2 || stride
== 4 || stride
== 6);
10287 Temp tf_vec
= create_vec_from_array(ctx
, out
, stride
, RegType::vgpr
, 4u);
10288 store_vmem_mubuf(ctx
, tf_vec
, hs_ring_tess_factor
, byte_offset
, tf_base
, tf_const_offset
, 4, (1 << stride
) - 1, true, false);
10290 /* Store to offchip for TES to read - only if TES reads them */
10291 if (ctx
->args
->options
->key
.tcs
.tes_reads_tess_factors
) {
10292 Temp hs_ring_tess_offchip
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), ctx
->program
->private_segment_buffer
, Operand(RING_HS_TESS_OFFCHIP
* 16u));
10293 Temp oc_lds
= get_arg(ctx
, ctx
->args
->oc_lds
);
10295 std::pair
<Temp
, unsigned> vmem_offs_outer
= get_tcs_per_patch_output_vmem_offset(ctx
, nullptr, ctx
->tcs_tess_lvl_out_loc
);
10296 store_vmem_mubuf(ctx
, tf_outer_vec
, hs_ring_tess_offchip
, vmem_offs_outer
.first
, oc_lds
, vmem_offs_outer
.second
, 4, (1 << outer_comps
) - 1, true, false);
10298 if (likely(inner_comps
)) {
10299 std::pair
<Temp
, unsigned> vmem_offs_inner
= get_tcs_per_patch_output_vmem_offset(ctx
, nullptr, ctx
->tcs_tess_lvl_in_loc
);
10300 store_vmem_mubuf(ctx
, tf_inner_vec
, hs_ring_tess_offchip
, vmem_offs_inner
.first
, oc_lds
, vmem_offs_inner
.second
, 4, (1 << inner_comps
) - 1, true, false);
10304 begin_divergent_if_else(ctx
, &ic_invocation_id_is_zero
);
10305 end_divergent_if(ctx
, &ic_invocation_id_is_zero
);
10308 static void emit_stream_output(isel_context
*ctx
,
10309 Temp
const *so_buffers
,
10310 Temp
const *so_write_offset
,
10311 const struct radv_stream_output
*output
)
10313 unsigned num_comps
= util_bitcount(output
->component_mask
);
10314 unsigned writemask
= (1 << num_comps
) - 1;
10315 unsigned loc
= output
->location
;
10316 unsigned buf
= output
->buffer
;
10318 assert(num_comps
&& num_comps
<= 4);
10319 if (!num_comps
|| num_comps
> 4)
10322 unsigned start
= ffs(output
->component_mask
) - 1;
10325 bool all_undef
= true;
10326 assert(ctx
->stage
& hw_vs
);
10327 for (unsigned i
= 0; i
< num_comps
; i
++) {
10328 out
[i
] = ctx
->outputs
.temps
[loc
* 4 + start
+ i
];
10329 all_undef
= all_undef
&& !out
[i
].id();
10334 while (writemask
) {
10336 u_bit_scan_consecutive_range(&writemask
, &start
, &count
);
10337 if (count
== 3 && ctx
->options
->chip_class
== GFX6
) {
10338 /* GFX6 doesn't support storing vec3, split it. */
10339 writemask
|= 1u << (start
+ 2);
10343 unsigned offset
= output
->offset
+ start
* 4;
10345 Temp write_data
= {ctx
->program
->allocateId(), RegClass(RegType::vgpr
, count
)};
10346 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, count
, 1)};
10347 for (int i
= 0; i
< count
; ++i
)
10348 vec
->operands
[i
] = (ctx
->outputs
.mask
[loc
] & 1 << (start
+ i
)) ? Operand(out
[start
+ i
]) : Operand(0u);
10349 vec
->definitions
[0] = Definition(write_data
);
10350 ctx
->block
->instructions
.emplace_back(std::move(vec
));
10355 opcode
= aco_opcode::buffer_store_dword
;
10358 opcode
= aco_opcode::buffer_store_dwordx2
;
10361 opcode
= aco_opcode::buffer_store_dwordx3
;
10364 opcode
= aco_opcode::buffer_store_dwordx4
;
10367 unreachable("Unsupported dword count.");
10370 aco_ptr
<MUBUF_instruction
> store
{create_instruction
<MUBUF_instruction
>(opcode
, Format::MUBUF
, 4, 0)};
10371 store
->operands
[0] = Operand(so_buffers
[buf
]);
10372 store
->operands
[1] = Operand(so_write_offset
[buf
]);
10373 store
->operands
[2] = Operand((uint32_t) 0);
10374 store
->operands
[3] = Operand(write_data
);
10375 if (offset
> 4095) {
10376 /* Don't think this can happen in RADV, but maybe GL? It's easy to do this anyway. */
10377 Builder
bld(ctx
->program
, ctx
->block
);
10378 store
->operands
[0] = bld
.vadd32(bld
.def(v1
), Operand(offset
), Operand(so_write_offset
[buf
]));
10380 store
->offset
= offset
;
10382 store
->offen
= true;
10384 store
->dlc
= false;
10386 store
->can_reorder
= true;
10387 ctx
->block
->instructions
.emplace_back(std::move(store
));
10391 static void emit_streamout(isel_context
*ctx
, unsigned stream
)
10393 Builder
bld(ctx
->program
, ctx
->block
);
10395 Temp so_buffers
[4];
10396 Temp buf_ptr
= convert_pointer_to_64_bit(ctx
, get_arg(ctx
, ctx
->args
->streamout_buffers
));
10397 for (unsigned i
= 0; i
< 4; i
++) {
10398 unsigned stride
= ctx
->program
->info
->so
.strides
[i
];
10402 Operand off
= bld
.copy(bld
.def(s1
), Operand(i
* 16u));
10403 so_buffers
[i
] = bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), buf_ptr
, off
);
10406 Temp so_vtx_count
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
),
10407 get_arg(ctx
, ctx
->args
->streamout_config
), Operand(0x70010u
));
10409 Temp tid
= emit_mbcnt(ctx
, bld
.def(v1
));
10411 Temp can_emit
= bld
.vopc(aco_opcode::v_cmp_gt_i32
, bld
.def(bld
.lm
), so_vtx_count
, tid
);
10414 begin_divergent_if_then(ctx
, &ic
, can_emit
);
10416 bld
.reset(ctx
->block
);
10418 Temp so_write_index
= bld
.vadd32(bld
.def(v1
), get_arg(ctx
, ctx
->args
->streamout_write_idx
), tid
);
10420 Temp so_write_offset
[4];
10422 for (unsigned i
= 0; i
< 4; i
++) {
10423 unsigned stride
= ctx
->program
->info
->so
.strides
[i
];
10428 Temp offset
= bld
.sop2(aco_opcode::s_add_i32
, bld
.def(s1
), bld
.def(s1
, scc
),
10429 get_arg(ctx
, ctx
->args
->streamout_write_idx
),
10430 get_arg(ctx
, ctx
->args
->streamout_offset
[i
]));
10431 Temp new_offset
= bld
.vadd32(bld
.def(v1
), offset
, tid
);
10433 so_write_offset
[i
] = bld
.vop2(aco_opcode::v_lshlrev_b32
, bld
.def(v1
), Operand(2u), new_offset
);
10435 Temp offset
= bld
.v_mul_imm(bld
.def(v1
), so_write_index
, stride
* 4u);
10436 Temp offset2
= bld
.sop2(aco_opcode::s_mul_i32
, bld
.def(s1
), Operand(4u),
10437 get_arg(ctx
, ctx
->args
->streamout_offset
[i
]));
10438 so_write_offset
[i
] = bld
.vadd32(bld
.def(v1
), offset
, offset2
);
10442 for (unsigned i
= 0; i
< ctx
->program
->info
->so
.num_outputs
; i
++) {
10443 struct radv_stream_output
*output
=
10444 &ctx
->program
->info
->so
.outputs
[i
];
10445 if (stream
!= output
->stream
)
10448 emit_stream_output(ctx
, so_buffers
, so_write_offset
, output
);
10451 begin_divergent_if_else(ctx
, &ic
);
10452 end_divergent_if(ctx
, &ic
);
10455 } /* end namespace */
10457 void fix_ls_vgpr_init_bug(isel_context
*ctx
, Pseudo_instruction
*startpgm
)
10459 assert(ctx
->shader
->info
.stage
== MESA_SHADER_VERTEX
);
10460 Builder
bld(ctx
->program
, ctx
->block
);
10461 constexpr unsigned hs_idx
= 1u;
10462 Builder::Result hs_thread_count
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
),
10463 get_arg(ctx
, ctx
->args
->merged_wave_info
),
10464 Operand((8u << 16) | (hs_idx
* 8u)));
10465 Temp ls_has_nonzero_hs_threads
= bool_to_vector_condition(ctx
, hs_thread_count
.def(1).getTemp());
10467 /* If there are no HS threads, SPI mistakenly loads the LS VGPRs starting at VGPR 0. */
10469 Temp instance_id
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
),
10470 get_arg(ctx
, ctx
->args
->rel_auto_id
),
10471 get_arg(ctx
, ctx
->args
->ac
.instance_id
),
10472 ls_has_nonzero_hs_threads
);
10473 Temp rel_auto_id
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
),
10474 get_arg(ctx
, ctx
->args
->ac
.tcs_rel_ids
),
10475 get_arg(ctx
, ctx
->args
->rel_auto_id
),
10476 ls_has_nonzero_hs_threads
);
10477 Temp vertex_id
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
),
10478 get_arg(ctx
, ctx
->args
->ac
.tcs_patch_id
),
10479 get_arg(ctx
, ctx
->args
->ac
.vertex_id
),
10480 ls_has_nonzero_hs_threads
);
10482 ctx
->arg_temps
[ctx
->args
->ac
.instance_id
.arg_index
] = instance_id
;
10483 ctx
->arg_temps
[ctx
->args
->rel_auto_id
.arg_index
] = rel_auto_id
;
10484 ctx
->arg_temps
[ctx
->args
->ac
.vertex_id
.arg_index
] = vertex_id
;
10487 void split_arguments(isel_context
*ctx
, Pseudo_instruction
*startpgm
)
10489 /* Split all arguments except for the first (ring_offsets) and the last
10490 * (exec) so that the dead channels don't stay live throughout the program.
10492 for (int i
= 1; i
< startpgm
->definitions
.size() - 1; i
++) {
10493 if (startpgm
->definitions
[i
].regClass().size() > 1) {
10494 emit_split_vector(ctx
, startpgm
->definitions
[i
].getTemp(),
10495 startpgm
->definitions
[i
].regClass().size());
10500 void handle_bc_optimize(isel_context
*ctx
)
10502 /* needed when SPI_PS_IN_CONTROL.BC_OPTIMIZE_DISABLE is set to 0 */
10503 Builder
bld(ctx
->program
, ctx
->block
);
10504 uint32_t spi_ps_input_ena
= ctx
->program
->config
->spi_ps_input_ena
;
10505 bool uses_center
= G_0286CC_PERSP_CENTER_ENA(spi_ps_input_ena
) || G_0286CC_LINEAR_CENTER_ENA(spi_ps_input_ena
);
10506 bool uses_centroid
= G_0286CC_PERSP_CENTROID_ENA(spi_ps_input_ena
) || G_0286CC_LINEAR_CENTROID_ENA(spi_ps_input_ena
);
10507 ctx
->persp_centroid
= get_arg(ctx
, ctx
->args
->ac
.persp_centroid
);
10508 ctx
->linear_centroid
= get_arg(ctx
, ctx
->args
->ac
.linear_centroid
);
10509 if (uses_center
&& uses_centroid
) {
10510 Temp sel
= bld
.vopc_e64(aco_opcode::v_cmp_lt_i32
, bld
.hint_vcc(bld
.def(bld
.lm
)),
10511 get_arg(ctx
, ctx
->args
->ac
.prim_mask
), Operand(0u));
10513 if (G_0286CC_PERSP_CENTROID_ENA(spi_ps_input_ena
)) {
10515 for (unsigned i
= 0; i
< 2; i
++) {
10516 Temp persp_centroid
= emit_extract_vector(ctx
, get_arg(ctx
, ctx
->args
->ac
.persp_centroid
), i
, v1
);
10517 Temp persp_center
= emit_extract_vector(ctx
, get_arg(ctx
, ctx
->args
->ac
.persp_center
), i
, v1
);
10518 new_coord
[i
] = bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
),
10519 persp_centroid
, persp_center
, sel
);
10521 ctx
->persp_centroid
= bld
.tmp(v2
);
10522 bld
.pseudo(aco_opcode::p_create_vector
, Definition(ctx
->persp_centroid
),
10523 Operand(new_coord
[0]), Operand(new_coord
[1]));
10524 emit_split_vector(ctx
, ctx
->persp_centroid
, 2);
10527 if (G_0286CC_LINEAR_CENTROID_ENA(spi_ps_input_ena
)) {
10529 for (unsigned i
= 0; i
< 2; i
++) {
10530 Temp linear_centroid
= emit_extract_vector(ctx
, get_arg(ctx
, ctx
->args
->ac
.linear_centroid
), i
, v1
);
10531 Temp linear_center
= emit_extract_vector(ctx
, get_arg(ctx
, ctx
->args
->ac
.linear_center
), i
, v1
);
10532 new_coord
[i
] = bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
),
10533 linear_centroid
, linear_center
, sel
);
10535 ctx
->linear_centroid
= bld
.tmp(v2
);
10536 bld
.pseudo(aco_opcode::p_create_vector
, Definition(ctx
->linear_centroid
),
10537 Operand(new_coord
[0]), Operand(new_coord
[1]));
10538 emit_split_vector(ctx
, ctx
->linear_centroid
, 2);
10543 void setup_fp_mode(isel_context
*ctx
, nir_shader
*shader
)
10545 Program
*program
= ctx
->program
;
10547 unsigned float_controls
= shader
->info
.float_controls_execution_mode
;
10549 program
->next_fp_mode
.preserve_signed_zero_inf_nan32
=
10550 float_controls
& FLOAT_CONTROLS_SIGNED_ZERO_INF_NAN_PRESERVE_FP32
;
10551 program
->next_fp_mode
.preserve_signed_zero_inf_nan16_64
=
10552 float_controls
& (FLOAT_CONTROLS_SIGNED_ZERO_INF_NAN_PRESERVE_FP16
|
10553 FLOAT_CONTROLS_SIGNED_ZERO_INF_NAN_PRESERVE_FP64
);
10555 program
->next_fp_mode
.must_flush_denorms32
=
10556 float_controls
& FLOAT_CONTROLS_DENORM_FLUSH_TO_ZERO_FP32
;
10557 program
->next_fp_mode
.must_flush_denorms16_64
=
10558 float_controls
& (FLOAT_CONTROLS_DENORM_FLUSH_TO_ZERO_FP16
|
10559 FLOAT_CONTROLS_DENORM_FLUSH_TO_ZERO_FP64
);
10561 program
->next_fp_mode
.care_about_round32
=
10562 float_controls
& (FLOAT_CONTROLS_ROUNDING_MODE_RTZ_FP32
| FLOAT_CONTROLS_ROUNDING_MODE_RTE_FP32
);
10564 program
->next_fp_mode
.care_about_round16_64
=
10565 float_controls
& (FLOAT_CONTROLS_ROUNDING_MODE_RTZ_FP16
| FLOAT_CONTROLS_ROUNDING_MODE_RTZ_FP64
|
10566 FLOAT_CONTROLS_ROUNDING_MODE_RTE_FP16
| FLOAT_CONTROLS_ROUNDING_MODE_RTE_FP64
);
10568 /* default to preserving fp16 and fp64 denorms, since it's free for fp64 and
10569 * the precision seems needed for Wolfenstein: Youngblood to render correctly */
10570 if (program
->next_fp_mode
.must_flush_denorms16_64
)
10571 program
->next_fp_mode
.denorm16_64
= 0;
10573 program
->next_fp_mode
.denorm16_64
= fp_denorm_keep
;
10575 /* preserving fp32 denorms is expensive, so only do it if asked */
10576 if (float_controls
& FLOAT_CONTROLS_DENORM_PRESERVE_FP32
)
10577 program
->next_fp_mode
.denorm32
= fp_denorm_keep
;
10579 program
->next_fp_mode
.denorm32
= 0;
10581 if (float_controls
& FLOAT_CONTROLS_ROUNDING_MODE_RTZ_FP32
)
10582 program
->next_fp_mode
.round32
= fp_round_tz
;
10584 program
->next_fp_mode
.round32
= fp_round_ne
;
10586 if (float_controls
& (FLOAT_CONTROLS_ROUNDING_MODE_RTZ_FP16
| FLOAT_CONTROLS_ROUNDING_MODE_RTZ_FP64
))
10587 program
->next_fp_mode
.round16_64
= fp_round_tz
;
10589 program
->next_fp_mode
.round16_64
= fp_round_ne
;
10591 ctx
->block
->fp_mode
= program
->next_fp_mode
;
10594 void cleanup_cfg(Program
*program
)
10596 /* create linear_succs/logical_succs */
10597 for (Block
& BB
: program
->blocks
) {
10598 for (unsigned idx
: BB
.linear_preds
)
10599 program
->blocks
[idx
].linear_succs
.emplace_back(BB
.index
);
10600 for (unsigned idx
: BB
.logical_preds
)
10601 program
->blocks
[idx
].logical_succs
.emplace_back(BB
.index
);
10605 Temp
merged_wave_info_to_mask(isel_context
*ctx
, unsigned i
)
10607 Builder
bld(ctx
->program
, ctx
->block
);
10609 /* The s_bfm only cares about s0.u[5:0] so we don't need either s_bfe nor s_and here */
10610 Temp count
= i
== 0
10611 ? get_arg(ctx
, ctx
->args
->merged_wave_info
)
10612 : bld
.sop2(aco_opcode::s_lshr_b32
, bld
.def(s1
), bld
.def(s1
, scc
),
10613 get_arg(ctx
, ctx
->args
->merged_wave_info
), Operand(i
* 8u));
10615 Temp mask
= bld
.sop2(aco_opcode::s_bfm_b64
, bld
.def(s2
), count
, Operand(0u));
10618 if (ctx
->program
->wave_size
== 64) {
10619 /* Special case for 64 active invocations, because 64 doesn't work with s_bfm */
10620 Temp active_64
= bld
.sopc(aco_opcode::s_bitcmp1_b32
, bld
.def(s1
, scc
), count
, Operand(6u /* log2(64) */));
10621 cond
= bld
.sop2(Builder::s_cselect
, bld
.def(bld
.lm
), Operand(-1u), mask
, bld
.scc(active_64
));
10623 /* We use s_bfm_b64 (not _b32) which works with 32, but we need to extract the lower half of the register */
10624 cond
= emit_extract_vector(ctx
, mask
, 0, bld
.lm
);
10630 bool ngg_early_prim_export(isel_context
*ctx
)
10632 /* TODO: Check edge flags, and if they are written, return false. (Needed for OpenGL, not for Vulkan.) */
10636 void ngg_emit_sendmsg_gs_alloc_req(isel_context
*ctx
)
10638 Builder
bld(ctx
->program
, ctx
->block
);
10640 /* It is recommended to do the GS_ALLOC_REQ as soon and as quickly as possible, so we set the maximum priority (3). */
10641 bld
.sopp(aco_opcode::s_setprio
, -1u, 0x3u
);
10643 /* Get the id of the current wave within the threadgroup (workgroup) */
10644 Builder::Result wave_id_in_tg
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
),
10645 get_arg(ctx
, ctx
->args
->merged_wave_info
), Operand(24u | (4u << 16)));
10647 /* Execute the following code only on the first wave (wave id 0),
10648 * use the SCC def to tell if the wave id is zero or not.
10650 Temp cond
= wave_id_in_tg
.def(1).getTemp();
10652 begin_uniform_if_then(ctx
, &ic
, cond
);
10653 begin_uniform_if_else(ctx
, &ic
);
10654 bld
.reset(ctx
->block
);
10656 /* Number of vertices output by VS/TES */
10657 Temp vtx_cnt
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
),
10658 get_arg(ctx
, ctx
->args
->gs_tg_info
), Operand(12u | (9u << 16u)));
10659 /* Number of primitives output by VS/TES */
10660 Temp prm_cnt
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
),
10661 get_arg(ctx
, ctx
->args
->gs_tg_info
), Operand(22u | (9u << 16u)));
10663 /* Put the number of vertices and primitives into m0 for the GS_ALLOC_REQ */
10664 Temp tmp
= bld
.sop2(aco_opcode::s_lshl_b32
, bld
.def(s1
), bld
.def(s1
, scc
), prm_cnt
, Operand(12u));
10665 tmp
= bld
.sop2(aco_opcode::s_or_b32
, bld
.m0(bld
.def(s1
)), bld
.def(s1
, scc
), tmp
, vtx_cnt
);
10667 /* Request the SPI to allocate space for the primitives and vertices that will be exported by the threadgroup. */
10668 bld
.sopp(aco_opcode::s_sendmsg
, bld
.m0(tmp
), -1, sendmsg_gs_alloc_req
);
10670 end_uniform_if(ctx
, &ic
);
10672 /* After the GS_ALLOC_REQ is done, reset priority to default (0). */
10673 bld
.reset(ctx
->block
);
10674 bld
.sopp(aco_opcode::s_setprio
, -1u, 0x0u
);
10677 Temp
ngg_get_prim_exp_arg(isel_context
*ctx
, unsigned num_vertices
, const Temp vtxindex
[])
10679 Builder
bld(ctx
->program
, ctx
->block
);
10681 if (ctx
->args
->options
->key
.vs_common_out
.as_ngg_passthrough
) {
10682 return get_arg(ctx
, ctx
->args
->gs_vtx_offset
[0]);
10685 Temp gs_invocation_id
= get_arg(ctx
, ctx
->args
->ac
.gs_invocation_id
);
10688 for (unsigned i
= 0; i
< num_vertices
; ++i
) {
10689 assert(vtxindex
[i
].id());
10692 tmp
= bld
.vop3(aco_opcode::v_lshl_add_u32
, bld
.def(v1
), vtxindex
[i
], Operand(10u * i
), tmp
);
10696 /* The initial edge flag is always false in tess eval shaders. */
10697 if (ctx
->stage
== ngg_vertex_gs
) {
10698 Temp edgeflag
= bld
.vop3(aco_opcode::v_bfe_u32
, bld
.def(v1
), gs_invocation_id
, Operand(8 + i
), Operand(1u));
10699 tmp
= bld
.vop3(aco_opcode::v_lshl_add_u32
, bld
.def(v1
), edgeflag
, Operand(10u * i
+ 9u), tmp
);
10703 /* TODO: Set isnull field in case of merged NGG VS+GS. */
10708 void ngg_emit_prim_export(isel_context
*ctx
, unsigned num_vertices_per_primitive
, const Temp vtxindex
[])
10710 Builder
bld(ctx
->program
, ctx
->block
);
10711 Temp prim_exp_arg
= ngg_get_prim_exp_arg(ctx
, num_vertices_per_primitive
, vtxindex
);
10713 bld
.exp(aco_opcode::exp
, prim_exp_arg
, Operand(v1
), Operand(v1
), Operand(v1
),
10714 1 /* enabled mask */, V_008DFC_SQ_EXP_PRIM
/* dest */,
10715 false /* compressed */, true/* done */, false /* valid mask */);
10718 void ngg_emit_nogs_gsthreads(isel_context
*ctx
)
10720 /* Emit the things that NGG GS threads need to do, for shaders that don't have SW GS.
10721 * These must always come before VS exports.
10723 * It is recommended to do these as early as possible. They can be at the beginning when
10724 * there is no SW GS and the shader doesn't write edge flags.
10728 Temp is_gs_thread
= merged_wave_info_to_mask(ctx
, 1);
10729 begin_divergent_if_then(ctx
, &ic
, is_gs_thread
);
10731 Builder
bld(ctx
->program
, ctx
->block
);
10732 constexpr unsigned max_vertices_per_primitive
= 3;
10733 unsigned num_vertices_per_primitive
= max_vertices_per_primitive
;
10735 if (ctx
->stage
== ngg_vertex_gs
) {
10736 /* TODO: optimize for points & lines */
10737 } else if (ctx
->stage
== ngg_tess_eval_gs
) {
10738 if (ctx
->shader
->info
.tess
.point_mode
)
10739 num_vertices_per_primitive
= 1;
10740 else if (ctx
->shader
->info
.tess
.primitive_mode
== GL_ISOLINES
)
10741 num_vertices_per_primitive
= 2;
10743 unreachable("Unsupported NGG shader stage");
10746 Temp vtxindex
[max_vertices_per_primitive
];
10747 vtxindex
[0] = bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(0xffffu
),
10748 get_arg(ctx
, ctx
->args
->gs_vtx_offset
[0]));
10749 vtxindex
[1] = num_vertices_per_primitive
< 2 ? Temp(0, v1
) :
10750 bld
.vop3(aco_opcode::v_bfe_u32
, bld
.def(v1
),
10751 get_arg(ctx
, ctx
->args
->gs_vtx_offset
[0]), Operand(16u), Operand(16u));
10752 vtxindex
[2] = num_vertices_per_primitive
< 3 ? Temp(0, v1
) :
10753 bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(0xffffu
),
10754 get_arg(ctx
, ctx
->args
->gs_vtx_offset
[2]));
10756 /* Export primitive data to the index buffer. */
10757 ngg_emit_prim_export(ctx
, num_vertices_per_primitive
, vtxindex
);
10759 /* Export primitive ID. */
10760 if (ctx
->stage
== ngg_vertex_gs
&& ctx
->args
->options
->key
.vs_common_out
.export_prim_id
) {
10761 /* Copy Primitive IDs from GS threads to the LDS address corresponding to the ES thread of the provoking vertex. */
10762 Temp prim_id
= get_arg(ctx
, ctx
->args
->ac
.gs_prim_id
);
10763 Temp provoking_vtx_index
= vtxindex
[0];
10764 Temp addr
= bld
.v_mul_imm(bld
.def(v1
), provoking_vtx_index
, 4u);
10766 store_lds(ctx
, 4, prim_id
, 0x1u
, addr
, 0u, 4u);
10769 begin_divergent_if_else(ctx
, &ic
);
10770 end_divergent_if(ctx
, &ic
);
10773 void ngg_emit_nogs_output(isel_context
*ctx
)
10775 /* Emits NGG GS output, for stages that don't have SW GS. */
10778 Builder
bld(ctx
->program
, ctx
->block
);
10779 bool late_prim_export
= !ngg_early_prim_export(ctx
);
10781 /* NGG streamout is currently disabled by default. */
10782 assert(!ctx
->args
->shader_info
->so
.num_outputs
);
10784 if (late_prim_export
) {
10785 /* VS exports are output to registers in a predecessor block. Emit phis to get them into this block. */
10786 create_export_phis(ctx
);
10787 /* Do what we need to do in the GS threads. */
10788 ngg_emit_nogs_gsthreads(ctx
);
10790 /* What comes next should be executed on ES threads. */
10791 Temp is_es_thread
= merged_wave_info_to_mask(ctx
, 0);
10792 begin_divergent_if_then(ctx
, &ic
, is_es_thread
);
10793 bld
.reset(ctx
->block
);
10796 /* Export VS outputs */
10797 ctx
->block
->kind
|= block_kind_export_end
;
10798 create_vs_exports(ctx
);
10800 /* Export primitive ID */
10801 if (ctx
->args
->options
->key
.vs_common_out
.export_prim_id
) {
10804 if (ctx
->stage
== ngg_vertex_gs
) {
10805 /* Wait for GS threads to store primitive ID in LDS. */
10806 bld
.barrier(aco_opcode::p_memory_barrier_shared
);
10807 bld
.sopp(aco_opcode::s_barrier
);
10809 /* Calculate LDS address where the GS threads stored the primitive ID. */
10810 Temp wave_id_in_tg
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
),
10811 get_arg(ctx
, ctx
->args
->merged_wave_info
), Operand(24u | (4u << 16)));
10812 Temp thread_id_in_wave
= emit_mbcnt(ctx
, bld
.def(v1
));
10813 Temp wave_id_mul
= bld
.v_mul24_imm(bld
.def(v1
), as_vgpr(ctx
, wave_id_in_tg
), ctx
->program
->wave_size
);
10814 Temp thread_id_in_tg
= bld
.vadd32(bld
.def(v1
), Operand(wave_id_mul
), Operand(thread_id_in_wave
));
10815 Temp addr
= bld
.v_mul24_imm(bld
.def(v1
), thread_id_in_tg
, 4u);
10817 /* Load primitive ID from LDS. */
10818 prim_id
= load_lds(ctx
, 4, bld
.tmp(v1
), addr
, 0u, 4u);
10819 } else if (ctx
->stage
== ngg_tess_eval_gs
) {
10820 /* TES: Just use the patch ID as the primitive ID. */
10821 prim_id
= get_arg(ctx
, ctx
->args
->ac
.tes_patch_id
);
10823 unreachable("unsupported NGG shader stage.");
10826 ctx
->outputs
.mask
[VARYING_SLOT_PRIMITIVE_ID
] |= 0x1;
10827 ctx
->outputs
.temps
[VARYING_SLOT_PRIMITIVE_ID
* 4u] = prim_id
;
10829 export_vs_varying(ctx
, VARYING_SLOT_PRIMITIVE_ID
, false, nullptr);
10832 if (late_prim_export
) {
10833 begin_divergent_if_else(ctx
, &ic
);
10834 end_divergent_if(ctx
, &ic
);
10835 bld
.reset(ctx
->block
);
10839 void select_program(Program
*program
,
10840 unsigned shader_count
,
10841 struct nir_shader
*const *shaders
,
10842 ac_shader_config
* config
,
10843 struct radv_shader_args
*args
)
10845 isel_context ctx
= setup_isel_context(program
, shader_count
, shaders
, config
, args
, false);
10846 if_context ic_merged_wave_info
;
10847 bool ngg_no_gs
= ctx
.stage
== ngg_vertex_gs
|| ctx
.stage
== ngg_tess_eval_gs
;
10849 for (unsigned i
= 0; i
< shader_count
; i
++) {
10850 nir_shader
*nir
= shaders
[i
];
10851 init_context(&ctx
, nir
);
10853 setup_fp_mode(&ctx
, nir
);
10856 /* needs to be after init_context() for FS */
10857 Pseudo_instruction
*startpgm
= add_startpgm(&ctx
);
10858 append_logical_start(ctx
.block
);
10860 if (unlikely(args
->options
->has_ls_vgpr_init_bug
&& ctx
.stage
== vertex_tess_control_hs
))
10861 fix_ls_vgpr_init_bug(&ctx
, startpgm
);
10863 split_arguments(&ctx
, startpgm
);
10867 ngg_emit_sendmsg_gs_alloc_req(&ctx
);
10869 if (ngg_early_prim_export(&ctx
))
10870 ngg_emit_nogs_gsthreads(&ctx
);
10873 /* In a merged VS+TCS HS, the VS implementation can be completely empty. */
10874 nir_function_impl
*func
= nir_shader_get_entrypoint(nir
);
10875 bool empty_shader
= nir_cf_list_is_empty_block(&func
->body
) &&
10876 ((nir
->info
.stage
== MESA_SHADER_VERTEX
&&
10877 (ctx
.stage
== vertex_tess_control_hs
|| ctx
.stage
== vertex_geometry_gs
)) ||
10878 (nir
->info
.stage
== MESA_SHADER_TESS_EVAL
&&
10879 ctx
.stage
== tess_eval_geometry_gs
));
10881 bool check_merged_wave_info
= ctx
.tcs_in_out_eq
? i
== 0 : ((shader_count
>= 2 && !empty_shader
) || ngg_no_gs
);
10882 bool endif_merged_wave_info
= ctx
.tcs_in_out_eq
? i
== 1 : check_merged_wave_info
;
10883 if (check_merged_wave_info
) {
10884 Temp cond
= merged_wave_info_to_mask(&ctx
, i
);
10885 begin_divergent_if_then(&ctx
, &ic_merged_wave_info
, cond
);
10889 Builder
bld(ctx
.program
, ctx
.block
);
10891 bld
.barrier(aco_opcode::p_memory_barrier_shared
);
10892 bld
.sopp(aco_opcode::s_barrier
);
10894 if (ctx
.stage
== vertex_geometry_gs
|| ctx
.stage
== tess_eval_geometry_gs
) {
10895 ctx
.gs_wave_id
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
, m0
), bld
.def(s1
, scc
), get_arg(&ctx
, args
->merged_wave_info
), Operand((8u << 16) | 16u));
10897 } else if (ctx
.stage
== geometry_gs
)
10898 ctx
.gs_wave_id
= get_arg(&ctx
, args
->gs_wave_id
);
10900 if (ctx
.stage
== fragment_fs
)
10901 handle_bc_optimize(&ctx
);
10903 visit_cf_list(&ctx
, &func
->body
);
10905 if (ctx
.program
->info
->so
.num_outputs
&& (ctx
.stage
& hw_vs
))
10906 emit_streamout(&ctx
, 0);
10908 if (ctx
.stage
& hw_vs
) {
10909 create_vs_exports(&ctx
);
10910 ctx
.block
->kind
|= block_kind_export_end
;
10911 } else if (ngg_no_gs
&& ngg_early_prim_export(&ctx
)) {
10912 ngg_emit_nogs_output(&ctx
);
10913 } else if (nir
->info
.stage
== MESA_SHADER_GEOMETRY
) {
10914 Builder
bld(ctx
.program
, ctx
.block
);
10915 bld
.barrier(aco_opcode::p_memory_barrier_gs_data
);
10916 bld
.sopp(aco_opcode::s_sendmsg
, bld
.m0(ctx
.gs_wave_id
), -1, sendmsg_gs_done(false, false, 0));
10917 } else if (nir
->info
.stage
== MESA_SHADER_TESS_CTRL
) {
10918 write_tcs_tess_factors(&ctx
);
10921 if (ctx
.stage
== fragment_fs
) {
10922 create_fs_exports(&ctx
);
10923 ctx
.block
->kind
|= block_kind_export_end
;
10926 if (endif_merged_wave_info
) {
10927 begin_divergent_if_else(&ctx
, &ic_merged_wave_info
);
10928 end_divergent_if(&ctx
, &ic_merged_wave_info
);
10931 if (ngg_no_gs
&& !ngg_early_prim_export(&ctx
))
10932 ngg_emit_nogs_output(&ctx
);
10934 if (i
== 0 && ctx
.stage
== vertex_tess_control_hs
&& ctx
.tcs_in_out_eq
) {
10935 /* Outputs of the previous stage are inputs to the next stage */
10936 ctx
.inputs
= ctx
.outputs
;
10937 ctx
.outputs
= shader_io_state();
10941 program
->config
->float_mode
= program
->blocks
[0].fp_mode
.val
;
10943 append_logical_end(ctx
.block
);
10944 ctx
.block
->kind
|= block_kind_uniform
;
10945 Builder
bld(ctx
.program
, ctx
.block
);
10946 if (ctx
.program
->wb_smem_l1_on_end
)
10947 bld
.smem(aco_opcode::s_dcache_wb
, false);
10948 bld
.sopp(aco_opcode::s_endpgm
);
10950 cleanup_cfg(program
);
10953 void select_gs_copy_shader(Program
*program
, struct nir_shader
*gs_shader
,
10954 ac_shader_config
* config
,
10955 struct radv_shader_args
*args
)
10957 isel_context ctx
= setup_isel_context(program
, 1, &gs_shader
, config
, args
, true);
10959 program
->next_fp_mode
.preserve_signed_zero_inf_nan32
= false;
10960 program
->next_fp_mode
.preserve_signed_zero_inf_nan16_64
= false;
10961 program
->next_fp_mode
.must_flush_denorms32
= false;
10962 program
->next_fp_mode
.must_flush_denorms16_64
= false;
10963 program
->next_fp_mode
.care_about_round32
= false;
10964 program
->next_fp_mode
.care_about_round16_64
= false;
10965 program
->next_fp_mode
.denorm16_64
= fp_denorm_keep
;
10966 program
->next_fp_mode
.denorm32
= 0;
10967 program
->next_fp_mode
.round32
= fp_round_ne
;
10968 program
->next_fp_mode
.round16_64
= fp_round_ne
;
10969 ctx
.block
->fp_mode
= program
->next_fp_mode
;
10971 add_startpgm(&ctx
);
10972 append_logical_start(ctx
.block
);
10974 Builder
bld(ctx
.program
, ctx
.block
);
10976 Temp gsvs_ring
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), program
->private_segment_buffer
, Operand(RING_GSVS_VS
* 16u));
10978 Operand
stream_id(0u);
10979 if (args
->shader_info
->so
.num_outputs
)
10980 stream_id
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
),
10981 get_arg(&ctx
, ctx
.args
->streamout_config
), Operand(0x20018u
));
10983 Temp vtx_offset
= bld
.vop2(aco_opcode::v_lshlrev_b32
, bld
.def(v1
), Operand(2u), get_arg(&ctx
, ctx
.args
->ac
.vertex_id
));
10985 std::stack
<Block
> endif_blocks
;
10987 for (unsigned stream
= 0; stream
< 4; stream
++) {
10988 if (stream_id
.isConstant() && stream
!= stream_id
.constantValue())
10991 unsigned num_components
= args
->shader_info
->gs
.num_stream_output_components
[stream
];
10992 if (stream
> 0 && (!num_components
|| !args
->shader_info
->so
.num_outputs
))
10995 memset(ctx
.outputs
.mask
, 0, sizeof(ctx
.outputs
.mask
));
10997 unsigned BB_if_idx
= ctx
.block
->index
;
10998 Block BB_endif
= Block();
10999 if (!stream_id
.isConstant()) {
11001 Temp cond
= bld
.sopc(aco_opcode::s_cmp_eq_u32
, bld
.def(s1
, scc
), stream_id
, Operand(stream
));
11002 append_logical_end(ctx
.block
);
11003 ctx
.block
->kind
|= block_kind_uniform
;
11004 bld
.branch(aco_opcode::p_cbranch_z
, cond
);
11006 BB_endif
.kind
|= ctx
.block
->kind
& block_kind_top_level
;
11008 ctx
.block
= ctx
.program
->create_and_insert_block();
11009 add_edge(BB_if_idx
, ctx
.block
);
11010 bld
.reset(ctx
.block
);
11011 append_logical_start(ctx
.block
);
11014 unsigned offset
= 0;
11015 for (unsigned i
= 0; i
<= VARYING_SLOT_VAR31
; ++i
) {
11016 if (args
->shader_info
->gs
.output_streams
[i
] != stream
)
11019 unsigned output_usage_mask
= args
->shader_info
->gs
.output_usage_mask
[i
];
11020 unsigned length
= util_last_bit(output_usage_mask
);
11021 for (unsigned j
= 0; j
< length
; ++j
) {
11022 if (!(output_usage_mask
& (1 << j
)))
11025 unsigned const_offset
= offset
* args
->shader_info
->gs
.vertices_out
* 16 * 4;
11026 Temp voffset
= vtx_offset
;
11027 if (const_offset
>= 4096u) {
11028 voffset
= bld
.vadd32(bld
.def(v1
), Operand(const_offset
/ 4096u * 4096u), voffset
);
11029 const_offset
%= 4096u;
11032 aco_ptr
<MUBUF_instruction
> mubuf
{create_instruction
<MUBUF_instruction
>(aco_opcode::buffer_load_dword
, Format::MUBUF
, 3, 1)};
11033 mubuf
->definitions
[0] = bld
.def(v1
);
11034 mubuf
->operands
[0] = Operand(gsvs_ring
);
11035 mubuf
->operands
[1] = Operand(voffset
);
11036 mubuf
->operands
[2] = Operand(0u);
11037 mubuf
->offen
= true;
11038 mubuf
->offset
= const_offset
;
11041 mubuf
->dlc
= args
->options
->chip_class
>= GFX10
;
11042 mubuf
->barrier
= barrier_none
;
11043 mubuf
->can_reorder
= true;
11045 ctx
.outputs
.mask
[i
] |= 1 << j
;
11046 ctx
.outputs
.temps
[i
* 4u + j
] = mubuf
->definitions
[0].getTemp();
11048 bld
.insert(std::move(mubuf
));
11054 if (args
->shader_info
->so
.num_outputs
) {
11055 emit_streamout(&ctx
, stream
);
11056 bld
.reset(ctx
.block
);
11060 create_vs_exports(&ctx
);
11061 ctx
.block
->kind
|= block_kind_export_end
;
11064 if (!stream_id
.isConstant()) {
11065 append_logical_end(ctx
.block
);
11067 /* branch from then block to endif block */
11068 bld
.branch(aco_opcode::p_branch
);
11069 add_edge(ctx
.block
->index
, &BB_endif
);
11070 ctx
.block
->kind
|= block_kind_uniform
;
11072 /* emit else block */
11073 ctx
.block
= ctx
.program
->create_and_insert_block();
11074 add_edge(BB_if_idx
, ctx
.block
);
11075 bld
.reset(ctx
.block
);
11076 append_logical_start(ctx
.block
);
11078 endif_blocks
.push(std::move(BB_endif
));
11082 while (!endif_blocks
.empty()) {
11083 Block BB_endif
= std::move(endif_blocks
.top());
11084 endif_blocks
.pop();
11086 Block
*BB_else
= ctx
.block
;
11088 append_logical_end(BB_else
);
11089 /* branch from else block to endif block */
11090 bld
.branch(aco_opcode::p_branch
);
11091 add_edge(BB_else
->index
, &BB_endif
);
11092 BB_else
->kind
|= block_kind_uniform
;
11094 /** emit endif merge block */
11095 ctx
.block
= program
->insert_block(std::move(BB_endif
));
11096 bld
.reset(ctx
.block
);
11097 append_logical_start(ctx
.block
);
11100 program
->config
->float_mode
= program
->blocks
[0].fp_mode
.val
;
11102 append_logical_end(ctx
.block
);
11103 ctx
.block
->kind
|= block_kind_uniform
;
11104 bld
.sopp(aco_opcode::s_endpgm
);
11106 cleanup_cfg(program
);