src/amd/compiler/aco_instruction_selection.cpp

   1 /*
   2  * Copyright © 2018 Valve Corporation
   3  * Copyright © 2018 Google
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the "Software"),
   7  * to deal in the Software without restriction, including without limitation
   8  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   9  * and/or sell copies of the Software, and to permit persons to whom the
  10  * Software is furnished to do so, subject to the following conditions:
  11  *
  12  * The above copyright notice and this permission notice (including the next
  13  * paragraph) shall be included in all copies or substantial portions of the
  14  * Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  21  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  22  * IN THE SOFTWARE.
  23  *
  24  */
  25
  26 #include <algorithm>
  27 #include <array>
  28 #include <stack>
  29 #include <map>
  30
  31 #include "ac_shader_util.h"
  32 #include "aco_ir.h"
  33 #include "aco_builder.h"
  34 #include "aco_interface.h"
  35 #include "aco_instruction_selection_setup.cpp"
  36 #include "util/fast_idiv_by_const.h"
  37
  38 namespace aco {
  39 namespace {
  40
  41 class loop_info_RAII {
  42    isel_context* ctx;
  43    unsigned header_idx_old;
  44    Block* exit_old;
  45    bool divergent_cont_old;
  46    bool divergent_branch_old;
  47    bool divergent_if_old;
  48
  49 public:
  50    loop_info_RAII(isel_context* ctx, unsigned loop_header_idx, Block* loop_exit)
  51       : ctx(ctx),
  52         header_idx_old(ctx->cf_info.parent_loop.header_idx), exit_old(ctx->cf_info.parent_loop.exit),
  53         divergent_cont_old(ctx->cf_info.parent_loop.has_divergent_continue),
  54         divergent_branch_old(ctx->cf_info.parent_loop.has_divergent_branch),
  55         divergent_if_old(ctx->cf_info.parent_if.is_divergent)
  56    {
  57       ctx->cf_info.parent_loop.header_idx = loop_header_idx;
  58       ctx->cf_info.parent_loop.exit = loop_exit;
  59       ctx->cf_info.parent_loop.has_divergent_continue = false;
  60       ctx->cf_info.parent_loop.has_divergent_branch = false;
  61       ctx->cf_info.parent_if.is_divergent = false;
  62       ctx->cf_info.loop_nest_depth = ctx->cf_info.loop_nest_depth + 1;
  63    }
  64
  65    ~loop_info_RAII()
  66    {
  67       ctx->cf_info.parent_loop.header_idx = header_idx_old;
  68       ctx->cf_info.parent_loop.exit = exit_old;
  69       ctx->cf_info.parent_loop.has_divergent_continue = divergent_cont_old;
  70       ctx->cf_info.parent_loop.has_divergent_branch = divergent_branch_old;
  71       ctx->cf_info.parent_if.is_divergent = divergent_if_old;
  72       ctx->cf_info.loop_nest_depth = ctx->cf_info.loop_nest_depth - 1;
  73       if (!ctx->cf_info.loop_nest_depth && !ctx->cf_info.parent_if.is_divergent)
  74          ctx->cf_info.exec_potentially_empty_discard = false;
  75    }
  76 };
  77
  78 struct if_context {
  79    Temp cond;
  80
  81    bool divergent_old;
  82    bool exec_potentially_empty_discard_old;
  83    bool exec_potentially_empty_break_old;
  84    uint16_t exec_potentially_empty_break_depth_old;
  85
  86    unsigned BB_if_idx;
  87    unsigned invert_idx;
  88    bool then_branch_divergent;
  89    Block BB_invert;
  90    Block BB_endif;
  91 };
  92
  93 static void visit_cf_list(struct isel_context *ctx,
  94                           struct exec_list *list);
  95
  96 static void add_logical_edge(unsigned pred_idx, Block *succ)
  97 {
  98    succ->logical_preds.emplace_back(pred_idx);
  99 }
 100
 101
 102 static void add_linear_edge(unsigned pred_idx, Block *succ)
 103 {
 104    succ->linear_preds.emplace_back(pred_idx);
 105 }
 106
 107 static void add_edge(unsigned pred_idx, Block *succ)
 108 {
 109    add_logical_edge(pred_idx, succ);
 110    add_linear_edge(pred_idx, succ);
 111 }
 112
 113 static void append_logical_start(Block *b)
 114 {
 115    Builder(NULL, b).pseudo(aco_opcode::p_logical_start);
 116 }
 117
 118 static void append_logical_end(Block *b)
 119 {
 120    Builder(NULL, b).pseudo(aco_opcode::p_logical_end);
 121 }
 122
 123 Temp get_ssa_temp(struct isel_context *ctx, nir_ssa_def *def)
 124 {
 125    assert(ctx->allocated[def->index].id());
 126    return ctx->allocated[def->index];
 127 }
 128
 129 Temp emit_mbcnt(isel_context *ctx, Definition dst,
 130                 Operand mask_lo = Operand((uint32_t) -1), Operand mask_hi = Operand((uint32_t) -1))
 131 {
 132    Builder bld(ctx->program, ctx->block);
 133    Definition lo_def = ctx->program->wave_size == 32 ? dst : bld.def(v1);
 134    Temp thread_id_lo = bld.vop3(aco_opcode::v_mbcnt_lo_u32_b32, lo_def, mask_lo, Operand(0u));
 135
 136    if (ctx->program->wave_size == 32) {
 137       return thread_id_lo;
 138    } else {
 139       Temp thread_id_hi = bld.vop3(aco_opcode::v_mbcnt_hi_u32_b32, dst, mask_hi, thread_id_lo);
 140       return thread_id_hi;
 141    }
 142 }
 143
 144 Temp emit_wqm(isel_context *ctx, Temp src, Temp dst=Temp(0, s1), bool program_needs_wqm = false)
 145 {
 146    Builder bld(ctx->program, ctx->block);
 147
 148    if (!dst.id())
 149       dst = bld.tmp(src.regClass());
 150
 151    assert(src.size() == dst.size());
 152
 153    if (ctx->stage != fragment_fs) {
 154       if (!dst.id())
 155          return src;
 156
 157       bld.copy(Definition(dst), src);
 158       return dst;
 159    }
 160
 161    bld.pseudo(aco_opcode::p_wqm, Definition(dst), src);
 162    ctx->program->needs_wqm |= program_needs_wqm;
 163    return dst;
 164 }
 165
 166 static Temp emit_bpermute(isel_context *ctx, Builder &bld, Temp index, Temp data)
 167 {
 168    if (index.regClass() == s1)
 169       return bld.readlane(bld.def(s1), data, index);
 170
 171    Temp index_x4 = bld.vop2(aco_opcode::v_lshlrev_b32, bld.def(v1), Operand(2u), index);
 172
 173    /* Currently not implemented on GFX6-7 */
 174    assert(ctx->options->chip_class >= GFX8);
 175
 176    if (ctx->options->chip_class <= GFX9 || ctx->program->wave_size == 32) {
 177       return bld.ds(aco_opcode::ds_bpermute_b32, bld.def(v1), index_x4, data);
 178    }
 179
 180    /* GFX10, wave64 mode:
 181     * The bpermute instruction is limited to half-wave operation, which means that it can't
 182     * properly support subgroup shuffle like older generations (or wave32 mode), so we
 183     * emulate it here.
 184     */
 185    if (!ctx->has_gfx10_wave64_bpermute) {
 186       ctx->has_gfx10_wave64_bpermute = true;
 187       ctx->program->config->num_shared_vgprs = 8; /* Shared VGPRs are allocated in groups of 8 */
 188       ctx->program->vgpr_limit -= 4; /* We allocate 8 shared VGPRs, so we'll have 4 fewer normal VGPRs */
 189    }
 190
 191    Temp lane_id = emit_mbcnt(ctx, bld.def(v1));
 192    Temp lane_is_hi = bld.vop2(aco_opcode::v_and_b32, bld.def(v1), Operand(0x20u), lane_id);
 193    Temp index_is_hi = bld.vop2(aco_opcode::v_and_b32, bld.def(v1), Operand(0x20u), index);
 194    Temp cmp = bld.vopc(aco_opcode::v_cmp_eq_u32, bld.def(bld.lm, vcc), lane_is_hi, index_is_hi);
 195
 196    return bld.reduction(aco_opcode::p_wave64_bpermute, bld.def(v1), bld.def(s2), bld.def(s1, scc),
 197                         bld.vcc(cmp), Operand(v2.as_linear()), index_x4, data, gfx10_wave64_bpermute);
 198 }
 199
 200 Temp as_vgpr(isel_context *ctx, Temp val)
 201 {
 202    if (val.type() == RegType::sgpr) {
 203       Builder bld(ctx->program, ctx->block);
 204       return bld.copy(bld.def(RegType::vgpr, val.size()), val);
 205    }
 206    assert(val.type() == RegType::vgpr);
 207    return val;
 208 }
 209
 210 //assumes a != 0xffffffff
 211 void emit_v_div_u32(isel_context *ctx, Temp dst, Temp a, uint32_t b)
 212 {
 213    assert(b != 0);
 214    Builder bld(ctx->program, ctx->block);
 215
 216    if (util_is_power_of_two_or_zero(b)) {
 217       bld.vop2(aco_opcode::v_lshrrev_b32, Definition(dst), Operand((uint32_t)util_logbase2(b)), a);
 218       return;
 219    }
 220
 221    util_fast_udiv_info info = util_compute_fast_udiv_info(b, 32, 32);
 222
 223    assert(info.multiplier <= 0xffffffff);
 224
 225    bool pre_shift = info.pre_shift != 0;
 226    bool increment = info.increment != 0;
 227    bool multiply = true;
 228    bool post_shift = info.post_shift != 0;
 229
 230    if (!pre_shift && !increment && !multiply && !post_shift) {
 231       bld.vop1(aco_opcode::v_mov_b32, Definition(dst), a);
 232       return;
 233    }
 234
 235    Temp pre_shift_dst = a;
 236    if (pre_shift) {
 237       pre_shift_dst = (increment || multiply || post_shift) ? bld.tmp(v1) : dst;
 238       bld.vop2(aco_opcode::v_lshrrev_b32, Definition(pre_shift_dst), Operand((uint32_t)info.pre_shift), a);
 239    }
 240
 241    Temp increment_dst = pre_shift_dst;
 242    if (increment) {
 243       increment_dst = (post_shift || multiply) ? bld.tmp(v1) : dst;
 244       bld.vadd32(Definition(increment_dst), Operand((uint32_t) info.increment), pre_shift_dst);
 245    }
 246
 247    Temp multiply_dst = increment_dst;
 248    if (multiply) {
 249       multiply_dst = post_shift ? bld.tmp(v1) : dst;
 250       bld.vop3(aco_opcode::v_mul_hi_u32, Definition(multiply_dst), increment_dst,
 251                bld.vop1(aco_opcode::v_mov_b32, bld.def(v1), Operand((uint32_t)info.multiplier)));
 252    }
 253
 254    if (post_shift) {
 255       bld.vop2(aco_opcode::v_lshrrev_b32, Definition(dst), Operand((uint32_t)info.post_shift), multiply_dst);
 256    }
 257 }
 258
 259 void emit_extract_vector(isel_context* ctx, Temp src, uint32_t idx, Temp dst)
 260 {
 261    Builder bld(ctx->program, ctx->block);
 262    bld.pseudo(aco_opcode::p_extract_vector, Definition(dst), src, Operand(idx));
 263 }
 264
 265
 266 Temp emit_extract_vector(isel_context* ctx, Temp src, uint32_t idx, RegClass dst_rc)
 267 {
 268    /* no need to extract the whole vector */
 269    if (src.regClass() == dst_rc) {
 270       assert(idx == 0);
 271       return src;
 272    }
 273    assert(src.size() > idx);
 274    Builder bld(ctx->program, ctx->block);
 275    auto it = ctx->allocated_vec.find(src.id());
 276    /* the size check needs to be early because elements other than 0 may be garbage */
 277    if (it != ctx->allocated_vec.end() && it->second[0].size() == dst_rc.size()) {
 278       if (it->second[idx].regClass() == dst_rc) {
 279          return it->second[idx];
 280       } else {
 281          assert(dst_rc.size() == it->second[idx].regClass().size());
 282          assert(dst_rc.type() == RegType::vgpr && it->second[idx].type() == RegType::sgpr);
 283          return bld.copy(bld.def(dst_rc), it->second[idx]);
 284       }
 285    }
 286
 287    if (src.size() == dst_rc.size()) {
 288       assert(idx == 0);
 289       return bld.copy(bld.def(dst_rc), src);
 290    } else {
 291       Temp dst = bld.tmp(dst_rc);
 292       emit_extract_vector(ctx, src, idx, dst);
 293       return dst;
 294    }
 295 }
 296
 297 void emit_split_vector(isel_context* ctx, Temp vec_src, unsigned num_components)
 298 {
 299    if (num_components == 1)
 300       return;
 301    if (ctx->allocated_vec.find(vec_src.id()) != ctx->allocated_vec.end())
 302       return;
 303    aco_ptr<Pseudo_instruction> split{create_instruction<Pseudo_instruction>(aco_opcode::p_split_vector, Format::PSEUDO, 1, num_components)};
 304    split->operands[0] = Operand(vec_src);
 305    std::array<Temp,NIR_MAX_VEC_COMPONENTS> elems;
 306    for (unsigned i = 0; i < num_components; i++) {
 307       elems[i] = {ctx->program->allocateId(), RegClass(vec_src.type(), vec_src.size() / num_components)};
 308       split->definitions[i] = Definition(elems[i]);
 309    }
 310    ctx->block->instructions.emplace_back(std::move(split));
 311    ctx->allocated_vec.emplace(vec_src.id(), elems);
 312 }
 313
 314 /* This vector expansion uses a mask to determine which elements in the new vector
 315  * come from the original vector. The other elements are undefined. */
 316 void expand_vector(isel_context* ctx, Temp vec_src, Temp dst, unsigned num_components, unsigned mask)
 317 {
 318    emit_split_vector(ctx, vec_src, util_bitcount(mask));
 319
 320    if (vec_src == dst)
 321       return;
 322
 323    Builder bld(ctx->program, ctx->block);
 324    if (num_components == 1) {
 325       if (dst.type() == RegType::sgpr)
 326          bld.pseudo(aco_opcode::p_as_uniform, Definition(dst), vec_src);
 327       else
 328          bld.copy(Definition(dst), vec_src);
 329       return;
 330    }
 331
 332    unsigned component_size = dst.size() / num_components;
 333    std::array<Temp,NIR_MAX_VEC_COMPONENTS> elems;
 334
 335    aco_ptr<Pseudo_instruction> vec{create_instruction<Pseudo_instruction>(aco_opcode::p_create_vector, Format::PSEUDO, num_components, 1)};
 336    vec->definitions[0] = Definition(dst);
 337    unsigned k = 0;
 338    for (unsigned i = 0; i < num_components; i++) {
 339       if (mask & (1 << i)) {
 340          Temp src = emit_extract_vector(ctx, vec_src, k++, RegClass(vec_src.type(), component_size));
 341          if (dst.type() == RegType::sgpr)
 342             src = bld.as_uniform(src);
 343          vec->operands[i] = Operand(src);
 344       } else {
 345          vec->operands[i] = Operand(0u);
 346       }
 347       elems[i] = vec->operands[i].getTemp();
 348    }
 349    ctx->block->instructions.emplace_back(std::move(vec));
 350    ctx->allocated_vec.emplace(dst.id(), elems);
 351 }
 352
 353 Temp bool_to_vector_condition(isel_context *ctx, Temp val, Temp dst = Temp(0, s2))
 354 {
 355    Builder bld(ctx->program, ctx->block);
 356    if (!dst.id())
 357       dst = bld.tmp(bld.lm);
 358
 359    assert(val.regClass() == s1);
 360    assert(dst.regClass() == bld.lm);
 361
 362    return bld.sop2(Builder::s_cselect, Definition(dst), Operand((uint32_t) -1), Operand(0u), bld.scc(val));
 363 }
 364
 365 Temp bool_to_scalar_condition(isel_context *ctx, Temp val, Temp dst = Temp(0, s1))
 366 {
 367    Builder bld(ctx->program, ctx->block);
 368    if (!dst.id())
 369       dst = bld.tmp(s1);
 370
 371    assert(val.regClass() == bld.lm);
 372    assert(dst.regClass() == s1);
 373
 374    /* if we're currently in WQM mode, ensure that the source is also computed in WQM */
 375    Temp tmp = bld.tmp(s1);
 376    bld.sop2(Builder::s_and, bld.def(bld.lm), bld.scc(Definition(tmp)), val, Operand(exec, bld.lm));
 377    return emit_wqm(ctx, tmp, dst);
 378 }
 379
 380 Temp get_alu_src(struct isel_context *ctx, nir_alu_src src, unsigned size=1)
 381 {
 382    if (src.src.ssa->num_components == 1 && src.swizzle[0] == 0 && size == 1)
 383       return get_ssa_temp(ctx, src.src.ssa);
 384
 385    if (src.src.ssa->num_components == size) {
 386       bool identity_swizzle = true;
 387       for (unsigned i = 0; identity_swizzle && i < size; i++) {
 388          if (src.swizzle[i] != i)
 389             identity_swizzle = false;
 390       }
 391       if (identity_swizzle)
 392          return get_ssa_temp(ctx, src.src.ssa);
 393    }
 394
 395    Temp vec = get_ssa_temp(ctx, src.src.ssa);
 396    unsigned elem_size = vec.size() / src.src.ssa->num_components;
 397    assert(elem_size > 0); /* TODO: 8 and 16-bit vectors not supported */
 398    assert(vec.size() % elem_size == 0);
 399
 400    RegClass elem_rc = RegClass(vec.type(), elem_size);
 401    if (size == 1) {
 402       return emit_extract_vector(ctx, vec, src.swizzle[0], elem_rc);
 403    } else {
 404       assert(size <= 4);
 405       std::array<Temp,NIR_MAX_VEC_COMPONENTS> elems;
 406       aco_ptr<Pseudo_instruction> vec_instr{create_instruction<Pseudo_instruction>(aco_opcode::p_create_vector, Format::PSEUDO, size, 1)};
 407       for (unsigned i = 0; i < size; ++i) {
 408          elems[i] = emit_extract_vector(ctx, vec, src.swizzle[i], elem_rc);
 409          vec_instr->operands[i] = Operand{elems[i]};
 410       }
 411       Temp dst{ctx->program->allocateId(), RegClass(vec.type(), elem_size * size)};
 412       vec_instr->definitions[0] = Definition(dst);
 413       ctx->block->instructions.emplace_back(std::move(vec_instr));
 414       ctx->allocated_vec.emplace(dst.id(), elems);
 415       return dst;
 416    }
 417 }
 418
 419 Temp convert_pointer_to_64_bit(isel_context *ctx, Temp ptr)
 420 {
 421    if (ptr.size() == 2)
 422       return ptr;
 423    Builder bld(ctx->program, ctx->block);
 424    if (ptr.type() == RegType::vgpr)
 425       ptr = bld.vop1(aco_opcode::v_readfirstlane_b32, bld.def(s1), ptr);
 426    return bld.pseudo(aco_opcode::p_create_vector, bld.def(s2),
 427                      ptr, Operand((unsigned)ctx->options->address32_hi));
 428 }
 429
 430 void emit_sop2_instruction(isel_context *ctx, nir_alu_instr *instr, aco_opcode op, Temp dst, bool writes_scc)
 431 {
 432    aco_ptr<SOP2_instruction> sop2{create_instruction<SOP2_instruction>(op, Format::SOP2, 2, writes_scc ? 2 : 1)};
 433    sop2->operands[0] = Operand(get_alu_src(ctx, instr->src[0]));
 434    sop2->operands[1] = Operand(get_alu_src(ctx, instr->src[1]));
 435    sop2->definitions[0] = Definition(dst);
 436    if (writes_scc)
 437       sop2->definitions[1] = Definition(ctx->program->allocateId(), scc, s1);
 438    ctx->block->instructions.emplace_back(std::move(sop2));
 439 }
 440
 441 void emit_vop2_instruction(isel_context *ctx, nir_alu_instr *instr, aco_opcode op, Temp dst,
 442                            bool commutative, bool swap_srcs=false, bool flush_denorms = false)
 443 {
 444    Builder bld(ctx->program, ctx->block);
 445    Temp src0 = get_alu_src(ctx, instr->src[swap_srcs ? 1 : 0]);
 446    Temp src1 = get_alu_src(ctx, instr->src[swap_srcs ? 0 : 1]);
 447    if (src1.type() == RegType::sgpr) {
 448       if (commutative && src0.type() == RegType::vgpr) {
 449          Temp t = src0;
 450          src0 = src1;
 451          src1 = t;
 452       } else if (src0.type() == RegType::vgpr &&
 453                  op != aco_opcode::v_madmk_f32 &&
 454                  op != aco_opcode::v_madak_f32 &&
 455                  op != aco_opcode::v_madmk_f16 &&
 456                  op != aco_opcode::v_madak_f16) {
 457          /* If the instruction is not commutative, we emit a VOP3A instruction */
 458          bld.vop2_e64(op, Definition(dst), src0, src1);
 459          return;
 460       } else {
 461          src1 = bld.copy(bld.def(RegType::vgpr, src1.size()), src1); //TODO: as_vgpr
 462       }
 463    }
 464
 465    if (flush_denorms && ctx->program->chip_class < GFX9) {
 466       assert(dst.size() == 1);
 467       Temp tmp = bld.vop2(op, bld.def(v1), src0, src1);
 468       bld.vop2(aco_opcode::v_mul_f32, Definition(dst), Operand(0x3f800000u), tmp);
 469    } else {
 470       bld.vop2(op, Definition(dst), src0, src1);
 471    }
 472 }
 473
 474 void emit_vop3a_instruction(isel_context *ctx, nir_alu_instr *instr, aco_opcode op, Temp dst,
 475                             bool flush_denorms = false)
 476 {
 477    Temp src0 = get_alu_src(ctx, instr->src[0]);
 478    Temp src1 = get_alu_src(ctx, instr->src[1]);
 479    Temp src2 = get_alu_src(ctx, instr->src[2]);
 480
 481    /* ensure that the instruction has at most 1 sgpr operand
 482     * The optimizer will inline constants for us */
 483    if (src0.type() == RegType::sgpr && src1.type() == RegType::sgpr)
 484       src0 = as_vgpr(ctx, src0);
 485    if (src1.type() == RegType::sgpr && src2.type() == RegType::sgpr)
 486       src1 = as_vgpr(ctx, src1);
 487    if (src2.type() == RegType::sgpr && src0.type() == RegType::sgpr)
 488       src2 = as_vgpr(ctx, src2);
 489
 490    Builder bld(ctx->program, ctx->block);
 491    if (flush_denorms && ctx->program->chip_class < GFX9) {
 492       assert(dst.size() == 1);
 493       Temp tmp = bld.vop3(op, Definition(dst), src0, src1, src2);
 494       bld.vop2(aco_opcode::v_mul_f32, Definition(dst), Operand(0x3f800000u), tmp);
 495    } else {
 496       bld.vop3(op, Definition(dst), src0, src1, src2);
 497    }
 498 }
 499
 500 void emit_vop1_instruction(isel_context *ctx, nir_alu_instr *instr, aco_opcode op, Temp dst)
 501 {
 502    Builder bld(ctx->program, ctx->block);
 503    bld.vop1(op, Definition(dst), get_alu_src(ctx, instr->src[0]));
 504 }
 505
 506 void emit_vopc_instruction(isel_context *ctx, nir_alu_instr *instr, aco_opcode op, Temp dst)
 507 {
 508    Temp src0 = get_alu_src(ctx, instr->src[0]);
 509    Temp src1 = get_alu_src(ctx, instr->src[1]);
 510    assert(src0.size() == src1.size());
 511
 512    aco_ptr<Instruction> vopc;
 513    if (src1.type() == RegType::sgpr) {
 514       if (src0.type() == RegType::vgpr) {
 515          /* to swap the operands, we might also have to change the opcode */
 516          switch (op) {
 517             case aco_opcode::v_cmp_lt_f32:
 518                op = aco_opcode::v_cmp_gt_f32;
 519                break;
 520             case aco_opcode::v_cmp_ge_f32:
 521                op = aco_opcode::v_cmp_le_f32;
 522                break;
 523             case aco_opcode::v_cmp_lt_i32:
 524                op = aco_opcode::v_cmp_gt_i32;
 525                break;
 526             case aco_opcode::v_cmp_ge_i32:
 527                op = aco_opcode::v_cmp_le_i32;
 528                break;
 529             case aco_opcode::v_cmp_lt_u32:
 530                op = aco_opcode::v_cmp_gt_u32;
 531                break;
 532             case aco_opcode::v_cmp_ge_u32:
 533                op = aco_opcode::v_cmp_le_u32;
 534                break;
 535             case aco_opcode::v_cmp_lt_f64:
 536                op = aco_opcode::v_cmp_gt_f64;
 537                break;
 538             case aco_opcode::v_cmp_ge_f64:
 539                op = aco_opcode::v_cmp_le_f64;
 540                break;
 541             case aco_opcode::v_cmp_lt_i64:
 542                op = aco_opcode::v_cmp_gt_i64;
 543                break;
 544             case aco_opcode::v_cmp_ge_i64:
 545                op = aco_opcode::v_cmp_le_i64;
 546                break;
 547             case aco_opcode::v_cmp_lt_u64:
 548                op = aco_opcode::v_cmp_gt_u64;
 549                break;
 550             case aco_opcode::v_cmp_ge_u64:
 551                op = aco_opcode::v_cmp_le_u64;
 552                break;
 553             default: /* eq and ne are commutative */
 554                break;
 555          }
 556          Temp t = src0;
 557          src0 = src1;
 558          src1 = t;
 559       } else {
 560          src1 = as_vgpr(ctx, src1);
 561       }
 562    }
 563
 564    Builder bld(ctx->program, ctx->block);
 565    bld.vopc(op, bld.hint_vcc(Definition(dst)), src0, src1);
 566 }
 567
 568 void emit_sopc_instruction(isel_context *ctx, nir_alu_instr *instr, aco_opcode op, Temp dst)
 569 {
 570    Temp src0 = get_alu_src(ctx, instr->src[0]);
 571    Temp src1 = get_alu_src(ctx, instr->src[1]);
 572    Builder bld(ctx->program, ctx->block);
 573
 574    assert(dst.regClass() == bld.lm);
 575    assert(src0.type() == RegType::sgpr);
 576    assert(src1.type() == RegType::sgpr);
 577    assert(src0.regClass() == src1.regClass());
 578
 579    /* Emit the SALU comparison instruction */
 580    Temp cmp = bld.sopc(op, bld.scc(bld.def(s1)), src0, src1);
 581    /* Turn the result into a per-lane bool */
 582    bool_to_vector_condition(ctx, cmp, dst);
 583 }
 584
 585 void emit_comparison(isel_context *ctx, nir_alu_instr *instr, Temp dst,
 586                      aco_opcode v32_op, aco_opcode v64_op, aco_opcode s32_op = aco_opcode::num_opcodes, aco_opcode s64_op = aco_opcode::num_opcodes)
 587 {
 588    aco_opcode s_op = instr->src[0].src.ssa->bit_size == 64 ? s64_op : s32_op;
 589    aco_opcode v_op = instr->src[0].src.ssa->bit_size == 64 ? v64_op : v32_op;
 590    bool divergent_vals = ctx->divergent_vals[instr->dest.dest.ssa.index];
 591    bool use_valu = s_op == aco_opcode::num_opcodes ||
 592                    divergent_vals ||
 593                    ctx->allocated[instr->src[0].src.ssa->index].type() == RegType::vgpr ||
 594                    ctx->allocated[instr->src[1].src.ssa->index].type() == RegType::vgpr;
 595    aco_opcode op = use_valu ? v_op : s_op;
 596    assert(op != aco_opcode::num_opcodes);
 597    assert(dst.regClass() == ctx->program->lane_mask);
 598
 599    if (use_valu)
 600       emit_vopc_instruction(ctx, instr, op, dst);
 601    else
 602       emit_sopc_instruction(ctx, instr, op, dst);
 603 }
 604
 605 void emit_boolean_logic(isel_context *ctx, nir_alu_instr *instr, Builder::WaveSpecificOpcode op, Temp dst)
 606 {
 607    Builder bld(ctx->program, ctx->block);
 608    Temp src0 = get_alu_src(ctx, instr->src[0]);
 609    Temp src1 = get_alu_src(ctx, instr->src[1]);
 610
 611    assert(dst.regClass() == bld.lm);
 612    assert(src0.regClass() == bld.lm);
 613    assert(src1.regClass() == bld.lm);
 614
 615    bld.sop2(op, Definition(dst), bld.def(s1, scc), src0, src1);
 616 }
 617
 618 void emit_bcsel(isel_context *ctx, nir_alu_instr *instr, Temp dst)
 619 {
 620    Builder bld(ctx->program, ctx->block);
 621    Temp cond = get_alu_src(ctx, instr->src[0]);
 622    Temp then = get_alu_src(ctx, instr->src[1]);
 623    Temp els = get_alu_src(ctx, instr->src[2]);
 624
 625    assert(cond.regClass() == bld.lm);
 626
 627    if (dst.type() == RegType::vgpr) {
 628       aco_ptr<Instruction> bcsel;
 629       if (dst.size() == 1) {
 630          then = as_vgpr(ctx, then);
 631          els = as_vgpr(ctx, els);
 632
 633          bld.vop2(aco_opcode::v_cndmask_b32, Definition(dst), els, then, cond);
 634       } else if (dst.size() == 2) {
 635          Temp then_lo = bld.tmp(v1), then_hi = bld.tmp(v1);
 636          bld.pseudo(aco_opcode::p_split_vector, Definition(then_lo), Definition(then_hi), then);
 637          Temp else_lo = bld.tmp(v1), else_hi = bld.tmp(v1);
 638          bld.pseudo(aco_opcode::p_split_vector, Definition(else_lo), Definition(else_hi), els);
 639
 640          Temp dst0 = bld.vop2(aco_opcode::v_cndmask_b32, bld.def(v1), else_lo, then_lo, cond);
 641          Temp dst1 = bld.vop2(aco_opcode::v_cndmask_b32, bld.def(v1), else_hi, then_hi, cond);
 642
 643          bld.pseudo(aco_opcode::p_create_vector, Definition(dst), dst0, dst1);
 644       } else {
 645          fprintf(stderr, "Unimplemented NIR instr bit size: ");
 646          nir_print_instr(&instr->instr, stderr);
 647          fprintf(stderr, "\n");
 648       }
 649       return;
 650    }
 651
 652    if (instr->dest.dest.ssa.bit_size == 1) {
 653       assert(dst.regClass() == bld.lm);
 654       assert(then.regClass() == bld.lm);
 655       assert(els.regClass() == bld.lm);
 656    }
 657
 658    if (!ctx->divergent_vals[instr->src[0].src.ssa->index]) { /* uniform condition and values in sgpr */
 659       if (dst.regClass() == s1 || dst.regClass() == s2) {
 660          assert((then.regClass() == s1 || then.regClass() == s2) && els.regClass() == then.regClass());
 661          assert(dst.size() == then.size());
 662          aco_opcode op = dst.regClass() == s1 ? aco_opcode::s_cselect_b32 : aco_opcode::s_cselect_b64;
 663          bld.sop2(op, Definition(dst), then, els, bld.scc(bool_to_scalar_condition(ctx, cond)));
 664       } else {
 665          fprintf(stderr, "Unimplemented uniform bcsel bit size: ");
 666          nir_print_instr(&instr->instr, stderr);
 667          fprintf(stderr, "\n");
 668       }
 669       return;
 670    }
 671
 672    /* divergent boolean bcsel
 673     * this implements bcsel on bools: dst = s0 ? s1 : s2
 674     * are going to be: dst = (s0 & s1) | (~s0 & s2) */
 675    assert(instr->dest.dest.ssa.bit_size == 1);
 676
 677    if (cond.id() != then.id())
 678       then = bld.sop2(Builder::s_and, bld.def(bld.lm), bld.def(s1, scc), cond, then);
 679
 680    if (cond.id() == els.id())
 681       bld.sop1(Builder::s_mov, Definition(dst), then);
 682    else
 683       bld.sop2(Builder::s_or, Definition(dst), bld.def(s1, scc), then,
 684                bld.sop2(Builder::s_andn2, bld.def(bld.lm), bld.def(s1, scc), els, cond));
 685 }
 686
 687 void emit_scaled_op(isel_context *ctx, Builder& bld, Definition dst, Temp val,
 688                     aco_opcode op, uint32_t undo)
 689 {
 690    /* multiply by 16777216 to handle denormals */
 691    Temp is_denormal = bld.vopc(aco_opcode::v_cmp_class_f32, bld.hint_vcc(bld.def(bld.lm)),
 692                                as_vgpr(ctx, val), bld.copy(bld.def(v1), Operand((1u << 7) | (1u << 4))));
 693    Temp scaled = bld.vop2(aco_opcode::v_mul_f32, bld.def(v1), Operand(0x4b800000u), val);
 694    scaled = bld.vop1(op, bld.def(v1), scaled);
 695    scaled = bld.vop2(aco_opcode::v_mul_f32, bld.def(v1), Operand(undo), scaled);
 696
 697    Temp not_scaled = bld.vop1(op, bld.def(v1), val);
 698
 699    bld.vop2(aco_opcode::v_cndmask_b32, dst, not_scaled, scaled, is_denormal);
 700 }
 701
 702 void emit_rcp(isel_context *ctx, Builder& bld, Definition dst, Temp val)
 703 {
 704    if (ctx->block->fp_mode.denorm32 == 0) {
 705       bld.vop1(aco_opcode::v_rcp_f32, dst, val);
 706       return;
 707    }
 708
 709    emit_scaled_op(ctx, bld, dst, val, aco_opcode::v_rcp_f32, 0x4b800000u);
 710 }
 711
 712 void emit_rsq(isel_context *ctx, Builder& bld, Definition dst, Temp val)
 713 {
 714    if (ctx->block->fp_mode.denorm32 == 0) {
 715       bld.vop1(aco_opcode::v_rsq_f32, dst, val);
 716       return;
 717    }
 718
 719    emit_scaled_op(ctx, bld, dst, val, aco_opcode::v_rsq_f32, 0x45800000u);
 720 }
 721
 722 void emit_sqrt(isel_context *ctx, Builder& bld, Definition dst, Temp val)
 723 {
 724    if (ctx->block->fp_mode.denorm32 == 0) {
 725       bld.vop1(aco_opcode::v_sqrt_f32, dst, val);
 726       return;
 727    }
 728
 729    emit_scaled_op(ctx, bld, dst, val, aco_opcode::v_sqrt_f32, 0x39800000u);
 730 }
 731
 732 void emit_log2(isel_context *ctx, Builder& bld, Definition dst, Temp val)
 733 {
 734    if (ctx->block->fp_mode.denorm32 == 0) {
 735       bld.vop1(aco_opcode::v_log_f32, dst, val);
 736       return;
 737    }
 738
 739    emit_scaled_op(ctx, bld, dst, val, aco_opcode::v_log_f32, 0xc1c00000u);
 740 }
 741
 742 Temp emit_trunc_f64(isel_context *ctx, Builder& bld, Definition dst, Temp val)
 743 {
 744    if (ctx->options->chip_class >= GFX7)
 745       return bld.vop1(aco_opcode::v_trunc_f64, Definition(dst), val);
 746
 747    /* GFX6 doesn't support V_TRUNC_F64, lower it. */
 748    /* TODO: create more efficient code! */
 749    if (val.type() == RegType::sgpr)
 750       val = as_vgpr(ctx, val);
 751
 752    /* Split the input value. */
 753    Temp val_lo = bld.tmp(v1), val_hi = bld.tmp(v1);
 754    bld.pseudo(aco_opcode::p_split_vector, Definition(val_lo), Definition(val_hi), val);
 755
 756    /* Extract the exponent and compute the unbiased value. */
 757    Temp exponent = bld.vop1(aco_opcode::v_frexp_exp_i32_f64, bld.def(v1), val);
 758
 759    /* Extract the fractional part. */
 760    Temp fract_mask = bld.pseudo(aco_opcode::p_create_vector, bld.def(v2), Operand(-1u), Operand(0x000fffffu));
 761    fract_mask = bld.vop3(aco_opcode::v_lshr_b64, bld.def(v2), fract_mask, exponent);
 762
 763    Temp fract_mask_lo = bld.tmp(v1), fract_mask_hi = bld.tmp(v1);
 764    bld.pseudo(aco_opcode::p_split_vector, Definition(fract_mask_lo), Definition(fract_mask_hi), fract_mask);
 765
 766    Temp fract_lo = bld.tmp(v1), fract_hi = bld.tmp(v1);
 767    Temp tmp = bld.vop1(aco_opcode::v_not_b32, bld.def(v1), fract_mask_lo);
 768    fract_lo = bld.vop2(aco_opcode::v_and_b32, bld.def(v1), val_lo, tmp);
 769    tmp = bld.vop1(aco_opcode::v_not_b32, bld.def(v1), fract_mask_hi);
 770    fract_hi = bld.vop2(aco_opcode::v_and_b32, bld.def(v1), val_hi, tmp);
 771
 772    /* Get the sign bit. */
 773    Temp sign = bld.vop2(aco_opcode::v_ashr_i32, bld.def(v1), Operand(31u), val_hi);
 774
 775    /* Decide the operation to apply depending on the unbiased exponent. */
 776    Temp exp_lt0 = bld.vopc_e64(aco_opcode::v_cmp_lt_i32, bld.hint_vcc(bld.def(bld.lm)), exponent, Operand(0u));
 777    Temp dst_lo = bld.vop2(aco_opcode::v_cndmask_b32, bld.def(v1), fract_lo, bld.copy(bld.def(v1), Operand(0u)), exp_lt0);
 778    Temp dst_hi = bld.vop2(aco_opcode::v_cndmask_b32, bld.def(v1), fract_hi, sign, exp_lt0);
 779    Temp exp_gt51 = bld.vopc_e64(aco_opcode::v_cmp_gt_i32, bld.def(s2), exponent, Operand(51u));
 780    dst_lo = bld.vop2(aco_opcode::v_cndmask_b32, bld.def(v1), dst_lo, val_lo, exp_gt51);
 781    dst_hi = bld.vop2(aco_opcode::v_cndmask_b32, bld.def(v1), dst_hi, val_hi, exp_gt51);
 782
 783    return bld.pseudo(aco_opcode::p_create_vector, Definition(dst), dst_lo, dst_hi);
 784 }
 785
 786 Temp emit_floor_f64(isel_context *ctx, Builder& bld, Definition dst, Temp val)
 787 {
 788    if (ctx->options->chip_class >= GFX7)
 789       return bld.vop1(aco_opcode::v_floor_f64, Definition(dst), val);
 790
 791    /* GFX6 doesn't support V_FLOOR_F64, lower it. */
 792    Temp src0 = as_vgpr(ctx, val);
 793
 794    Temp mask = bld.copy(bld.def(s1), Operand(3u)); /* isnan */
 795    Temp min_val = bld.pseudo(aco_opcode::p_create_vector, bld.def(s2), Operand(-1u), Operand(0x3fefffffu));
 796
 797    Temp isnan = bld.vopc_e64(aco_opcode::v_cmp_class_f64, bld.hint_vcc(bld.def(bld.lm)), src0, mask);
 798    Temp fract = bld.vop1(aco_opcode::v_fract_f64, bld.def(v2), src0);
 799    Temp min = bld.vop3(aco_opcode::v_min_f64, bld.def(v2), fract, min_val);
 800
 801    Temp then_lo = bld.tmp(v1), then_hi = bld.tmp(v1);
 802    bld.pseudo(aco_opcode::p_split_vector, Definition(then_lo), Definition(then_hi), src0);
 803    Temp else_lo = bld.tmp(v1), else_hi = bld.tmp(v1);
 804    bld.pseudo(aco_opcode::p_split_vector, Definition(else_lo), Definition(else_hi), min);
 805
 806    Temp dst0 = bld.vop2(aco_opcode::v_cndmask_b32, bld.def(v1), else_lo, then_lo, isnan);
 807    Temp dst1 = bld.vop2(aco_opcode::v_cndmask_b32, bld.def(v1), else_hi, then_hi, isnan);
 808
 809    Temp v = bld.pseudo(aco_opcode::p_create_vector, bld.def(v2), dst0, dst1);
 810
 811    Instruction* add = bld.vop3(aco_opcode::v_add_f64, Definition(dst), src0, v);
 812    static_cast<VOP3A_instruction*>(add)->neg[1] = true;
 813
 814    return add->definitions[0].getTemp();
 815 }
 816
 817 void visit_alu_instr(isel_context *ctx, nir_alu_instr *instr)
 818 {
 819    if (!instr->dest.dest.is_ssa) {
 820       fprintf(stderr, "nir alu dst not in ssa: ");
 821       nir_print_instr(&instr->instr, stderr);
 822       fprintf(stderr, "\n");
 823       abort();
 824    }
 825    Builder bld(ctx->program, ctx->block);
 826    Temp dst = get_ssa_temp(ctx, &instr->dest.dest.ssa);
 827    switch(instr->op) {
 828    case nir_op_vec2:
 829    case nir_op_vec3:
 830    case nir_op_vec4: {
 831       std::array<Temp,NIR_MAX_VEC_COMPONENTS> elems;
 832       aco_ptr<Pseudo_instruction> vec{create_instruction<Pseudo_instruction>(aco_opcode::p_create_vector, Format::PSEUDO, instr->dest.dest.ssa.num_components, 1)};
 833       for (unsigned i = 0; i < instr->dest.dest.ssa.num_components; ++i) {
 834          elems[i] = get_alu_src(ctx, instr->src[i]);
 835          vec->operands[i] = Operand{elems[i]};
 836       }
 837       vec->definitions[0] = Definition(dst);
 838       ctx->block->instructions.emplace_back(std::move(vec));
 839       ctx->allocated_vec.emplace(dst.id(), elems);
 840       break;
 841    }
 842    case nir_op_mov: {
 843       Temp src = get_alu_src(ctx, instr->src[0]);
 844       aco_ptr<Instruction> mov;
 845       if (dst.type() == RegType::sgpr) {
 846          if (src.type() == RegType::vgpr)
 847             bld.pseudo(aco_opcode::p_as_uniform, Definition(dst), src);
 848          else if (src.regClass() == s1)
 849             bld.sop1(aco_opcode::s_mov_b32, Definition(dst), src);
 850          else if (src.regClass() == s2)
 851             bld.sop1(aco_opcode::s_mov_b64, Definition(dst), src);
 852          else
 853             unreachable("wrong src register class for nir_op_imov");
 854       } else if (dst.regClass() == v1) {
 855          bld.vop1(aco_opcode::v_mov_b32, Definition(dst), src);
 856       } else if (dst.regClass() == v2) {
 857          bld.pseudo(aco_opcode::p_create_vector, Definition(dst), src);
 858       } else {
 859          nir_print_instr(&instr->instr, stderr);
 860          unreachable("Should have been lowered to scalar.");
 861       }
 862       break;
 863    }
 864    case nir_op_inot: {
 865       Temp src = get_alu_src(ctx, instr->src[0]);
 866       if (instr->dest.dest.ssa.bit_size == 1) {
 867          assert(src.regClass() == bld.lm);
 868          assert(dst.regClass() == bld.lm);
 869          /* Don't use s_andn2 here, this allows the optimizer to make a better decision */
 870          Temp tmp = bld.sop1(Builder::s_not, bld.def(bld.lm), bld.def(s1, scc), src);
 871          bld.sop2(Builder::s_and, Definition(dst), bld.def(s1, scc), tmp, Operand(exec, bld.lm));
 872       } else if (dst.regClass() == v1) {
 873          emit_vop1_instruction(ctx, instr, aco_opcode::v_not_b32, dst);
 874       } else if (dst.type() == RegType::sgpr) {
 875          aco_opcode opcode = dst.size() == 1 ? aco_opcode::s_not_b32 : aco_opcode::s_not_b64;
 876          bld.sop1(opcode, Definition(dst), bld.def(s1, scc), src);
 877       } else {
 878          fprintf(stderr, "Unimplemented NIR instr bit size: ");
 879          nir_print_instr(&instr->instr, stderr);
 880          fprintf(stderr, "\n");
 881       }
 882       break;
 883    }
 884    case nir_op_ineg: {
 885       Temp src = get_alu_src(ctx, instr->src[0]);
 886       if (dst.regClass() == v1) {
 887          bld.vsub32(Definition(dst), Operand(0u), Operand(src));
 888       } else if (dst.regClass() == s1) {
 889          bld.sop2(aco_opcode::s_mul_i32, Definition(dst), Operand((uint32_t) -1), src);
 890       } else if (dst.size() == 2) {
 891          Temp src0 = bld.tmp(dst.type(), 1);
 892          Temp src1 = bld.tmp(dst.type(), 1);
 893          bld.pseudo(aco_opcode::p_split_vector, Definition(src0), Definition(src1), src);
 894
 895          if (dst.regClass() == s2) {
 896             Temp carry = bld.tmp(s1);
 897             Temp dst0 = bld.sop2(aco_opcode::s_sub_u32, bld.def(s1), bld.scc(Definition(carry)), Operand(0u), src0);
 898             Temp dst1 = bld.sop2(aco_opcode::s_subb_u32, bld.def(s1), bld.def(s1, scc), Operand(0u), src1, carry);
 899             bld.pseudo(aco_opcode::p_create_vector, Definition(dst), dst0, dst1);
 900          } else {
 901             Temp lower = bld.tmp(v1);
 902             Temp borrow = bld.vsub32(Definition(lower), Operand(0u), src0, true).def(1).getTemp();
 903             Temp upper = bld.vsub32(bld.def(v1), Operand(0u), src1, false, borrow);
 904             bld.pseudo(aco_opcode::p_create_vector, Definition(dst), lower, upper);
 905          }
 906       } else {
 907          fprintf(stderr, "Unimplemented NIR instr bit size: ");
 908          nir_print_instr(&instr->instr, stderr);
 909          fprintf(stderr, "\n");
 910       }
 911       break;
 912    }
 913    case nir_op_iabs: {
 914       if (dst.regClass() == s1) {
 915          bld.sop1(aco_opcode::s_abs_i32, Definition(dst), bld.def(s1, scc), get_alu_src(ctx, instr->src[0]));
 916       } else if (dst.regClass() == v1) {
 917          Temp src = get_alu_src(ctx, instr->src[0]);
 918          bld.vop2(aco_opcode::v_max_i32, Definition(dst), src, bld.vsub32(bld.def(v1), Operand(0u), src));
 919       } else {
 920          fprintf(stderr, "Unimplemented NIR instr bit size: ");
 921          nir_print_instr(&instr->instr, stderr);
 922          fprintf(stderr, "\n");
 923       }
 924       break;
 925    }
 926    case nir_op_isign: {
 927       Temp src = get_alu_src(ctx, instr->src[0]);
 928       if (dst.regClass() == s1) {
 929          Temp tmp = bld.sop2(aco_opcode::s_ashr_i32, bld.def(s1), bld.def(s1, scc), src, Operand(31u));
 930          Temp gtz = bld.sopc(aco_opcode::s_cmp_gt_i32, bld.def(s1, scc), src, Operand(0u));
 931          bld.sop2(aco_opcode::s_add_i32, Definition(dst), bld.def(s1, scc), gtz, tmp);
 932       } else if (dst.regClass() == s2) {
 933          Temp neg = bld.sop2(aco_opcode::s_ashr_i64, bld.def(s2), bld.def(s1, scc), src, Operand(63u));
 934          Temp neqz;
 935          if (ctx->program->chip_class >= GFX8)
 936             neqz = bld.sopc(aco_opcode::s_cmp_lg_u64, bld.def(s1, scc), src, Operand(0u));
 937          else
 938             neqz = bld.sop2(aco_opcode::s_or_b64, bld.def(s2), bld.def(s1, scc), src, Operand(0u)).def(1).getTemp();
 939          /* SCC gets zero-extended to 64 bit */
 940          bld.sop2(aco_opcode::s_or_b64, Definition(dst), bld.def(s1, scc), neg, bld.scc(neqz));
 941       } else if (dst.regClass() == v1) {
 942          Temp tmp = bld.vop2(aco_opcode::v_ashrrev_i32, bld.def(v1), Operand(31u), src);
 943          Temp gtz = bld.vopc(aco_opcode::v_cmp_ge_i32, bld.hint_vcc(bld.def(bld.lm)), Operand(0u), src);
 944          bld.vop2(aco_opcode::v_cndmask_b32, Definition(dst), Operand(1u), tmp, gtz);
 945       } else if (dst.regClass() == v2) {
 946          Temp upper = emit_extract_vector(ctx, src, 1, v1);
 947          Temp neg = bld.vop2(aco_opcode::v_ashrrev_i32, bld.def(v1), Operand(31u), upper);
 948          Temp gtz = bld.vopc(aco_opcode::v_cmp_ge_i64, bld.hint_vcc(bld.def(bld.lm)), Operand(0u), src);
 949          Temp lower = bld.vop2(aco_opcode::v_cndmask_b32, bld.def(v1), Operand(1u), neg, gtz);
 950          upper = bld.vop2(aco_opcode::v_cndmask_b32, bld.def(v1), Operand(0u), neg, gtz);
 951          bld.pseudo(aco_opcode::p_create_vector, Definition(dst), lower, upper);
 952       } else {
 953          fprintf(stderr, "Unimplemented NIR instr bit size: ");
 954          nir_print_instr(&instr->instr, stderr);
 955          fprintf(stderr, "\n");
 956       }
 957       break;
 958    }
 959    case nir_op_imax: {
 960       if (dst.regClass() == v1) {
 961          emit_vop2_instruction(ctx, instr, aco_opcode::v_max_i32, dst, true);
 962       } else if (dst.regClass() == s1) {
 963          emit_sop2_instruction(ctx, instr, aco_opcode::s_max_i32, dst, true);
 964       } else {
 965          fprintf(stderr, "Unimplemented NIR instr bit size: ");
 966          nir_print_instr(&instr->instr, stderr);
 967          fprintf(stderr, "\n");
 968       }
 969       break;
 970    }
 971    case nir_op_umax: {
 972       if (dst.regClass() == v1) {
 973          emit_vop2_instruction(ctx, instr, aco_opcode::v_max_u32, dst, true);
 974       } else if (dst.regClass() == s1) {
 975          emit_sop2_instruction(ctx, instr, aco_opcode::s_max_u32, dst, true);
 976       } else {
 977          fprintf(stderr, "Unimplemented NIR instr bit size: ");
 978          nir_print_instr(&instr->instr, stderr);
 979          fprintf(stderr, "\n");
 980       }
 981       break;
 982    }
 983    case nir_op_imin: {
 984       if (dst.regClass() == v1) {
 985          emit_vop2_instruction(ctx, instr, aco_opcode::v_min_i32, dst, true);
 986       } else if (dst.regClass() == s1) {
 987          emit_sop2_instruction(ctx, instr, aco_opcode::s_min_i32, dst, true);
 988       } else {
 989          fprintf(stderr, "Unimplemented NIR instr bit size: ");
 990          nir_print_instr(&instr->instr, stderr);
 991          fprintf(stderr, "\n");
 992       }
 993       break;
 994    }
 995    case nir_op_umin: {
 996       if (dst.regClass() == v1) {
 997          emit_vop2_instruction(ctx, instr, aco_opcode::v_min_u32, dst, true);
 998       } else if (dst.regClass() == s1) {
 999          emit_sop2_instruction(ctx, instr, aco_opcode::s_min_u32, dst, true);
1000       } else {
1001          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1002          nir_print_instr(&instr->instr, stderr);
1003          fprintf(stderr, "\n");
1004       }
1005       break;
1006    }
1007    case nir_op_ior: {
1008       if (instr->dest.dest.ssa.bit_size == 1) {
1009          emit_boolean_logic(ctx, instr, Builder::s_or, dst);
1010       } else if (dst.regClass() == v1) {
1011          emit_vop2_instruction(ctx, instr, aco_opcode::v_or_b32, dst, true);
1012       } else if (dst.regClass() == s1) {
1013          emit_sop2_instruction(ctx, instr, aco_opcode::s_or_b32, dst, true);
1014       } else if (dst.regClass() == s2) {
1015          emit_sop2_instruction(ctx, instr, aco_opcode::s_or_b64, dst, true);
1016       } else {
1017          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1018          nir_print_instr(&instr->instr, stderr);
1019          fprintf(stderr, "\n");
1020       }
1021       break;
1022    }
1023    case nir_op_iand: {
1024       if (instr->dest.dest.ssa.bit_size == 1) {
1025          emit_boolean_logic(ctx, instr, Builder::s_and, dst);
1026       } else if (dst.regClass() == v1) {
1027          emit_vop2_instruction(ctx, instr, aco_opcode::v_and_b32, dst, true);
1028       } else if (dst.regClass() == s1) {
1029          emit_sop2_instruction(ctx, instr, aco_opcode::s_and_b32, dst, true);
1030       } else if (dst.regClass() == s2) {
1031          emit_sop2_instruction(ctx, instr, aco_opcode::s_and_b64, dst, true);
1032       } else {
1033          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1034          nir_print_instr(&instr->instr, stderr);
1035          fprintf(stderr, "\n");
1036       }
1037       break;
1038    }
1039    case nir_op_ixor: {
1040       if (instr->dest.dest.ssa.bit_size == 1) {
1041          emit_boolean_logic(ctx, instr, Builder::s_xor, dst);
1042       } else if (dst.regClass() == v1) {
1043          emit_vop2_instruction(ctx, instr, aco_opcode::v_xor_b32, dst, true);
1044       } else if (dst.regClass() == s1) {
1045          emit_sop2_instruction(ctx, instr, aco_opcode::s_xor_b32, dst, true);
1046       } else if (dst.regClass() == s2) {
1047          emit_sop2_instruction(ctx, instr, aco_opcode::s_xor_b64, dst, true);
1048       } else {
1049          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1050          nir_print_instr(&instr->instr, stderr);
1051          fprintf(stderr, "\n");
1052       }
1053       break;
1054    }
1055    case nir_op_ushr: {
1056       if (dst.regClass() == v1) {
1057          emit_vop2_instruction(ctx, instr, aco_opcode::v_lshrrev_b32, dst, false, true);
1058       } else if (dst.regClass() == v2 && ctx->program->chip_class >= GFX8) {
1059          bld.vop3(aco_opcode::v_lshrrev_b64, Definition(dst),
1060                   get_alu_src(ctx, instr->src[1]), get_alu_src(ctx, instr->src[0]));
1061       } else if (dst.regClass() == v2) {
1062          bld.vop3(aco_opcode::v_lshr_b64, Definition(dst),
1063                   get_alu_src(ctx, instr->src[0]), get_alu_src(ctx, instr->src[1]));
1064       } else if (dst.regClass() == s2) {
1065          emit_sop2_instruction(ctx, instr, aco_opcode::s_lshr_b64, dst, true);
1066       } else if (dst.regClass() == s1) {
1067          emit_sop2_instruction(ctx, instr, aco_opcode::s_lshr_b32, dst, true);
1068       } else {
1069          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1070          nir_print_instr(&instr->instr, stderr);
1071          fprintf(stderr, "\n");
1072       }
1073       break;
1074    }
1075    case nir_op_ishl: {
1076       if (dst.regClass() == v1) {
1077          emit_vop2_instruction(ctx, instr, aco_opcode::v_lshlrev_b32, dst, false, true);
1078       } else if (dst.regClass() == v2 && ctx->program->chip_class >= GFX8) {
1079          bld.vop3(aco_opcode::v_lshlrev_b64, Definition(dst),
1080                   get_alu_src(ctx, instr->src[1]), get_alu_src(ctx, instr->src[0]));
1081       } else if (dst.regClass() == v2) {
1082          bld.vop3(aco_opcode::v_lshl_b64, Definition(dst),
1083                   get_alu_src(ctx, instr->src[0]), get_alu_src(ctx, instr->src[1]));
1084       } else if (dst.regClass() == s1) {
1085          emit_sop2_instruction(ctx, instr, aco_opcode::s_lshl_b32, dst, true);
1086       } else if (dst.regClass() == s2) {
1087          emit_sop2_instruction(ctx, instr, aco_opcode::s_lshl_b64, dst, true);
1088       } else {
1089          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1090          nir_print_instr(&instr->instr, stderr);
1091          fprintf(stderr, "\n");
1092       }
1093       break;
1094    }
1095    case nir_op_ishr: {
1096       if (dst.regClass() == v1) {
1097          emit_vop2_instruction(ctx, instr, aco_opcode::v_ashrrev_i32, dst, false, true);
1098       } else if (dst.regClass() == v2 && ctx->program->chip_class >= GFX8) {
1099          bld.vop3(aco_opcode::v_ashrrev_i64, Definition(dst),
1100                   get_alu_src(ctx, instr->src[1]), get_alu_src(ctx, instr->src[0]));
1101       } else if (dst.regClass() == v2) {
1102          bld.vop3(aco_opcode::v_ashr_i64, Definition(dst),
1103                   get_alu_src(ctx, instr->src[0]), get_alu_src(ctx, instr->src[1]));
1104       } else if (dst.regClass() == s1) {
1105          emit_sop2_instruction(ctx, instr, aco_opcode::s_ashr_i32, dst, true);
1106       } else if (dst.regClass() == s2) {
1107          emit_sop2_instruction(ctx, instr, aco_opcode::s_ashr_i64, dst, true);
1108       } else {
1109          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1110          nir_print_instr(&instr->instr, stderr);
1111          fprintf(stderr, "\n");
1112       }
1113       break;
1114    }
1115    case nir_op_find_lsb: {
1116       Temp src = get_alu_src(ctx, instr->src[0]);
1117       if (src.regClass() == s1) {
1118          bld.sop1(aco_opcode::s_ff1_i32_b32, Definition(dst), src);
1119       } else if (src.regClass() == v1) {
1120          emit_vop1_instruction(ctx, instr, aco_opcode::v_ffbl_b32, dst);
1121       } else if (src.regClass() == s2) {
1122          bld.sop1(aco_opcode::s_ff1_i32_b64, Definition(dst), src);
1123       } else {
1124          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1125          nir_print_instr(&instr->instr, stderr);
1126          fprintf(stderr, "\n");
1127       }
1128       break;
1129    }
1130    case nir_op_ufind_msb:
1131    case nir_op_ifind_msb: {
1132       Temp src = get_alu_src(ctx, instr->src[0]);
1133       if (src.regClass() == s1 || src.regClass() == s2) {
1134          aco_opcode op = src.regClass() == s2 ?
1135                          (instr->op == nir_op_ufind_msb ? aco_opcode::s_flbit_i32_b64 : aco_opcode::s_flbit_i32_i64) :
1136                          (instr->op == nir_op_ufind_msb ? aco_opcode::s_flbit_i32_b32 : aco_opcode::s_flbit_i32);
1137          Temp msb_rev = bld.sop1(op, bld.def(s1), src);
1138
1139          Builder::Result sub = bld.sop2(aco_opcode::s_sub_u32, bld.def(s1), bld.def(s1, scc),
1140                                         Operand(src.size() * 32u - 1u), msb_rev);
1141          Temp msb = sub.def(0).getTemp();
1142          Temp carry = sub.def(1).getTemp();
1143
1144          bld.sop2(aco_opcode::s_cselect_b32, Definition(dst), Operand((uint32_t)-1), msb, bld.scc(carry));
1145       } else if (src.regClass() == v1) {
1146          aco_opcode op = instr->op == nir_op_ufind_msb ? aco_opcode::v_ffbh_u32 : aco_opcode::v_ffbh_i32;
1147          Temp msb_rev = bld.tmp(v1);
1148          emit_vop1_instruction(ctx, instr, op, msb_rev);
1149          Temp msb = bld.tmp(v1);
1150          Temp carry = bld.vsub32(Definition(msb), Operand(31u), Operand(msb_rev), true).def(1).getTemp();
1151          bld.vop2_e64(aco_opcode::v_cndmask_b32, Definition(dst), msb, Operand((uint32_t)-1), carry);
1152       } else {
1153          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1154          nir_print_instr(&instr->instr, stderr);
1155          fprintf(stderr, "\n");
1156       }
1157       break;
1158    }
1159    case nir_op_bitfield_reverse: {
1160       if (dst.regClass() == s1) {
1161          bld.sop1(aco_opcode::s_brev_b32, Definition(dst), get_alu_src(ctx, instr->src[0]));
1162       } else if (dst.regClass() == v1) {
1163          bld.vop1(aco_opcode::v_bfrev_b32, Definition(dst), get_alu_src(ctx, instr->src[0]));
1164       } else {
1165          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1166          nir_print_instr(&instr->instr, stderr);
1167          fprintf(stderr, "\n");
1168       }
1169       break;
1170    }
1171    case nir_op_iadd: {
1172       if (dst.regClass() == s1) {
1173          emit_sop2_instruction(ctx, instr, aco_opcode::s_add_u32, dst, true);
1174          break;
1175       }
1176
1177       Temp src0 = get_alu_src(ctx, instr->src[0]);
1178       Temp src1 = get_alu_src(ctx, instr->src[1]);
1179       if (dst.regClass() == v1) {
1180          bld.vadd32(Definition(dst), Operand(src0), Operand(src1));
1181          break;
1182       }
1183
1184       assert(src0.size() == 2 && src1.size() == 2);
1185       Temp src00 = bld.tmp(src0.type(), 1);
1186       Temp src01 = bld.tmp(dst.type(), 1);
1187       bld.pseudo(aco_opcode::p_split_vector, Definition(src00), Definition(src01), src0);
1188       Temp src10 = bld.tmp(src1.type(), 1);
1189       Temp src11 = bld.tmp(dst.type(), 1);
1190       bld.pseudo(aco_opcode::p_split_vector, Definition(src10), Definition(src11), src1);
1191
1192       if (dst.regClass() == s2) {
1193          Temp carry = bld.tmp(s1);
1194          Temp dst0 = bld.sop2(aco_opcode::s_add_u32, bld.def(s1), bld.scc(Definition(carry)), src00, src10);
1195          Temp dst1 = bld.sop2(aco_opcode::s_addc_u32, bld.def(s1), bld.def(s1, scc), src01, src11, bld.scc(carry));
1196          bld.pseudo(aco_opcode::p_create_vector, Definition(dst), dst0, dst1);
1197       } else if (dst.regClass() == v2) {
1198          Temp dst0 = bld.tmp(v1);
1199          Temp carry = bld.vadd32(Definition(dst0), src00, src10, true).def(1).getTemp();
1200          Temp dst1 = bld.vadd32(bld.def(v1), src01, src11, false, carry);
1201          bld.pseudo(aco_opcode::p_create_vector, Definition(dst), dst0, dst1);
1202       } else {
1203          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1204          nir_print_instr(&instr->instr, stderr);
1205          fprintf(stderr, "\n");
1206       }
1207       break;
1208    }
1209    case nir_op_uadd_sat: {
1210       Temp src0 = get_alu_src(ctx, instr->src[0]);
1211       Temp src1 = get_alu_src(ctx, instr->src[1]);
1212       if (dst.regClass() == s1) {
1213          Temp tmp = bld.tmp(s1), carry = bld.tmp(s1);
1214          bld.sop2(aco_opcode::s_add_u32, Definition(tmp), bld.scc(Definition(carry)),
1215                   src0, src1);
1216          bld.sop2(aco_opcode::s_cselect_b32, Definition(dst), Operand((uint32_t) -1), tmp, bld.scc(carry));
1217       } else if (dst.regClass() == v1) {
1218          if (ctx->options->chip_class >= GFX9) {
1219             aco_ptr<VOP3A_instruction> add{create_instruction<VOP3A_instruction>(aco_opcode::v_add_u32, asVOP3(Format::VOP2), 2, 1)};
1220             add->operands[0] = Operand(src0);
1221             add->operands[1] = Operand(src1);
1222             add->definitions[0] = Definition(dst);
1223             add->clamp = 1;
1224             ctx->block->instructions.emplace_back(std::move(add));
1225          } else {
1226             if (src1.regClass() != v1)
1227                std::swap(src0, src1);
1228             assert(src1.regClass() == v1);
1229             Temp tmp = bld.tmp(v1);
1230             Temp carry = bld.vadd32(Definition(tmp), src0, src1, true).def(1).getTemp();
1231             bld.vop2_e64(aco_opcode::v_cndmask_b32, Definition(dst), tmp, Operand((uint32_t) -1), carry);
1232          }
1233       } else {
1234          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1235          nir_print_instr(&instr->instr, stderr);
1236          fprintf(stderr, "\n");
1237       }
1238       break;
1239    }
1240    case nir_op_uadd_carry: {
1241       Temp src0 = get_alu_src(ctx, instr->src[0]);
1242       Temp src1 = get_alu_src(ctx, instr->src[1]);
1243       if (dst.regClass() == s1) {
1244          bld.sop2(aco_opcode::s_add_u32, bld.def(s1), bld.scc(Definition(dst)), src0, src1);
1245          break;
1246       }
1247       if (dst.regClass() == v1) {
1248          Temp carry = bld.vadd32(bld.def(v1), src0, src1, true).def(1).getTemp();
1249          bld.vop2_e64(aco_opcode::v_cndmask_b32, Definition(dst), Operand(0u), Operand(1u), carry);
1250          break;
1251       }
1252
1253       Temp src00 = bld.tmp(src0.type(), 1);
1254       Temp src01 = bld.tmp(dst.type(), 1);
1255       bld.pseudo(aco_opcode::p_split_vector, Definition(src00), Definition(src01), src0);
1256       Temp src10 = bld.tmp(src1.type(), 1);
1257       Temp src11 = bld.tmp(dst.type(), 1);
1258       bld.pseudo(aco_opcode::p_split_vector, Definition(src10), Definition(src11), src1);
1259       if (dst.regClass() == s2) {
1260          Temp carry = bld.tmp(s1);
1261          bld.sop2(aco_opcode::s_add_u32, bld.def(s1), bld.scc(Definition(carry)), src00, src10);
1262          carry = bld.sop2(aco_opcode::s_addc_u32, bld.def(s1), bld.scc(bld.def(s1)), src01, src11, bld.scc(carry)).def(1).getTemp();
1263          bld.pseudo(aco_opcode::p_create_vector, Definition(dst), carry, Operand(0u));
1264       } else if (dst.regClass() == v2) {
1265          Temp carry = bld.vadd32(bld.def(v1), src00, src10, true).def(1).getTemp();
1266          carry = bld.vadd32(bld.def(v1), src01, src11, true, carry).def(1).getTemp();
1267          carry = bld.vop2_e64(aco_opcode::v_cndmask_b32, bld.def(v1), Operand(0u), Operand(1u), carry);
1268          bld.pseudo(aco_opcode::p_create_vector, Definition(dst), carry, Operand(0u));
1269       } else {
1270          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1271          nir_print_instr(&instr->instr, stderr);
1272          fprintf(stderr, "\n");
1273       }
1274       break;
1275    }
1276    case nir_op_isub: {
1277       if (dst.regClass() == s1) {
1278          emit_sop2_instruction(ctx, instr, aco_opcode::s_sub_i32, dst, true);
1279          break;
1280       }
1281
1282       Temp src0 = get_alu_src(ctx, instr->src[0]);
1283       Temp src1 = get_alu_src(ctx, instr->src[1]);
1284       if (dst.regClass() == v1) {
1285          bld.vsub32(Definition(dst), src0, src1);
1286          break;
1287       }
1288
1289       Temp src00 = bld.tmp(src0.type(), 1);
1290       Temp src01 = bld.tmp(dst.type(), 1);
1291       bld.pseudo(aco_opcode::p_split_vector, Definition(src00), Definition(src01), src0);
1292       Temp src10 = bld.tmp(src1.type(), 1);
1293       Temp src11 = bld.tmp(dst.type(), 1);
1294       bld.pseudo(aco_opcode::p_split_vector, Definition(src10), Definition(src11), src1);
1295       if (dst.regClass() == s2) {
1296          Temp carry = bld.tmp(s1);
1297          Temp dst0 = bld.sop2(aco_opcode::s_sub_u32, bld.def(s1), bld.scc(Definition(carry)), src00, src10);
1298          Temp dst1 = bld.sop2(aco_opcode::s_subb_u32, bld.def(s1), bld.def(s1, scc), src01, src11, carry);
1299          bld.pseudo(aco_opcode::p_create_vector, Definition(dst), dst0, dst1);
1300       } else if (dst.regClass() == v2) {
1301          Temp lower = bld.tmp(v1);
1302          Temp borrow = bld.vsub32(Definition(lower), src00, src10, true).def(1).getTemp();
1303          Temp upper = bld.vsub32(bld.def(v1), src01, src11, false, borrow);
1304          bld.pseudo(aco_opcode::p_create_vector, Definition(dst), lower, upper);
1305       } else {
1306          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1307          nir_print_instr(&instr->instr, stderr);
1308          fprintf(stderr, "\n");
1309       }
1310       break;
1311    }
1312    case nir_op_usub_borrow: {
1313       Temp src0 = get_alu_src(ctx, instr->src[0]);
1314       Temp src1 = get_alu_src(ctx, instr->src[1]);
1315       if (dst.regClass() == s1) {
1316          bld.sop2(aco_opcode::s_sub_u32, bld.def(s1), bld.scc(Definition(dst)), src0, src1);
1317          break;
1318       } else if (dst.regClass() == v1) {
1319          Temp borrow = bld.vsub32(bld.def(v1), src0, src1, true).def(1).getTemp();
1320          bld.vop2_e64(aco_opcode::v_cndmask_b32, Definition(dst), Operand(0u), Operand(1u), borrow);
1321          break;
1322       }
1323
1324       Temp src00 = bld.tmp(src0.type(), 1);
1325       Temp src01 = bld.tmp(dst.type(), 1);
1326       bld.pseudo(aco_opcode::p_split_vector, Definition(src00), Definition(src01), src0);
1327       Temp src10 = bld.tmp(src1.type(), 1);
1328       Temp src11 = bld.tmp(dst.type(), 1);
1329       bld.pseudo(aco_opcode::p_split_vector, Definition(src10), Definition(src11), src1);
1330       if (dst.regClass() == s2) {
1331          Temp borrow = bld.tmp(s1);
1332          bld.sop2(aco_opcode::s_sub_u32, bld.def(s1), bld.scc(Definition(borrow)), src00, src10);
1333          borrow = bld.sop2(aco_opcode::s_subb_u32, bld.def(s1), bld.scc(bld.def(s1)), src01, src11, bld.scc(borrow)).def(1).getTemp();
1334          bld.pseudo(aco_opcode::p_create_vector, Definition(dst), borrow, Operand(0u));
1335       } else if (dst.regClass() == v2) {
1336          Temp borrow = bld.vsub32(bld.def(v1), src00, src10, true).def(1).getTemp();
1337          borrow = bld.vsub32(bld.def(v1), src01, src11, true, Operand(borrow)).def(1).getTemp();
1338          borrow = bld.vop2_e64(aco_opcode::v_cndmask_b32, bld.def(v1), Operand(0u), Operand(1u), borrow);
1339          bld.pseudo(aco_opcode::p_create_vector, Definition(dst), borrow, Operand(0u));
1340       } else {
1341          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1342          nir_print_instr(&instr->instr, stderr);
1343          fprintf(stderr, "\n");
1344       }
1345       break;
1346    }
1347    case nir_op_imul: {
1348       if (dst.regClass() == v1) {
1349          bld.vop3(aco_opcode::v_mul_lo_u32, Definition(dst),
1350                   get_alu_src(ctx, instr->src[0]), get_alu_src(ctx, instr->src[1]));
1351       } else if (dst.regClass() == s1) {
1352          emit_sop2_instruction(ctx, instr, aco_opcode::s_mul_i32, dst, false);
1353       } else {
1354          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1355          nir_print_instr(&instr->instr, stderr);
1356          fprintf(stderr, "\n");
1357       }
1358       break;
1359    }
1360    case nir_op_umul_high: {
1361       if (dst.regClass() == v1) {
1362          bld.vop3(aco_opcode::v_mul_hi_u32, Definition(dst), get_alu_src(ctx, instr->src[0]), get_alu_src(ctx, instr->src[1]));
1363       } else if (dst.regClass() == s1 && ctx->options->chip_class >= GFX9) {
1364          bld.sop2(aco_opcode::s_mul_hi_u32, Definition(dst), get_alu_src(ctx, instr->src[0]), get_alu_src(ctx, instr->src[1]));
1365       } else if (dst.regClass() == s1) {
1366          Temp tmp = bld.vop3(aco_opcode::v_mul_hi_u32, bld.def(v1), get_alu_src(ctx, instr->src[0]),
1367                              as_vgpr(ctx, get_alu_src(ctx, instr->src[1])));
1368          bld.pseudo(aco_opcode::p_as_uniform, Definition(dst), tmp);
1369       } else {
1370          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1371          nir_print_instr(&instr->instr, stderr);
1372          fprintf(stderr, "\n");
1373       }
1374       break;
1375    }
1376    case nir_op_imul_high: {
1377       if (dst.regClass() == v1) {
1378          bld.vop3(aco_opcode::v_mul_hi_i32, Definition(dst), get_alu_src(ctx, instr->src[0]), get_alu_src(ctx, instr->src[1]));
1379       } else if (dst.regClass() == s1 && ctx->options->chip_class >= GFX9) {
1380          bld.sop2(aco_opcode::s_mul_hi_i32, Definition(dst), get_alu_src(ctx, instr->src[0]), get_alu_src(ctx, instr->src[1]));
1381       } else if (dst.regClass() == s1) {
1382          Temp tmp = bld.vop3(aco_opcode::v_mul_hi_i32, bld.def(v1), get_alu_src(ctx, instr->src[0]),
1383                              as_vgpr(ctx, get_alu_src(ctx, instr->src[1])));
1384          bld.pseudo(aco_opcode::p_as_uniform, Definition(dst), tmp);
1385       } else {
1386          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1387          nir_print_instr(&instr->instr, stderr);
1388          fprintf(stderr, "\n");
1389       }
1390       break;
1391    }
1392    case nir_op_fmul: {
1393       if (dst.size() == 1) {
1394          emit_vop2_instruction(ctx, instr, aco_opcode::v_mul_f32, dst, true);
1395       } else if (dst.size() == 2) {
1396          bld.vop3(aco_opcode::v_mul_f64, Definition(dst), get_alu_src(ctx, instr->src[0]),
1397                   as_vgpr(ctx, get_alu_src(ctx, instr->src[1])));
1398       } else {
1399          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1400          nir_print_instr(&instr->instr, stderr);
1401          fprintf(stderr, "\n");
1402       }
1403       break;
1404    }
1405    case nir_op_fadd: {
1406       if (dst.size() == 1) {
1407          emit_vop2_instruction(ctx, instr, aco_opcode::v_add_f32, dst, true);
1408       } else if (dst.size() == 2) {
1409          bld.vop3(aco_opcode::v_add_f64, Definition(dst), get_alu_src(ctx, instr->src[0]),
1410                   as_vgpr(ctx, get_alu_src(ctx, instr->src[1])));
1411       } else {
1412          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1413          nir_print_instr(&instr->instr, stderr);
1414          fprintf(stderr, "\n");
1415       }
1416       break;
1417    }
1418    case nir_op_fsub: {
1419       Temp src0 = get_alu_src(ctx, instr->src[0]);
1420       Temp src1 = get_alu_src(ctx, instr->src[1]);
1421       if (dst.size() == 1) {
1422          if (src1.type() == RegType::vgpr || src0.type() != RegType::vgpr)
1423             emit_vop2_instruction(ctx, instr, aco_opcode::v_sub_f32, dst, false);
1424          else
1425             emit_vop2_instruction(ctx, instr, aco_opcode::v_subrev_f32, dst, true);
1426       } else if (dst.size() == 2) {
1427          Instruction* add = bld.vop3(aco_opcode::v_add_f64, Definition(dst),
1428                                      get_alu_src(ctx, instr->src[0]),
1429                                      as_vgpr(ctx, get_alu_src(ctx, instr->src[1])));
1430          VOP3A_instruction* sub = static_cast<VOP3A_instruction*>(add);
1431          sub->neg[1] = true;
1432       } else {
1433          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1434          nir_print_instr(&instr->instr, stderr);
1435          fprintf(stderr, "\n");
1436       }
1437       break;
1438    }
1439    case nir_op_fmax: {
1440       if (dst.size() == 1) {
1441          emit_vop2_instruction(ctx, instr, aco_opcode::v_max_f32, dst, true, false, ctx->block->fp_mode.must_flush_denorms32);
1442       } else if (dst.size() == 2) {
1443          if (ctx->block->fp_mode.must_flush_denorms16_64 && ctx->program->chip_class < GFX9) {
1444             Temp tmp = bld.vop3(aco_opcode::v_max_f64, bld.def(v2),
1445                                 get_alu_src(ctx, instr->src[0]),
1446                                 as_vgpr(ctx, get_alu_src(ctx, instr->src[1])));
1447             bld.vop3(aco_opcode::v_mul_f64, Definition(dst), Operand(0x3FF0000000000000lu), tmp);
1448          } else {
1449             bld.vop3(aco_opcode::v_max_f64, Definition(dst),
1450                      get_alu_src(ctx, instr->src[0]),
1451                      as_vgpr(ctx, get_alu_src(ctx, instr->src[1])));
1452          }
1453       } else {
1454          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1455          nir_print_instr(&instr->instr, stderr);
1456          fprintf(stderr, "\n");
1457       }
1458       break;
1459    }
1460    case nir_op_fmin: {
1461       if (dst.size() == 1) {
1462          emit_vop2_instruction(ctx, instr, aco_opcode::v_min_f32, dst, true, false, ctx->block->fp_mode.must_flush_denorms32);
1463       } else if (dst.size() == 2) {
1464          if (ctx->block->fp_mode.must_flush_denorms16_64 && ctx->program->chip_class < GFX9) {
1465             Temp tmp = bld.vop3(aco_opcode::v_min_f64, bld.def(v2),
1466                                 get_alu_src(ctx, instr->src[0]),
1467                                 as_vgpr(ctx, get_alu_src(ctx, instr->src[1])));
1468             bld.vop3(aco_opcode::v_mul_f64, Definition(dst), Operand(0x3FF0000000000000lu), tmp);
1469          } else {
1470             bld.vop3(aco_opcode::v_min_f64, Definition(dst),
1471                      get_alu_src(ctx, instr->src[0]),
1472                      as_vgpr(ctx, get_alu_src(ctx, instr->src[1])));
1473          }
1474       } else {
1475          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1476          nir_print_instr(&instr->instr, stderr);
1477          fprintf(stderr, "\n");
1478       }
1479       break;
1480    }
1481    case nir_op_fmax3: {
1482       if (dst.size() == 1) {
1483          emit_vop3a_instruction(ctx, instr, aco_opcode::v_max3_f32, dst, ctx->block->fp_mode.must_flush_denorms32);
1484       } else {
1485          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1486          nir_print_instr(&instr->instr, stderr);
1487          fprintf(stderr, "\n");
1488       }
1489       break;
1490    }
1491    case nir_op_fmin3: {
1492       if (dst.size() == 1) {
1493          emit_vop3a_instruction(ctx, instr, aco_opcode::v_min3_f32, dst, ctx->block->fp_mode.must_flush_denorms32);
1494       } else {
1495          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1496          nir_print_instr(&instr->instr, stderr);
1497          fprintf(stderr, "\n");
1498       }
1499       break;
1500    }
1501    case nir_op_fmed3: {
1502       if (dst.size() == 1) {
1503          emit_vop3a_instruction(ctx, instr, aco_opcode::v_med3_f32, dst, ctx->block->fp_mode.must_flush_denorms32);
1504       } else {
1505          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1506          nir_print_instr(&instr->instr, stderr);
1507          fprintf(stderr, "\n");
1508       }
1509       break;
1510    }
1511    case nir_op_umax3: {
1512       if (dst.size() == 1) {
1513          emit_vop3a_instruction(ctx, instr, aco_opcode::v_max3_u32, dst);
1514       } else {
1515          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1516          nir_print_instr(&instr->instr, stderr);
1517          fprintf(stderr, "\n");
1518       }
1519       break;
1520    }
1521    case nir_op_umin3: {
1522       if (dst.size() == 1) {
1523          emit_vop3a_instruction(ctx, instr, aco_opcode::v_min3_u32, dst);
1524       } else {
1525          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1526          nir_print_instr(&instr->instr, stderr);
1527          fprintf(stderr, "\n");
1528       }
1529       break;
1530    }
1531    case nir_op_umed3: {
1532       if (dst.size() == 1) {
1533          emit_vop3a_instruction(ctx, instr, aco_opcode::v_med3_u32, dst);
1534       } else {
1535          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1536          nir_print_instr(&instr->instr, stderr);
1537          fprintf(stderr, "\n");
1538       }
1539       break;
1540    }
1541    case nir_op_imax3: {
1542       if (dst.size() == 1) {
1543          emit_vop3a_instruction(ctx, instr, aco_opcode::v_max3_i32, dst);
1544       } else {
1545          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1546          nir_print_instr(&instr->instr, stderr);
1547          fprintf(stderr, "\n");
1548       }
1549       break;
1550    }
1551    case nir_op_imin3: {
1552       if (dst.size() == 1) {
1553          emit_vop3a_instruction(ctx, instr, aco_opcode::v_min3_i32, dst);
1554       } else {
1555          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1556          nir_print_instr(&instr->instr, stderr);
1557          fprintf(stderr, "\n");
1558       }
1559       break;
1560    }
1561    case nir_op_imed3: {
1562       if (dst.size() == 1) {
1563          emit_vop3a_instruction(ctx, instr, aco_opcode::v_med3_i32, dst);
1564       } else {
1565          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1566          nir_print_instr(&instr->instr, stderr);
1567          fprintf(stderr, "\n");
1568       }
1569       break;
1570    }
1571    case nir_op_cube_face_coord: {
1572       Temp in = get_alu_src(ctx, instr->src[0], 3);
1573       Temp src[3] = { emit_extract_vector(ctx, in, 0, v1),
1574                       emit_extract_vector(ctx, in, 1, v1),
1575                       emit_extract_vector(ctx, in, 2, v1) };
1576       Temp ma = bld.vop3(aco_opcode::v_cubema_f32, bld.def(v1), src[0], src[1], src[2]);
1577       ma = bld.vop1(aco_opcode::v_rcp_f32, bld.def(v1), ma);
1578       Temp sc = bld.vop3(aco_opcode::v_cubesc_f32, bld.def(v1), src[0], src[1], src[2]);
1579       Temp tc = bld.vop3(aco_opcode::v_cubetc_f32, bld.def(v1), src[0], src[1], src[2]);
1580       sc = bld.vop2(aco_opcode::v_madak_f32, bld.def(v1), sc, ma, Operand(0x3f000000u/*0.5*/));
1581       tc = bld.vop2(aco_opcode::v_madak_f32, bld.def(v1), tc, ma, Operand(0x3f000000u/*0.5*/));
1582       bld.pseudo(aco_opcode::p_create_vector, Definition(dst), sc, tc);
1583       break;
1584    }
1585    case nir_op_cube_face_index: {
1586       Temp in = get_alu_src(ctx, instr->src[0], 3);
1587       Temp src[3] = { emit_extract_vector(ctx, in, 0, v1),
1588                       emit_extract_vector(ctx, in, 1, v1),
1589                       emit_extract_vector(ctx, in, 2, v1) };
1590       bld.vop3(aco_opcode::v_cubeid_f32, Definition(dst), src[0], src[1], src[2]);
1591       break;
1592    }
1593    case nir_op_bcsel: {
1594       emit_bcsel(ctx, instr, dst);
1595       break;
1596    }
1597    case nir_op_frsq: {
1598       if (dst.size() == 1) {
1599          emit_rsq(ctx, bld, Definition(dst), get_alu_src(ctx, instr->src[0]));
1600       } else if (dst.size() == 2) {
1601          emit_vop1_instruction(ctx, instr, aco_opcode::v_rsq_f64, dst);
1602       } else {
1603          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1604          nir_print_instr(&instr->instr, stderr);
1605          fprintf(stderr, "\n");
1606       }
1607       break;
1608    }
1609    case nir_op_fneg: {
1610       Temp src = get_alu_src(ctx, instr->src[0]);
1611       if (dst.size() == 1) {
1612          if (ctx->block->fp_mode.must_flush_denorms32)
1613             src = bld.vop2(aco_opcode::v_mul_f32, bld.def(v1), Operand(0x3f800000u), as_vgpr(ctx, src));
1614          bld.vop2(aco_opcode::v_xor_b32, Definition(dst), Operand(0x80000000u), as_vgpr(ctx, src));
1615       } else if (dst.size() == 2) {
1616          if (ctx->block->fp_mode.must_flush_denorms16_64)
1617             src = bld.vop3(aco_opcode::v_mul_f64, bld.def(v2), Operand(0x3FF0000000000000lu), as_vgpr(ctx, src));
1618          Temp upper = bld.tmp(v1), lower = bld.tmp(v1);
1619          bld.pseudo(aco_opcode::p_split_vector, Definition(lower), Definition(upper), src);
1620          upper = bld.vop2(aco_opcode::v_xor_b32, bld.def(v1), Operand(0x80000000u), upper);
1621          bld.pseudo(aco_opcode::p_create_vector, Definition(dst), lower, upper);
1622       } else {
1623          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1624          nir_print_instr(&instr->instr, stderr);
1625          fprintf(stderr, "\n");
1626       }
1627       break;
1628    }
1629    case nir_op_fabs: {
1630       Temp src = get_alu_src(ctx, instr->src[0]);
1631       if (dst.size() == 1) {
1632          if (ctx->block->fp_mode.must_flush_denorms32)
1633             src = bld.vop2(aco_opcode::v_mul_f32, bld.def(v1), Operand(0x3f800000u), as_vgpr(ctx, src));
1634          bld.vop2(aco_opcode::v_and_b32, Definition(dst), Operand(0x7FFFFFFFu), as_vgpr(ctx, src));
1635       } else if (dst.size() == 2) {
1636          if (ctx->block->fp_mode.must_flush_denorms16_64)
1637             src = bld.vop3(aco_opcode::v_mul_f64, bld.def(v2), Operand(0x3FF0000000000000lu), as_vgpr(ctx, src));
1638          Temp upper = bld.tmp(v1), lower = bld.tmp(v1);
1639          bld.pseudo(aco_opcode::p_split_vector, Definition(lower), Definition(upper), src);
1640          upper = bld.vop2(aco_opcode::v_and_b32, bld.def(v1), Operand(0x7FFFFFFFu), upper);
1641          bld.pseudo(aco_opcode::p_create_vector, Definition(dst), lower, upper);
1642       } else {
1643          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1644          nir_print_instr(&instr->instr, stderr);
1645          fprintf(stderr, "\n");
1646       }
1647       break;
1648    }
1649    case nir_op_fsat: {
1650       Temp src = get_alu_src(ctx, instr->src[0]);
1651       if (dst.size() == 1) {
1652          bld.vop3(aco_opcode::v_med3_f32, Definition(dst), Operand(0u), Operand(0x3f800000u), src);
1653          /* apparently, it is not necessary to flush denorms if this instruction is used with these operands */
1654          // TODO: confirm that this holds under any circumstances
1655       } else if (dst.size() == 2) {
1656          Instruction* add = bld.vop3(aco_opcode::v_add_f64, Definition(dst), src, Operand(0u));
1657          VOP3A_instruction* vop3 = static_cast<VOP3A_instruction*>(add);
1658          vop3->clamp = true;
1659       } else {
1660          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1661          nir_print_instr(&instr->instr, stderr);
1662          fprintf(stderr, "\n");
1663       }
1664       break;
1665    }
1666    case nir_op_flog2: {
1667       if (dst.size() == 1) {
1668          emit_log2(ctx, bld, Definition(dst), get_alu_src(ctx, instr->src[0]));
1669       } else {
1670          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1671          nir_print_instr(&instr->instr, stderr);
1672          fprintf(stderr, "\n");
1673       }
1674       break;
1675    }
1676    case nir_op_frcp: {
1677       if (dst.size() == 1) {
1678          emit_rcp(ctx, bld, Definition(dst), get_alu_src(ctx, instr->src[0]));
1679       } else if (dst.size() == 2) {
1680          emit_vop1_instruction(ctx, instr, aco_opcode::v_rcp_f64, dst);
1681       } else {
1682          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1683          nir_print_instr(&instr->instr, stderr);
1684          fprintf(stderr, "\n");
1685       }
1686       break;
1687    }
1688    case nir_op_fexp2: {
1689       if (dst.size() == 1) {
1690          emit_vop1_instruction(ctx, instr, aco_opcode::v_exp_f32, dst);
1691       } else {
1692          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1693          nir_print_instr(&instr->instr, stderr);
1694          fprintf(stderr, "\n");
1695       }
1696       break;
1697    }
1698    case nir_op_fsqrt: {
1699       if (dst.size() == 1) {
1700          emit_sqrt(ctx, bld, Definition(dst), get_alu_src(ctx, instr->src[0]));
1701       } else if (dst.size() == 2) {
1702          emit_vop1_instruction(ctx, instr, aco_opcode::v_sqrt_f64, dst);
1703       } else {
1704          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1705          nir_print_instr(&instr->instr, stderr);
1706          fprintf(stderr, "\n");
1707       }
1708       break;
1709    }
1710    case nir_op_ffract: {
1711       if (dst.size() == 1) {
1712          emit_vop1_instruction(ctx, instr, aco_opcode::v_fract_f32, dst);
1713       } else if (dst.size() == 2) {
1714          emit_vop1_instruction(ctx, instr, aco_opcode::v_fract_f64, dst);
1715       } else {
1716          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1717          nir_print_instr(&instr->instr, stderr);
1718          fprintf(stderr, "\n");
1719       }
1720       break;
1721    }
1722    case nir_op_ffloor: {
1723       if (dst.size() == 1) {
1724          emit_vop1_instruction(ctx, instr, aco_opcode::v_floor_f32, dst);
1725       } else if (dst.size() == 2) {
1726          emit_floor_f64(ctx, bld, Definition(dst), get_alu_src(ctx, instr->src[0]));
1727       } else {
1728          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1729          nir_print_instr(&instr->instr, stderr);
1730          fprintf(stderr, "\n");
1731       }
1732       break;
1733    }
1734    case nir_op_fceil: {
1735       if (dst.size() == 1) {
1736          emit_vop1_instruction(ctx, instr, aco_opcode::v_ceil_f32, dst);
1737       } else if (dst.size() == 2) {
1738          if (ctx->options->chip_class >= GFX7) {
1739             emit_vop1_instruction(ctx, instr, aco_opcode::v_ceil_f64, dst);
1740          } else {
1741             /* GFX6 doesn't support V_CEIL_F64, lower it. */
1742             Temp src0 = get_alu_src(ctx, instr->src[0]);
1743
1744             /* trunc = trunc(src0)
1745              * if (src0 > 0.0 && src0 != trunc)
1746              *    trunc += 1.0
1747              */
1748             Temp trunc = emit_trunc_f64(ctx, bld, bld.def(v2), src0);
1749             Temp tmp0 = bld.vopc_e64(aco_opcode::v_cmp_gt_f64, bld.def(bld.lm), src0, Operand(0u));
1750             Temp tmp1 = bld.vopc(aco_opcode::v_cmp_lg_f64, bld.hint_vcc(bld.def(bld.lm)), src0, trunc);
1751             Temp cond = bld.sop2(aco_opcode::s_and_b64, bld.hint_vcc(bld.def(s2)), bld.def(s1, scc), tmp0, tmp1);
1752             Temp add = bld.vop2(aco_opcode::v_cndmask_b32, bld.def(v1), bld.copy(bld.def(v1), Operand(0u)), bld.copy(bld.def(v1), Operand(0x3ff00000u)), cond);
1753             add = bld.pseudo(aco_opcode::p_create_vector, bld.def(v2), bld.copy(bld.def(v1), Operand(0u)), add);
1754             bld.vop3(aco_opcode::v_add_f64, Definition(dst), trunc, add);
1755          }
1756       } else {
1757          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1758          nir_print_instr(&instr->instr, stderr);
1759          fprintf(stderr, "\n");
1760       }
1761       break;
1762    }
1763    case nir_op_ftrunc: {
1764       if (dst.size() == 1) {
1765          emit_vop1_instruction(ctx, instr, aco_opcode::v_trunc_f32, dst);
1766       } else if (dst.size() == 2) {
1767          emit_trunc_f64(ctx, bld, Definition(dst), get_alu_src(ctx, instr->src[0]));
1768       } else {
1769          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1770          nir_print_instr(&instr->instr, stderr);
1771          fprintf(stderr, "\n");
1772       }
1773       break;
1774    }
1775    case nir_op_fround_even: {
1776       if (dst.size() == 1) {
1777          emit_vop1_instruction(ctx, instr, aco_opcode::v_rndne_f32, dst);
1778       } else if (dst.size() == 2) {
1779          if (ctx->options->chip_class >= GFX7) {
1780             emit_vop1_instruction(ctx, instr, aco_opcode::v_rndne_f64, dst);
1781          } else {
1782             /* GFX6 doesn't support V_RNDNE_F64, lower it. */
1783             Temp src0 = get_alu_src(ctx, instr->src[0]);
1784
1785             Temp src0_lo = bld.tmp(v1), src0_hi = bld.tmp(v1);
1786             bld.pseudo(aco_opcode::p_split_vector, Definition(src0_lo), Definition(src0_hi), src0);
1787
1788             Temp bitmask = bld.sop1(aco_opcode::s_brev_b32, bld.def(s1), bld.copy(bld.def(s1), Operand(-2u)));
1789             Temp bfi = bld.vop3(aco_opcode::v_bfi_b32, bld.def(v1), bitmask, bld.copy(bld.def(v1), Operand(0x43300000u)), as_vgpr(ctx, src0_hi));
1790             Temp tmp = bld.vop3(aco_opcode::v_add_f64, bld.def(v2), src0, bld.pseudo(aco_opcode::p_create_vector, bld.def(v2), Operand(0u), bfi));
1791             Instruction *sub = bld.vop3(aco_opcode::v_add_f64, bld.def(v2), tmp, bld.pseudo(aco_opcode::p_create_vector, bld.def(v2), Operand(0u), bfi));
1792             static_cast<VOP3A_instruction*>(sub)->neg[1] = true;
1793             tmp = sub->definitions[0].getTemp();
1794
1795             Temp v = bld.pseudo(aco_opcode::p_create_vector, bld.def(v2), Operand(-1u), Operand(0x432fffffu));
1796             Instruction* vop3 = bld.vopc_e64(aco_opcode::v_cmp_gt_f64, bld.hint_vcc(bld.def(bld.lm)), src0, v);
1797             static_cast<VOP3A_instruction*>(vop3)->abs[0] = true;
1798             Temp cond = vop3->definitions[0].getTemp();
1799
1800             Temp tmp_lo = bld.tmp(v1), tmp_hi = bld.tmp(v1);
1801             bld.pseudo(aco_opcode::p_split_vector, Definition(tmp_lo), Definition(tmp_hi), tmp);
1802             Temp dst0 = bld.vop2_e64(aco_opcode::v_cndmask_b32, bld.def(v1), tmp_lo, as_vgpr(ctx, src0_lo), cond);
1803             Temp dst1 = bld.vop2_e64(aco_opcode::v_cndmask_b32, bld.def(v1), tmp_hi, as_vgpr(ctx, src0_hi), cond);
1804
1805             bld.pseudo(aco_opcode::p_create_vector, Definition(dst), dst0, dst1);
1806          }
1807       } else {
1808          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1809          nir_print_instr(&instr->instr, stderr);
1810          fprintf(stderr, "\n");
1811       }
1812       break;
1813    }
1814    case nir_op_fsin:
1815    case nir_op_fcos: {
1816       Temp src = get_alu_src(ctx, instr->src[0]);
1817       aco_ptr<Instruction> norm;
1818       if (dst.size() == 1) {
1819          Temp half_pi = bld.copy(bld.def(s1), Operand(0x3e22f983u));
1820          Temp tmp = bld.vop2(aco_opcode::v_mul_f32, bld.def(v1), half_pi, as_vgpr(ctx, src));
1821
1822          /* before GFX9, v_sin_f32 and v_cos_f32 had a valid input domain of [-256, +256] */
1823          if (ctx->options->chip_class < GFX9)
1824             tmp = bld.vop1(aco_opcode::v_fract_f32, bld.def(v1), tmp);
1825
1826          aco_opcode opcode = instr->op == nir_op_fsin ? aco_opcode::v_sin_f32 : aco_opcode::v_cos_f32;
1827          bld.vop1(opcode, Definition(dst), tmp);
1828       } else {
1829          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1830          nir_print_instr(&instr->instr, stderr);
1831          fprintf(stderr, "\n");
1832       }
1833       break;
1834    }
1835    case nir_op_ldexp: {
1836       if (dst.size() == 1) {
1837          bld.vop3(aco_opcode::v_ldexp_f32, Definition(dst),
1838                   as_vgpr(ctx, get_alu_src(ctx, instr->src[0])),
1839                   get_alu_src(ctx, instr->src[1]));
1840       } else if (dst.size() == 2) {
1841          bld.vop3(aco_opcode::v_ldexp_f64, Definition(dst),
1842                   as_vgpr(ctx, get_alu_src(ctx, instr->src[0])),
1843                   get_alu_src(ctx, instr->src[1]));
1844       } else {
1845          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1846          nir_print_instr(&instr->instr, stderr);
1847          fprintf(stderr, "\n");
1848       }
1849       break;
1850    }
1851    case nir_op_frexp_sig: {
1852       if (dst.size() == 1) {
1853          bld.vop1(aco_opcode::v_frexp_mant_f32, Definition(dst),
1854                   get_alu_src(ctx, instr->src[0]));
1855       } else if (dst.size() == 2) {
1856          bld.vop1(aco_opcode::v_frexp_mant_f64, Definition(dst),
1857                   get_alu_src(ctx, instr->src[0]));
1858       } else {
1859          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1860          nir_print_instr(&instr->instr, stderr);
1861          fprintf(stderr, "\n");
1862       }
1863       break;
1864    }
1865    case nir_op_frexp_exp: {
1866       if (instr->src[0].src.ssa->bit_size == 32) {
1867          bld.vop1(aco_opcode::v_frexp_exp_i32_f32, Definition(dst),
1868                   get_alu_src(ctx, instr->src[0]));
1869       } else if (instr->src[0].src.ssa->bit_size == 64) {
1870          bld.vop1(aco_opcode::v_frexp_exp_i32_f64, Definition(dst),
1871                   get_alu_src(ctx, instr->src[0]));
1872       } else {
1873          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1874          nir_print_instr(&instr->instr, stderr);
1875          fprintf(stderr, "\n");
1876       }
1877       break;
1878    }
1879    case nir_op_fsign: {
1880       Temp src = as_vgpr(ctx, get_alu_src(ctx, instr->src[0]));
1881       if (dst.size() == 1) {
1882          Temp cond = bld.vopc(aco_opcode::v_cmp_nlt_f32, bld.hint_vcc(bld.def(bld.lm)), Operand(0u), src);
1883          src = bld.vop2(aco_opcode::v_cndmask_b32, bld.def(v1), Operand(0x3f800000u), src, cond);
1884          cond = bld.vopc(aco_opcode::v_cmp_le_f32, bld.hint_vcc(bld.def(bld.lm)), Operand(0u), src);
1885          bld.vop2(aco_opcode::v_cndmask_b32, Definition(dst), Operand(0xbf800000u), src, cond);
1886       } else if (dst.size() == 2) {
1887          Temp cond = bld.vopc(aco_opcode::v_cmp_nlt_f64, bld.hint_vcc(bld.def(bld.lm)), Operand(0u), src);
1888          Temp tmp = bld.vop1(aco_opcode::v_mov_b32, bld.def(v1), Operand(0x3FF00000u));
1889          Temp upper = bld.vop2_e64(aco_opcode::v_cndmask_b32, bld.def(v1), tmp, emit_extract_vector(ctx, src, 1, v1), cond);
1890
1891          cond = bld.vopc(aco_opcode::v_cmp_le_f64, bld.hint_vcc(bld.def(bld.lm)), Operand(0u), src);
1892          tmp = bld.vop1(aco_opcode::v_mov_b32, bld.def(v1), Operand(0xBFF00000u));
1893          upper = bld.vop2(aco_opcode::v_cndmask_b32, bld.def(v1), tmp, upper, cond);
1894
1895          bld.pseudo(aco_opcode::p_create_vector, Definition(dst), Operand(0u), upper);
1896       } else {
1897          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1898          nir_print_instr(&instr->instr, stderr);
1899          fprintf(stderr, "\n");
1900       }
1901       break;
1902    }
1903    case nir_op_f2f32: {
1904       if (instr->src[0].src.ssa->bit_size == 64) {
1905          emit_vop1_instruction(ctx, instr, aco_opcode::v_cvt_f32_f64, dst);
1906       } else {
1907          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1908          nir_print_instr(&instr->instr, stderr);
1909          fprintf(stderr, "\n");
1910       }
1911       break;
1912    }
1913    case nir_op_f2f64: {
1914       if (instr->src[0].src.ssa->bit_size == 32) {
1915          emit_vop1_instruction(ctx, instr, aco_opcode::v_cvt_f64_f32, dst);
1916       } else {
1917          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1918          nir_print_instr(&instr->instr, stderr);
1919          fprintf(stderr, "\n");
1920       }
1921       break;
1922    }
1923    case nir_op_i2f32: {
1924       assert(dst.size() == 1);
1925       emit_vop1_instruction(ctx, instr, aco_opcode::v_cvt_f32_i32, dst);
1926       break;
1927    }
1928    case nir_op_i2f64: {
1929       if (instr->src[0].src.ssa->bit_size == 32) {
1930          emit_vop1_instruction(ctx, instr, aco_opcode::v_cvt_f64_i32, dst);
1931       } else if (instr->src[0].src.ssa->bit_size == 64) {
1932          Temp src = get_alu_src(ctx, instr->src[0]);
1933          RegClass rc = RegClass(src.type(), 1);
1934          Temp lower = bld.tmp(rc), upper = bld.tmp(rc);
1935          bld.pseudo(aco_opcode::p_split_vector, Definition(lower), Definition(upper), src);
1936          lower = bld.vop1(aco_opcode::v_cvt_f64_u32, bld.def(v2), lower);
1937          upper = bld.vop1(aco_opcode::v_cvt_f64_i32, bld.def(v2), upper);
1938          upper = bld.vop3(aco_opcode::v_ldexp_f64, bld.def(v2), upper, Operand(32u));
1939          bld.vop3(aco_opcode::v_add_f64, Definition(dst), lower, upper);
1940
1941       } else {
1942          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1943          nir_print_instr(&instr->instr, stderr);
1944          fprintf(stderr, "\n");
1945       }
1946       break;
1947    }
1948    case nir_op_u2f32: {
1949       assert(dst.size() == 1);
1950       emit_vop1_instruction(ctx, instr, aco_opcode::v_cvt_f32_u32, dst);
1951       break;
1952    }
1953    case nir_op_u2f64: {
1954       if (instr->src[0].src.ssa->bit_size == 32) {
1955          emit_vop1_instruction(ctx, instr, aco_opcode::v_cvt_f64_u32, dst);
1956       } else if (instr->src[0].src.ssa->bit_size == 64) {
1957          Temp src = get_alu_src(ctx, instr->src[0]);
1958          RegClass rc = RegClass(src.type(), 1);
1959          Temp lower = bld.tmp(rc), upper = bld.tmp(rc);
1960          bld.pseudo(aco_opcode::p_split_vector, Definition(lower), Definition(upper), src);
1961          lower = bld.vop1(aco_opcode::v_cvt_f64_u32, bld.def(v2), lower);
1962          upper = bld.vop1(aco_opcode::v_cvt_f64_u32, bld.def(v2), upper);
1963          upper = bld.vop3(aco_opcode::v_ldexp_f64, bld.def(v2), upper, Operand(32u));
1964          bld.vop3(aco_opcode::v_add_f64, Definition(dst), lower, upper);
1965       } else {
1966          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1967          nir_print_instr(&instr->instr, stderr);
1968          fprintf(stderr, "\n");
1969       }
1970       break;
1971    }
1972    case nir_op_f2i32: {
1973       Temp src = get_alu_src(ctx, instr->src[0]);
1974       if (instr->src[0].src.ssa->bit_size == 32) {
1975          if (dst.type() == RegType::vgpr)
1976             bld.vop1(aco_opcode::v_cvt_i32_f32, Definition(dst), src);
1977          else
1978             bld.pseudo(aco_opcode::p_as_uniform, Definition(dst),
1979                        bld.vop1(aco_opcode::v_cvt_i32_f32, bld.def(v1), src));
1980
1981       } else if (instr->src[0].src.ssa->bit_size == 64) {
1982          if (dst.type() == RegType::vgpr)
1983             bld.vop1(aco_opcode::v_cvt_i32_f64, Definition(dst), src);
1984          else
1985             bld.pseudo(aco_opcode::p_as_uniform, Definition(dst),
1986                        bld.vop1(aco_opcode::v_cvt_i32_f64, bld.def(v1), src));
1987
1988       } else {
1989          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1990          nir_print_instr(&instr->instr, stderr);
1991          fprintf(stderr, "\n");
1992       }
1993       break;
1994    }
1995    case nir_op_f2u32: {
1996       Temp src = get_alu_src(ctx, instr->src[0]);
1997       if (instr->src[0].src.ssa->bit_size == 32) {
1998          if (dst.type() == RegType::vgpr)
1999             bld.vop1(aco_opcode::v_cvt_u32_f32, Definition(dst), src);
2000          else
2001             bld.pseudo(aco_opcode::p_as_uniform, Definition(dst),
2002                        bld.vop1(aco_opcode::v_cvt_u32_f32, bld.def(v1), src));
2003
2004       } else if (instr->src[0].src.ssa->bit_size == 64) {
2005          if (dst.type() == RegType::vgpr)
2006             bld.vop1(aco_opcode::v_cvt_u32_f64, Definition(dst), src);
2007          else
2008             bld.pseudo(aco_opcode::p_as_uniform, Definition(dst),
2009                        bld.vop1(aco_opcode::v_cvt_u32_f64, bld.def(v1), src));
2010
2011       } else {
2012          fprintf(stderr, "Unimplemented NIR instr bit size: ");
2013          nir_print_instr(&instr->instr, stderr);
2014          fprintf(stderr, "\n");
2015       }
2016       break;
2017    }
2018    case nir_op_f2i64: {
2019       Temp src = get_alu_src(ctx, instr->src[0]);
2020       if (instr->src[0].src.ssa->bit_size == 32 && dst.type() == RegType::vgpr) {
2021          Temp exponent = bld.vop1(aco_opcode::v_frexp_exp_i32_f32, bld.def(v1), src);
2022          exponent = bld.vop3(aco_opcode::v_med3_i32, bld.def(v1), Operand(0x0u), exponent, Operand(64u));
2023          Temp mantissa = bld.vop2(aco_opcode::v_and_b32, bld.def(v1), Operand(0x7fffffu), src);
2024          Temp sign = bld.vop2(aco_opcode::v_ashrrev_i32, bld.def(v1), Operand(31u), src);
2025          mantissa = bld.vop2(aco_opcode::v_or_b32, bld.def(v1), Operand(0x800000u), mantissa);
2026          mantissa = bld.vop2(aco_opcode::v_lshlrev_b32, bld.def(v1), Operand(7u), mantissa);
2027          mantissa = bld.pseudo(aco_opcode::p_create_vector, bld.def(v2), Operand(0u), mantissa);
2028          Temp new_exponent = bld.tmp(v1);
2029          Temp borrow = bld.vsub32(Definition(new_exponent), Operand(63u), exponent, true).def(1).getTemp();
2030          if (ctx->program->chip_class >= GFX8)
2031             mantissa = bld.vop3(aco_opcode::v_lshrrev_b64, bld.def(v2), new_exponent, mantissa);
2032          else
2033             mantissa = bld.vop3(aco_opcode::v_lshr_b64, bld.def(v2), mantissa, new_exponent);
2034          Temp saturate = bld.vop1(aco_opcode::v_bfrev_b32, bld.def(v1), Operand(0xfffffffeu));
2035          Temp lower = bld.tmp(v1), upper = bld.tmp(v1);
2036          bld.pseudo(aco_opcode::p_split_vector, Definition(lower), Definition(upper), mantissa);
2037          lower = bld.vop2_e64(aco_opcode::v_cndmask_b32, bld.def(v1), lower, Operand(0xffffffffu), borrow);
2038          upper = bld.vop2(aco_opcode::v_cndmask_b32, bld.def(v1), upper, saturate, borrow);
2039          lower = bld.vop2(aco_opcode::v_xor_b32, bld.def(v1), sign, lower);
2040          upper = bld.vop2(aco_opcode::v_xor_b32, bld.def(v1), sign, upper);
2041          Temp new_lower = bld.tmp(v1);
2042          borrow = bld.vsub32(Definition(new_lower), lower, sign, true).def(1).getTemp();
2043          Temp new_upper = bld.vsub32(bld.def(v1), upper, sign, false, borrow);
2044          bld.pseudo(aco_opcode::p_create_vector, Definition(dst), new_lower, new_upper);
2045
2046       } else if (instr->src[0].src.ssa->bit_size == 32 && dst.type() == RegType::sgpr) {
2047          if (src.type() == RegType::vgpr)
2048             src = bld.as_uniform(src);
2049          Temp exponent = bld.sop2(aco_opcode::s_bfe_u32, bld.def(s1), bld.def(s1, scc), src, Operand(0x80017u));
2050          exponent = bld.sop2(aco_opcode::s_sub_u32, bld.def(s1), bld.def(s1, scc), exponent, Operand(126u));
2051          exponent = bld.sop2(aco_opcode::s_max_u32, bld.def(s1), bld.def(s1, scc), Operand(0u), exponent);
2052          exponent = bld.sop2(aco_opcode::s_min_u32, bld.def(s1), bld.def(s1, scc), Operand(64u), exponent);
2053          Temp mantissa = bld.sop2(aco_opcode::s_and_b32, bld.def(s1), bld.def(s1, scc), Operand(0x7fffffu), src);
2054          Temp sign = bld.sop2(aco_opcode::s_ashr_i32, bld.def(s1), bld.def(s1, scc), src, Operand(31u));
2055          mantissa = bld.sop2(aco_opcode::s_or_b32, bld.def(s1), bld.def(s1, scc), Operand(0x800000u), mantissa);
2056          mantissa = bld.sop2(aco_opcode::s_lshl_b32, bld.def(s1), bld.def(s1, scc), mantissa, Operand(7u));
2057          mantissa = bld.pseudo(aco_opcode::p_create_vector, bld.def(s2), Operand(0u), mantissa);
2058          exponent = bld.sop2(aco_opcode::s_sub_u32, bld.def(s1), bld.def(s1, scc), Operand(63u), exponent);
2059          mantissa = bld.sop2(aco_opcode::s_lshr_b64, bld.def(s2), bld.def(s1, scc), mantissa, exponent);
2060          Temp cond = bld.sopc(aco_opcode::s_cmp_eq_u32, bld.def(s1, scc), exponent, Operand(0xffffffffu)); // exp >= 64
2061          Temp saturate = bld.sop1(aco_opcode::s_brev_b64, bld.def(s2), Operand(0xfffffffeu));
2062          mantissa = bld.sop2(aco_opcode::s_cselect_b64, bld.def(s2), saturate, mantissa, cond);
2063          Temp lower = bld.tmp(s1), upper = bld.tmp(s1);
2064          bld.pseudo(aco_opcode::p_split_vector, Definition(lower), Definition(upper), mantissa);
2065          lower = bld.sop2(aco_opcode::s_xor_b32, bld.def(s1), bld.def(s1, scc), sign, lower);
2066          upper = bld.sop2(aco_opcode::s_xor_b32, bld.def(s1), bld.def(s1, scc), sign, upper);
2067          Temp borrow = bld.tmp(s1);
2068          lower = bld.sop2(aco_opcode::s_sub_u32, bld.def(s1), bld.scc(Definition(borrow)), lower, sign);
2069          upper = bld.sop2(aco_opcode::s_subb_u32, bld.def(s1), bld.def(s1, scc), upper, sign, borrow);
2070          bld.pseudo(aco_opcode::p_create_vector, Definition(dst), lower, upper);
2071
2072       } else if (instr->src[0].src.ssa->bit_size == 64) {
2073          Temp vec = bld.pseudo(aco_opcode::p_create_vector, bld.def(s2), Operand(0u), Operand(0x3df00000u));
2074          Temp trunc = emit_trunc_f64(ctx, bld, bld.def(v2), src);
2075          Temp mul = bld.vop3(aco_opcode::v_mul_f64, bld.def(v2), trunc, vec);
2076          vec = bld.pseudo(aco_opcode::p_create_vector, bld.def(s2), Operand(0u), Operand(0xc1f00000u));
2077          Temp floor = emit_floor_f64(ctx, bld, bld.def(v2), mul);
2078          Temp fma = bld.vop3(aco_opcode::v_fma_f64, bld.def(v2), floor, vec, trunc);
2079          Temp lower = bld.vop1(aco_opcode::v_cvt_u32_f64, bld.def(v1), fma);
2080          Temp upper = bld.vop1(aco_opcode::v_cvt_i32_f64, bld.def(v1), floor);
2081          if (dst.type() == RegType::sgpr) {
2082             lower = bld.as_uniform(lower);
2083             upper = bld.as_uniform(upper);
2084          }
2085          bld.pseudo(aco_opcode::p_create_vector, Definition(dst), lower, upper);
2086
2087       } else {
2088          fprintf(stderr, "Unimplemented NIR instr bit size: ");
2089          nir_print_instr(&instr->instr, stderr);
2090          fprintf(stderr, "\n");
2091       }
2092       break;
2093    }
2094    case nir_op_f2u64: {
2095       Temp src = get_alu_src(ctx, instr->src[0]);
2096       if (instr->src[0].src.ssa->bit_size == 32 && dst.type() == RegType::vgpr) {
2097          Temp exponent = bld.vop1(aco_opcode::v_frexp_exp_i32_f32, bld.def(v1), src);
2098          Temp exponent_in_range = bld.vopc(aco_opcode::v_cmp_ge_i32, bld.hint_vcc(bld.def(bld.lm)), Operand(64u), exponent);
2099          exponent = bld.vop2(aco_opcode::v_max_i32, bld.def(v1), Operand(0x0u), exponent);
2100          Temp mantissa = bld.vop2(aco_opcode::v_and_b32, bld.def(v1), Operand(0x7fffffu), src);
2101          mantissa = bld.vop2(aco_opcode::v_or_b32, bld.def(v1), Operand(0x800000u), mantissa);
2102          Temp exponent_small = bld.vsub32(bld.def(v1), Operand(24u), exponent);
2103          Temp small = bld.vop2(aco_opcode::v_lshrrev_b32, bld.def(v1), exponent_small, mantissa);
2104          mantissa = bld.pseudo(aco_opcode::p_create_vector, bld.def(v2), Operand(0u), mantissa);
2105          Temp new_exponent = bld.tmp(v1);
2106          Temp cond_small = bld.vsub32(Definition(new_exponent), exponent, Operand(24u), true).def(1).getTemp();
2107          if (ctx->program->chip_class >= GFX8)
2108             mantissa = bld.vop3(aco_opcode::v_lshlrev_b64, bld.def(v2), new_exponent, mantissa);
2109          else
2110             mantissa = bld.vop3(aco_opcode::v_lshl_b64, bld.def(v2), mantissa, new_exponent);
2111          Temp lower = bld.tmp(v1), upper = bld.tmp(v1);
2112          bld.pseudo(aco_opcode::p_split_vector, Definition(lower), Definition(upper), mantissa);
2113          lower = bld.vop2(aco_opcode::v_cndmask_b32, bld.def(v1), lower, small, cond_small);
2114          upper = bld.vop2_e64(aco_opcode::v_cndmask_b32, bld.def(v1), upper, Operand(0u), cond_small);
2115          lower = bld.vop2(aco_opcode::v_cndmask_b32, bld.def(v1), Operand(0xffffffffu), lower, exponent_in_range);
2116          upper = bld.vop2(aco_opcode::v_cndmask_b32, bld.def(v1), Operand(0xffffffffu), upper, exponent_in_range);
2117          bld.pseudo(aco_opcode::p_create_vector, Definition(dst), lower, upper);
2118
2119       } else if (instr->src[0].src.ssa->bit_size == 32 && dst.type() == RegType::sgpr) {
2120          if (src.type() == RegType::vgpr)
2121             src = bld.as_uniform(src);
2122          Temp exponent = bld.sop2(aco_opcode::s_bfe_u32, bld.def(s1), bld.def(s1, scc), src, Operand(0x80017u));
2123          exponent = bld.sop2(aco_opcode::s_sub_u32, bld.def(s1), bld.def(s1, scc), exponent, Operand(126u));
2124          exponent = bld.sop2(aco_opcode::s_max_u32, bld.def(s1), bld.def(s1, scc), Operand(0u), exponent);
2125          Temp mantissa = bld.sop2(aco_opcode::s_and_b32, bld.def(s1), bld.def(s1, scc), Operand(0x7fffffu), src);
2126          mantissa = bld.sop2(aco_opcode::s_or_b32, bld.def(s1), bld.def(s1, scc), Operand(0x800000u), mantissa);
2127          Temp exponent_small = bld.sop2(aco_opcode::s_sub_u32, bld.def(s1), bld.def(s1, scc), Operand(24u), exponent);
2128          Temp small = bld.sop2(aco_opcode::s_lshr_b32, bld.def(s1), bld.def(s1, scc), mantissa, exponent_small);
2129          mantissa = bld.pseudo(aco_opcode::p_create_vector, bld.def(s2), Operand(0u), mantissa);
2130          Temp exponent_large = bld.sop2(aco_opcode::s_sub_u32, bld.def(s1), bld.def(s1, scc), exponent, Operand(24u));
2131          mantissa = bld.sop2(aco_opcode::s_lshl_b64, bld.def(s2), bld.def(s1, scc), mantissa, exponent_large);
2132          Temp cond = bld.sopc(aco_opcode::s_cmp_ge_i32, bld.def(s1, scc), Operand(64u), exponent);
2133          mantissa = bld.sop2(aco_opcode::s_cselect_b64, bld.def(s2), mantissa, Operand(0xffffffffu), cond);
2134          Temp lower = bld.tmp(s1), upper = bld.tmp(s1);
2135          bld.pseudo(aco_opcode::p_split_vector, Definition(lower), Definition(upper), mantissa);
2136          Temp cond_small = bld.sopc(aco_opcode::s_cmp_le_i32, bld.def(s1, scc), exponent, Operand(24u));
2137          lower = bld.sop2(aco_opcode::s_cselect_b32, bld.def(s1), small, lower, cond_small);
2138          upper = bld.sop2(aco_opcode::s_cselect_b32, bld.def(s1), Operand(0u), upper, cond_small);
2139          bld.pseudo(aco_opcode::p_create_vector, Definition(dst), lower, upper);
2140
2141       } else if (instr->src[0].src.ssa->bit_size == 64) {
2142          Temp vec = bld.pseudo(aco_opcode::p_create_vector, bld.def(s2), Operand(0u), Operand(0x3df00000u));
2143          Temp trunc = emit_trunc_f64(ctx, bld, bld.def(v2), src);
2144          Temp mul = bld.vop3(aco_opcode::v_mul_f64, bld.def(v2), trunc, vec);
2145          vec = bld.pseudo(aco_opcode::p_create_vector, bld.def(s2), Operand(0u), Operand(0xc1f00000u));
2146          Temp floor = emit_floor_f64(ctx, bld, bld.def(v2), mul);
2147          Temp fma = bld.vop3(aco_opcode::v_fma_f64, bld.def(v2), floor, vec, trunc);
2148          Temp lower = bld.vop1(aco_opcode::v_cvt_u32_f64, bld.def(v1), fma);
2149          Temp upper = bld.vop1(aco_opcode::v_cvt_u32_f64, bld.def(v1), floor);
2150          if (dst.type() == RegType::sgpr) {
2151             lower = bld.as_uniform(lower);
2152             upper = bld.as_uniform(upper);
2153          }
2154          bld.pseudo(aco_opcode::p_create_vector, Definition(dst), lower, upper);
2155
2156       } else {
2157          fprintf(stderr, "Unimplemented NIR instr bit size: ");
2158          nir_print_instr(&instr->instr, stderr);
2159          fprintf(stderr, "\n");
2160       }
2161       break;
2162    }
2163    case nir_op_b2f32: {
2164       Temp src = get_alu_src(ctx, instr->src[0]);
2165       assert(src.regClass() == bld.lm);
2166
2167       if (dst.regClass() == s1) {
2168          src = bool_to_scalar_condition(ctx, src);
2169          bld.sop2(aco_opcode::s_mul_i32, Definition(dst), Operand(0x3f800000u), src);
2170       } else if (dst.regClass() == v1) {
2171          bld.vop2_e64(aco_opcode::v_cndmask_b32, Definition(dst), Operand(0u), Operand(0x3f800000u), src);
2172       } else {
2173          unreachable("Wrong destination register class for nir_op_b2f32.");
2174       }
2175       break;
2176    }
2177    case nir_op_b2f64: {
2178       Temp src = get_alu_src(ctx, instr->src[0]);
2179       assert(src.regClass() == bld.lm);
2180
2181       if (dst.regClass() == s2) {
2182          src = bool_to_scalar_condition(ctx, src);
2183          bld.sop2(aco_opcode::s_cselect_b64, Definition(dst), Operand(0x3f800000u), Operand(0u), bld.scc(src));
2184       } else if (dst.regClass() == v2) {
2185          Temp one = bld.vop1(aco_opcode::v_mov_b32, bld.def(v2), Operand(0x3FF00000u));
2186          Temp upper = bld.vop2_e64(aco_opcode::v_cndmask_b32, bld.def(v1), Operand(0u), one, src);
2187          bld.pseudo(aco_opcode::p_create_vector, Definition(dst), Operand(0u), upper);
2188       } else {
2189          unreachable("Wrong destination register class for nir_op_b2f64.");
2190       }
2191       break;
2192    }
2193    case nir_op_i2i32: {
2194       Temp src = get_alu_src(ctx, instr->src[0]);
2195       if (instr->src[0].src.ssa->bit_size == 64) {
2196          /* we can actually just say dst = src, as it would map the lower register */
2197          emit_extract_vector(ctx, src, 0, dst);
2198       } else {
2199          fprintf(stderr, "Unimplemented NIR instr bit size: ");
2200          nir_print_instr(&instr->instr, stderr);
2201          fprintf(stderr, "\n");
2202       }
2203       break;
2204    }
2205    case nir_op_u2u32: {
2206       Temp src = get_alu_src(ctx, instr->src[0]);
2207       if (instr->src[0].src.ssa->bit_size == 16) {
2208          if (dst.regClass() == s1) {
2209             bld.sop2(aco_opcode::s_and_b32, Definition(dst), bld.def(s1, scc), Operand(0xFFFFu), src);
2210          } else {
2211             // TODO: do better with SDWA
2212             bld.vop2(aco_opcode::v_and_b32, Definition(dst), Operand(0xFFFFu), src);
2213          }
2214       } else if (instr->src[0].src.ssa->bit_size == 64) {
2215          /* we can actually just say dst = src, as it would map the lower register */
2216          emit_extract_vector(ctx, src, 0, dst);
2217       } else {
2218          fprintf(stderr, "Unimplemented NIR instr bit size: ");
2219          nir_print_instr(&instr->instr, stderr);
2220          fprintf(stderr, "\n");
2221       }
2222       break;
2223    }
2224    case nir_op_i2i64: {
2225       Temp src = get_alu_src(ctx, instr->src[0]);
2226       if (src.regClass() == s1) {
2227          Temp high = bld.sop2(aco_opcode::s_ashr_i32, bld.def(s1), bld.def(s1, scc), src, Operand(31u));
2228          bld.pseudo(aco_opcode::p_create_vector, Definition(dst), src, high);
2229       } else if (src.regClass() == v1) {
2230          Temp high = bld.vop2(aco_opcode::v_ashrrev_i32, bld.def(v1), Operand(31u), src);
2231          bld.pseudo(aco_opcode::p_create_vector, Definition(dst), src, high);
2232       } else {
2233          fprintf(stderr, "Unimplemented NIR instr bit size: ");
2234          nir_print_instr(&instr->instr, stderr);
2235          fprintf(stderr, "\n");
2236       }
2237       break;
2238    }
2239    case nir_op_u2u64: {
2240       Temp src = get_alu_src(ctx, instr->src[0]);
2241       if (instr->src[0].src.ssa->bit_size == 32) {
2242          bld.pseudo(aco_opcode::p_create_vector, Definition(dst), src, Operand(0u));
2243       } else {
2244          fprintf(stderr, "Unimplemented NIR instr bit size: ");
2245          nir_print_instr(&instr->instr, stderr);
2246          fprintf(stderr, "\n");
2247       }
2248       break;
2249    }
2250    case nir_op_b2i32: {
2251       Temp src = get_alu_src(ctx, instr->src[0]);
2252       assert(src.regClass() == bld.lm);
2253
2254       if (dst.regClass() == s1) {
2255          // TODO: in a post-RA optimization, we can check if src is in VCC, and directly use VCCNZ
2256          bool_to_scalar_condition(ctx, src, dst);
2257       } else if (dst.regClass() == v1) {
2258          bld.vop2_e64(aco_opcode::v_cndmask_b32, Definition(dst), Operand(0u), Operand(1u), src);
2259       } else {
2260          unreachable("Invalid register class for b2i32");
2261       }
2262       break;
2263    }
2264    case nir_op_i2b1: {
2265       Temp src = get_alu_src(ctx, instr->src[0]);
2266       assert(dst.regClass() == bld.lm);
2267
2268       if (src.type() == RegType::vgpr) {
2269          assert(src.regClass() == v1 || src.regClass() == v2);
2270          assert(dst.regClass() == bld.lm);
2271          bld.vopc(src.size() == 2 ? aco_opcode::v_cmp_lg_u64 : aco_opcode::v_cmp_lg_u32,
2272                   Definition(dst), Operand(0u), src).def(0).setHint(vcc);
2273       } else {
2274          assert(src.regClass() == s1 || src.regClass() == s2);
2275          Temp tmp;
2276          if (src.regClass() == s2 && ctx->program->chip_class <= GFX7) {
2277             tmp = bld.sop2(aco_opcode::s_or_b64, bld.def(s2), bld.def(s1, scc), Operand(0u), src).def(1).getTemp();
2278          } else {
2279             tmp = bld.sopc(src.size() == 2 ? aco_opcode::s_cmp_lg_u64 : aco_opcode::s_cmp_lg_u32,
2280                            bld.scc(bld.def(s1)), Operand(0u), src);
2281          }
2282          bool_to_vector_condition(ctx, tmp, dst);
2283       }
2284       break;
2285    }
2286    case nir_op_pack_64_2x32_split: {
2287       Temp src0 = get_alu_src(ctx, instr->src[0]);
2288       Temp src1 = get_alu_src(ctx, instr->src[1]);
2289
2290       bld.pseudo(aco_opcode::p_create_vector, Definition(dst), src0, src1);
2291       break;
2292    }
2293    case nir_op_unpack_64_2x32_split_x:
2294       bld.pseudo(aco_opcode::p_split_vector, Definition(dst), bld.def(dst.regClass()), get_alu_src(ctx, instr->src[0]));
2295       break;
2296    case nir_op_unpack_64_2x32_split_y:
2297       bld.pseudo(aco_opcode::p_split_vector, bld.def(dst.regClass()), Definition(dst), get_alu_src(ctx, instr->src[0]));
2298       break;
2299    case nir_op_pack_half_2x16: {
2300       Temp src = get_alu_src(ctx, instr->src[0], 2);
2301
2302       if (dst.regClass() == v1) {
2303          Temp src0 = bld.tmp(v1);
2304          Temp src1 = bld.tmp(v1);
2305          bld.pseudo(aco_opcode::p_split_vector, Definition(src0), Definition(src1), src);
2306          if (!ctx->block->fp_mode.care_about_round32 || ctx->block->fp_mode.round32 == fp_round_tz)
2307             bld.vop3(aco_opcode::v_cvt_pkrtz_f16_f32, Definition(dst), src0, src1);
2308          else
2309             bld.vop3(aco_opcode::v_cvt_pk_u16_u32, Definition(dst),
2310                      bld.vop1(aco_opcode::v_cvt_f32_f16, bld.def(v1), src0),
2311                      bld.vop1(aco_opcode::v_cvt_f32_f16, bld.def(v1), src1));
2312       } else {
2313          fprintf(stderr, "Unimplemented NIR instr bit size: ");
2314          nir_print_instr(&instr->instr, stderr);
2315          fprintf(stderr, "\n");
2316       }
2317       break;
2318    }
2319    case nir_op_unpack_half_2x16_split_x: {
2320       if (dst.regClass() == v1) {
2321          Builder bld(ctx->program, ctx->block);
2322          bld.vop1(aco_opcode::v_cvt_f32_f16, Definition(dst), get_alu_src(ctx, instr->src[0]));
2323       } else {
2324          fprintf(stderr, "Unimplemented NIR instr bit size: ");
2325          nir_print_instr(&instr->instr, stderr);
2326          fprintf(stderr, "\n");
2327       }
2328       break;
2329    }
2330    case nir_op_unpack_half_2x16_split_y: {
2331       if (dst.regClass() == v1) {
2332          Builder bld(ctx->program, ctx->block);
2333          /* TODO: use SDWA here */
2334          bld.vop1(aco_opcode::v_cvt_f32_f16, Definition(dst),
2335                   bld.vop2(aco_opcode::v_lshrrev_b32, bld.def(v1), Operand(16u), as_vgpr(ctx, get_alu_src(ctx, instr->src[0]))));
2336       } else {
2337          fprintf(stderr, "Unimplemented NIR instr bit size: ");
2338          nir_print_instr(&instr->instr, stderr);
2339          fprintf(stderr, "\n");
2340       }
2341       break;
2342    }
2343    case nir_op_fquantize2f16: {
2344       Temp src = get_alu_src(ctx, instr->src[0]);
2345       Temp f16 = bld.vop1(aco_opcode::v_cvt_f16_f32, bld.def(v1), src);
2346       Temp f32, cmp_res;
2347
2348       if (ctx->program->chip_class >= GFX8) {
2349          Temp mask = bld.copy(bld.def(s1), Operand(0x36Fu)); /* value is NOT negative/positive denormal value */
2350          cmp_res = bld.vopc_e64(aco_opcode::v_cmp_class_f16, bld.hint_vcc(bld.def(bld.lm)), f16, mask);
2351          f32 = bld.vop1(aco_opcode::v_cvt_f32_f16, bld.def(v1), f16);
2352       } else {
2353          /* 0x38800000 is smallest half float value (2^-14) in 32-bit float,
2354           * so compare the result and flush to 0 if it's smaller.
2355           */
2356          f32 = bld.vop1(aco_opcode::v_cvt_f32_f16, bld.def(v1), f16);
2357          Temp smallest = bld.copy(bld.def(s1), Operand(0x38800000u));
2358          Instruction* vop3 = bld.vopc_e64(aco_opcode::v_cmp_nlt_f32, bld.hint_vcc(bld.def(bld.lm)), f32, smallest);
2359          static_cast<VOP3A_instruction*>(vop3)->abs[0] = true;
2360          cmp_res = vop3->definitions[0].getTemp();
2361       }
2362
2363       if (ctx->block->fp_mode.preserve_signed_zero_inf_nan32 || ctx->program->chip_class < GFX8) {
2364          Temp copysign_0 = bld.vop2(aco_opcode::v_mul_f32, bld.def(v1), Operand(0u), as_vgpr(ctx, src));
2365          bld.vop2(aco_opcode::v_cndmask_b32, Definition(dst), copysign_0, f32, cmp_res);
2366       } else {
2367          bld.vop2(aco_opcode::v_cndmask_b32, Definition(dst), Operand(0u), f32, cmp_res);
2368       }
2369       break;
2370    }
2371    case nir_op_bfm: {
2372       Temp bits = get_alu_src(ctx, instr->src[0]);
2373       Temp offset = get_alu_src(ctx, instr->src[1]);
2374
2375       if (dst.regClass() == s1) {
2376          bld.sop2(aco_opcode::s_bfm_b32, Definition(dst), bits, offset);
2377       } else if (dst.regClass() == v1) {
2378          bld.vop3(aco_opcode::v_bfm_b32, Definition(dst), bits, offset);
2379       } else {
2380          fprintf(stderr, "Unimplemented NIR instr bit size: ");
2381          nir_print_instr(&instr->instr, stderr);
2382          fprintf(stderr, "\n");
2383       }
2384       break;
2385    }
2386    case nir_op_bitfield_select: {
2387       /* (mask & insert) | (~mask & base) */
2388       Temp bitmask = get_alu_src(ctx, instr->src[0]);
2389       Temp insert = get_alu_src(ctx, instr->src[1]);
2390       Temp base = get_alu_src(ctx, instr->src[2]);
2391
2392       /* dst = (insert & bitmask) | (base & ~bitmask) */
2393       if (dst.regClass() == s1) {
2394          aco_ptr<Instruction> sop2;
2395          nir_const_value* const_bitmask = nir_src_as_const_value(instr->src[0].src);
2396          nir_const_value* const_insert = nir_src_as_const_value(instr->src[1].src);
2397          Operand lhs;
2398          if (const_insert && const_bitmask) {
2399             lhs = Operand(const_insert->u32 & const_bitmask->u32);
2400          } else {
2401             insert = bld.sop2(aco_opcode::s_and_b32, bld.def(s1), bld.def(s1, scc), insert, bitmask);
2402             lhs = Operand(insert);
2403          }
2404
2405          Operand rhs;
2406          nir_const_value* const_base = nir_src_as_const_value(instr->src[2].src);
2407          if (const_base && const_bitmask) {
2408             rhs = Operand(const_base->u32 & ~const_bitmask->u32);
2409          } else {
2410             base = bld.sop2(aco_opcode::s_andn2_b32, bld.def(s1), bld.def(s1, scc), base, bitmask);
2411             rhs = Operand(base);
2412          }
2413
2414          bld.sop2(aco_opcode::s_or_b32, Definition(dst), bld.def(s1, scc), rhs, lhs);
2415
2416       } else if (dst.regClass() == v1) {
2417          if (base.type() == RegType::sgpr && (bitmask.type() == RegType::sgpr || (insert.type() == RegType::sgpr)))
2418             base = as_vgpr(ctx, base);
2419          if (insert.type() == RegType::sgpr && bitmask.type() == RegType::sgpr)
2420             insert = as_vgpr(ctx, insert);
2421
2422          bld.vop3(aco_opcode::v_bfi_b32, Definition(dst), bitmask, insert, base);
2423
2424       } else {
2425          fprintf(stderr, "Unimplemented NIR instr bit size: ");
2426          nir_print_instr(&instr->instr, stderr);
2427          fprintf(stderr, "\n");
2428       }
2429       break;
2430    }
2431    case nir_op_ubfe:
2432    case nir_op_ibfe: {
2433       Temp base = get_alu_src(ctx, instr->src[0]);
2434       Temp offset = get_alu_src(ctx, instr->src[1]);
2435       Temp bits = get_alu_src(ctx, instr->src[2]);
2436
2437       if (dst.type() == RegType::sgpr) {
2438          Operand extract;
2439          nir_const_value* const_offset = nir_src_as_const_value(instr->src[1].src);
2440          nir_const_value* const_bits = nir_src_as_const_value(instr->src[2].src);
2441          if (const_offset && const_bits) {
2442             uint32_t const_extract = (const_bits->u32 << 16) | const_offset->u32;
2443             extract = Operand(const_extract);
2444          } else {
2445             Operand width;
2446             if (const_bits) {
2447                width = Operand(const_bits->u32 << 16);
2448             } else {
2449                width = bld.sop2(aco_opcode::s_lshl_b32, bld.def(s1), bld.def(s1, scc), bits, Operand(16u));
2450             }
2451             extract = bld.sop2(aco_opcode::s_or_b32, bld.def(s1), bld.def(s1, scc), offset, width);
2452          }
2453
2454          aco_opcode opcode;
2455          if (dst.regClass() == s1) {
2456             if (instr->op == nir_op_ubfe)
2457                opcode = aco_opcode::s_bfe_u32;
2458             else
2459                opcode = aco_opcode::s_bfe_i32;
2460          } else if (dst.regClass() == s2) {
2461             if (instr->op == nir_op_ubfe)
2462                opcode = aco_opcode::s_bfe_u64;
2463             else
2464                opcode = aco_opcode::s_bfe_i64;
2465          } else {
2466             unreachable("Unsupported BFE bit size");
2467          }
2468
2469          bld.sop2(opcode, Definition(dst), bld.def(s1, scc), base, extract);
2470
2471       } else {
2472          aco_opcode opcode;
2473          if (dst.regClass() == v1) {
2474             if (instr->op == nir_op_ubfe)
2475                opcode = aco_opcode::v_bfe_u32;
2476             else
2477                opcode = aco_opcode::v_bfe_i32;
2478          } else {
2479             unreachable("Unsupported BFE bit size");
2480          }
2481
2482          emit_vop3a_instruction(ctx, instr, opcode, dst);
2483       }
2484       break;
2485    }
2486    case nir_op_bit_count: {
2487       Temp src = get_alu_src(ctx, instr->src[0]);
2488       if (src.regClass() == s1) {
2489          bld.sop1(aco_opcode::s_bcnt1_i32_b32, Definition(dst), bld.def(s1, scc), src);
2490       } else if (src.regClass() == v1) {
2491          bld.vop3(aco_opcode::v_bcnt_u32_b32, Definition(dst), src, Operand(0u));
2492       } else if (src.regClass() == v2) {
2493          bld.vop3(aco_opcode::v_bcnt_u32_b32, Definition(dst),
2494                   emit_extract_vector(ctx, src, 1, v1),
2495                   bld.vop3(aco_opcode::v_bcnt_u32_b32, bld.def(v1),
2496                            emit_extract_vector(ctx, src, 0, v1), Operand(0u)));
2497       } else if (src.regClass() == s2) {
2498          bld.sop1(aco_opcode::s_bcnt1_i32_b64, Definition(dst), bld.def(s1, scc), src);
2499       } else {
2500          fprintf(stderr, "Unimplemented NIR instr bit size: ");
2501          nir_print_instr(&instr->instr, stderr);
2502          fprintf(stderr, "\n");
2503       }
2504       break;
2505    }
2506    case nir_op_flt: {
2507       emit_comparison(ctx, instr, dst, aco_opcode::v_cmp_lt_f32, aco_opcode::v_cmp_lt_f64);
2508       break;
2509    }
2510    case nir_op_fge: {
2511       emit_comparison(ctx, instr, dst, aco_opcode::v_cmp_ge_f32, aco_opcode::v_cmp_ge_f64);
2512       break;
2513    }
2514    case nir_op_feq: {
2515       emit_comparison(ctx, instr, dst, aco_opcode::v_cmp_eq_f32, aco_opcode::v_cmp_eq_f64);
2516       break;
2517    }
2518    case nir_op_fne: {
2519       emit_comparison(ctx, instr, dst, aco_opcode::v_cmp_neq_f32, aco_opcode::v_cmp_neq_f64);
2520       break;
2521    }
2522    case nir_op_ilt: {
2523       emit_comparison(ctx, instr, dst, aco_opcode::v_cmp_lt_i32, aco_opcode::v_cmp_lt_i64, aco_opcode::s_cmp_lt_i32);
2524       break;
2525    }
2526    case nir_op_ige: {
2527       emit_comparison(ctx, instr, dst, aco_opcode::v_cmp_ge_i32, aco_opcode::v_cmp_ge_i64, aco_opcode::s_cmp_ge_i32);
2528       break;
2529    }
2530    case nir_op_ieq: {
2531       if (instr->src[0].src.ssa->bit_size == 1)
2532          emit_boolean_logic(ctx, instr, Builder::s_xnor, dst);
2533       else
2534          emit_comparison(ctx, instr, dst, aco_opcode::v_cmp_eq_i32, aco_opcode::v_cmp_eq_i64, aco_opcode::s_cmp_eq_i32,
2535                          ctx->program->chip_class >= GFX8 ? aco_opcode::s_cmp_eq_u64 : aco_opcode::num_opcodes);
2536       break;
2537    }
2538    case nir_op_ine: {
2539       if (instr->src[0].src.ssa->bit_size == 1)
2540          emit_boolean_logic(ctx, instr, Builder::s_xor, dst);
2541       else
2542          emit_comparison(ctx, instr, dst, aco_opcode::v_cmp_lg_i32, aco_opcode::v_cmp_lg_i64, aco_opcode::s_cmp_lg_i32,
2543                          ctx->program->chip_class >= GFX8 ? aco_opcode::s_cmp_lg_u64 : aco_opcode::num_opcodes);
2544       break;
2545    }
2546    case nir_op_ult: {
2547       emit_comparison(ctx, instr, dst, aco_opcode::v_cmp_lt_u32, aco_opcode::v_cmp_lt_u64, aco_opcode::s_cmp_lt_u32);
2548       break;
2549    }
2550    case nir_op_uge: {
2551       emit_comparison(ctx, instr, dst, aco_opcode::v_cmp_ge_u32, aco_opcode::v_cmp_ge_u64, aco_opcode::s_cmp_ge_u32);
2552       break;
2553    }
2554    case nir_op_fddx:
2555    case nir_op_fddy:
2556    case nir_op_fddx_fine:
2557    case nir_op_fddy_fine:
2558    case nir_op_fddx_coarse:
2559    case nir_op_fddy_coarse: {
2560       Temp src = get_alu_src(ctx, instr->src[0]);
2561       uint16_t dpp_ctrl1, dpp_ctrl2;
2562       if (instr->op == nir_op_fddx_fine) {
2563          dpp_ctrl1 = dpp_quad_perm(0, 0, 2, 2);
2564          dpp_ctrl2 = dpp_quad_perm(1, 1, 3, 3);
2565       } else if (instr->op == nir_op_fddy_fine) {
2566          dpp_ctrl1 = dpp_quad_perm(0, 1, 0, 1);
2567          dpp_ctrl2 = dpp_quad_perm(2, 3, 2, 3);
2568       } else {
2569          dpp_ctrl1 = dpp_quad_perm(0, 0, 0, 0);
2570          if (instr->op == nir_op_fddx || instr->op == nir_op_fddx_coarse)
2571             dpp_ctrl2 = dpp_quad_perm(1, 1, 1, 1);
2572          else
2573             dpp_ctrl2 = dpp_quad_perm(2, 2, 2, 2);
2574       }
2575
2576       Temp tmp;
2577       if (ctx->program->chip_class >= GFX8) {
2578          Temp tl = bld.vop1_dpp(aco_opcode::v_mov_b32, bld.def(v1), src, dpp_ctrl1);
2579          tmp = bld.vop2_dpp(aco_opcode::v_sub_f32, bld.def(v1), src, tl, dpp_ctrl2);
2580       } else {
2581          Temp tl = bld.ds(aco_opcode::ds_swizzle_b32, bld.def(v1), src, (1 << 15) | dpp_ctrl1);
2582          Temp tr = bld.ds(aco_opcode::ds_swizzle_b32, bld.def(v1), src, (1 << 15) | dpp_ctrl2);
2583          tmp = bld.vop2(aco_opcode::v_sub_f32, bld.def(v1), tr, tl);
2584       }
2585       emit_wqm(ctx, tmp, dst, true);
2586       break;
2587    }
2588    default:
2589       fprintf(stderr, "Unknown NIR ALU instr: ");
2590       nir_print_instr(&instr->instr, stderr);
2591       fprintf(stderr, "\n");
2592    }
2593 }
2594
2595 void visit_load_const(isel_context *ctx, nir_load_const_instr *instr)
2596 {
2597    Temp dst = get_ssa_temp(ctx, &instr->def);
2598
2599    // TODO: we really want to have the resulting type as this would allow for 64bit literals
2600    // which get truncated the lsb if double and msb if int
2601    // for now, we only use s_mov_b64 with 64bit inline constants
2602    assert(instr->def.num_components == 1 && "Vector load_const should be lowered to scalar.");
2603    assert(dst.type() == RegType::sgpr);
2604
2605    Builder bld(ctx->program, ctx->block);
2606
2607    if (instr->def.bit_size == 1) {
2608       assert(dst.regClass() == bld.lm);
2609       int val = instr->value[0].b ? -1 : 0;
2610       Operand op = bld.lm.size() == 1 ? Operand((uint32_t) val) : Operand((uint64_t) val);
2611       bld.sop1(Builder::s_mov, Definition(dst), op);
2612    } else if (dst.size() == 1) {
2613       bld.copy(Definition(dst), Operand(instr->value[0].u32));
2614    } else {
2615       assert(dst.size() != 1);
2616       aco_ptr<Pseudo_instruction> vec{create_instruction<Pseudo_instruction>(aco_opcode::p_create_vector, Format::PSEUDO, dst.size(), 1)};
2617       if (instr->def.bit_size == 64)
2618          for (unsigned i = 0; i < dst.size(); i++)
2619             vec->operands[i] = Operand{(uint32_t)(instr->value[0].u64 >> i * 32)};
2620       else {
2621          for (unsigned i = 0; i < dst.size(); i++)
2622             vec->operands[i] = Operand{instr->value[i].u32};
2623       }
2624       vec->definitions[0] = Definition(dst);
2625       ctx->block->instructions.emplace_back(std::move(vec));
2626    }
2627 }
2628
2629 uint32_t widen_mask(uint32_t mask, unsigned multiplier)
2630 {
2631    uint32_t new_mask = 0;
2632    for(unsigned i = 0; i < 32 && (1u << i) <= mask; ++i)
2633       if (mask & (1u << i))
2634          new_mask |= ((1u << multiplier) - 1u) << (i * multiplier);
2635    return new_mask;
2636 }
2637
2638 Operand load_lds_size_m0(isel_context *ctx)
2639 {
2640    /* TODO: m0 does not need to be initialized on GFX9+ */
2641    Builder bld(ctx->program, ctx->block);
2642    return bld.m0((Temp)bld.sopk(aco_opcode::s_movk_i32, bld.def(s1, m0), 0xffff));
2643 }
2644
2645 void load_lds(isel_context *ctx, unsigned elem_size_bytes, Temp dst,
2646               Temp address, unsigned base_offset, unsigned align)
2647 {
2648    assert(util_is_power_of_two_nonzero(align) && align >= 4);
2649
2650    Builder bld(ctx->program, ctx->block);
2651
2652    Operand m = load_lds_size_m0(ctx);
2653
2654    unsigned num_components = dst.size() * 4u / elem_size_bytes;
2655    unsigned bytes_read = 0;
2656    unsigned result_size = 0;
2657    unsigned total_bytes = num_components * elem_size_bytes;
2658    std::array<Temp, NIR_MAX_VEC_COMPONENTS> result;
2659    bool large_ds_read = ctx->options->chip_class >= GFX7;
2660    bool usable_read2 = ctx->options->chip_class >= GFX7;
2661
2662    while (bytes_read < total_bytes) {
2663       unsigned todo = total_bytes - bytes_read;
2664       bool aligned8 = bytes_read % 8 == 0 && align % 8 == 0;
2665       bool aligned16 = bytes_read % 16 == 0 && align % 16 == 0;
2666
2667       aco_opcode op = aco_opcode::last_opcode;
2668       bool read2 = false;
2669       if (todo >= 16 && aligned16 && large_ds_read) {
2670          op = aco_opcode::ds_read_b128;
2671          todo = 16;
2672       } else if (todo >= 16 && aligned8 && usable_read2) {
2673          op = aco_opcode::ds_read2_b64;
2674          read2 = true;
2675          todo = 16;
2676       } else if (todo >= 12 && aligned16 && large_ds_read) {
2677          op = aco_opcode::ds_read_b96;
2678          todo = 12;
2679       } else if (todo >= 8 && aligned8) {
2680          op = aco_opcode::ds_read_b64;
2681          todo = 8;
2682       } else if (todo >= 8 && usable_read2) {
2683          op = aco_opcode::ds_read2_b32;
2684          read2 = true;
2685          todo = 8;
2686       } else if (todo >= 4) {
2687          op = aco_opcode::ds_read_b32;
2688          todo = 4;
2689       } else {
2690          assert(false);
2691       }
2692       assert(todo % elem_size_bytes == 0);
2693       unsigned num_elements = todo / elem_size_bytes;
2694       unsigned offset = base_offset + bytes_read;
2695       unsigned max_offset = read2 ? 1019 : 65535;
2696
2697       Temp address_offset = address;
2698       if (offset > max_offset) {
2699          address_offset = bld.vadd32(bld.def(v1), Operand(base_offset), address_offset);
2700          offset = bytes_read;
2701       }
2702       assert(offset <= max_offset); /* bytes_read shouldn't be large enough for this to happen */
2703
2704       Temp res;
2705       if (num_components == 1 && dst.type() == RegType::vgpr)
2706          res = dst;
2707       else
2708          res = bld.tmp(RegClass(RegType::vgpr, todo / 4));
2709
2710       if (read2)
2711          res = bld.ds(op, Definition(res), address_offset, m, offset >> 2, (offset >> 2) + 1);
2712       else
2713          res = bld.ds(op, Definition(res), address_offset, m, offset);
2714
2715       if (num_components == 1) {
2716          assert(todo == total_bytes);
2717          if (dst.type() == RegType::sgpr)
2718             bld.pseudo(aco_opcode::p_as_uniform, Definition(dst), res);
2719          return;
2720       }
2721
2722       if (dst.type() == RegType::sgpr) {
2723          Temp new_res = bld.tmp(RegType::sgpr, res.size());
2724          expand_vector(ctx, res, new_res, res.size(), (1 << res.size()) - 1);
2725          res = new_res;
2726       }
2727
2728       if (num_elements == 1) {
2729          result[result_size++] = res;
2730       } else {
2731          assert(res != dst && res.size() % num_elements == 0);
2732          aco_ptr<Pseudo_instruction> split{create_instruction<Pseudo_instruction>(aco_opcode::p_split_vector, Format::PSEUDO, 1, num_elements)};
2733          split->operands[0] = Operand(res);
2734          for (unsigned i = 0; i < num_elements; i++)
2735             split->definitions[i] = Definition(result[result_size++] = bld.tmp(res.type(), elem_size_bytes / 4));
2736          ctx->block->instructions.emplace_back(std::move(split));
2737       }
2738
2739       bytes_read += todo;
2740    }
2741
2742    assert(result_size == num_components && result_size > 1);
2743    aco_ptr<Pseudo_instruction> vec{create_instruction<Pseudo_instruction>(aco_opcode::p_create_vector, Format::PSEUDO, result_size, 1)};
2744    for (unsigned i = 0; i < result_size; i++)
2745       vec->operands[i] = Operand(result[i]);
2746    vec->definitions[0] = Definition(dst);
2747    ctx->block->instructions.emplace_back(std::move(vec));
2748    ctx->allocated_vec.emplace(dst.id(), result);
2749 }
2750
2751 Temp extract_subvector(isel_context *ctx, Temp data, unsigned start, unsigned size, RegType type)
2752 {
2753    if (start == 0 && size == data.size())
2754       return type == RegType::vgpr ? as_vgpr(ctx, data) : data;
2755
2756    unsigned size_hint = 1;
2757    auto it = ctx->allocated_vec.find(data.id());
2758    if (it != ctx->allocated_vec.end())
2759       size_hint = it->second[0].size();
2760    if (size % size_hint || start % size_hint)
2761       size_hint = 1;
2762
2763    start /= size_hint;
2764    size /= size_hint;
2765
2766    Temp elems[size];
2767    for (unsigned i = 0; i < size; i++)
2768       elems[i] = emit_extract_vector(ctx, data, start + i, RegClass(type, size_hint));
2769
2770    if (size == 1)
2771       return type == RegType::vgpr ? as_vgpr(ctx, elems[0]) : elems[0];
2772
2773    aco_ptr<Pseudo_instruction> vec{create_instruction<Pseudo_instruction>(aco_opcode::p_create_vector, Format::PSEUDO, size, 1)};
2774    for (unsigned i = 0; i < size; i++)
2775       vec->operands[i] = Operand(elems[i]);
2776    Temp res = {ctx->program->allocateId(), RegClass(type, size * size_hint)};
2777    vec->definitions[0] = Definition(res);
2778    ctx->block->instructions.emplace_back(std::move(vec));
2779    return res;
2780 }
2781
2782 void ds_write_helper(isel_context *ctx, Operand m, Temp address, Temp data, unsigned data_start, unsigned total_size, unsigned offset0, unsigned offset1, unsigned align)
2783 {
2784    Builder bld(ctx->program, ctx->block);
2785    unsigned bytes_written = 0;
2786    bool large_ds_write = ctx->options->chip_class >= GFX7;
2787    bool usable_write2 = ctx->options->chip_class >= GFX7;
2788
2789    while (bytes_written < total_size * 4) {
2790       unsigned todo = total_size * 4 - bytes_written;
2791       bool aligned8 = bytes_written % 8 == 0 && align % 8 == 0;
2792       bool aligned16 = bytes_written % 16 == 0 && align % 16 == 0;
2793
2794       aco_opcode op = aco_opcode::last_opcode;
2795       bool write2 = false;
2796       unsigned size = 0;
2797       if (todo >= 16 && aligned16 && large_ds_write) {
2798          op = aco_opcode::ds_write_b128;
2799          size = 4;
2800       } else if (todo >= 16 && aligned8 && usable_write2) {
2801          op = aco_opcode::ds_write2_b64;
2802          write2 = true;
2803          size = 4;
2804       } else if (todo >= 12 && aligned16 && large_ds_write) {
2805          op = aco_opcode::ds_write_b96;
2806          size = 3;
2807       } else if (todo >= 8 && aligned8) {
2808          op = aco_opcode::ds_write_b64;
2809          size = 2;
2810       } else if (todo >= 8 && usable_write2) {
2811          op = aco_opcode::ds_write2_b32;
2812          write2 = true;
2813          size = 2;
2814       } else if (todo >= 4) {
2815          op = aco_opcode::ds_write_b32;
2816          size = 1;
2817       } else {
2818          assert(false);
2819       }
2820
2821       unsigned offset = offset0 + offset1 + bytes_written;
2822       unsigned max_offset = write2 ? 1020 : 65535;
2823       Temp address_offset = address;
2824       if (offset > max_offset) {
2825          address_offset = bld.vadd32(bld.def(v1), Operand(offset0), address_offset);
2826          offset = offset1 + bytes_written;
2827       }
2828       assert(offset <= max_offset); /* offset1 shouldn't be large enough for this to happen */
2829
2830       if (write2) {
2831          Temp val0 = extract_subvector(ctx, data, data_start + (bytes_written >> 2), size / 2, RegType::vgpr);
2832          Temp val1 = extract_subvector(ctx, data, data_start + (bytes_written >> 2) + 1, size / 2, RegType::vgpr);
2833          bld.ds(op, address_offset, val0, val1, m, offset >> 2, (offset >> 2) + 1);
2834       } else {
2835          Temp val = extract_subvector(ctx, data, data_start + (bytes_written >> 2), size, RegType::vgpr);
2836          bld.ds(op, address_offset, val, m, offset);
2837       }
2838
2839       bytes_written += size * 4;
2840    }
2841 }
2842
2843 void store_lds(isel_context *ctx, unsigned elem_size_bytes, Temp data, uint32_t wrmask,
2844                Temp address, unsigned base_offset, unsigned align)
2845 {
2846    assert(util_is_power_of_two_nonzero(align) && align >= 4);
2847
2848    Operand m = load_lds_size_m0(ctx);
2849
2850    /* we need at most two stores for 32bit variables */
2851    int start[2], count[2];
2852    u_bit_scan_consecutive_range(&wrmask, &start[0], &count[0]);
2853    u_bit_scan_consecutive_range(&wrmask, &start[1], &count[1]);
2854    assert(wrmask == 0);
2855
2856    /* one combined store is sufficient */
2857    if (count[0] == count[1]) {
2858       Builder bld(ctx->program, ctx->block);
2859
2860       Temp address_offset = address;
2861       if ((base_offset >> 2) + start[1] > 255) {
2862          address_offset = bld.vadd32(bld.def(v1), Operand(base_offset), address_offset);
2863          base_offset = 0;
2864       }
2865
2866       assert(count[0] == 1);
2867       Temp val0 = emit_extract_vector(ctx, data, start[0], v1);
2868       Temp val1 = emit_extract_vector(ctx, data, start[1], v1);
2869       aco_opcode op = elem_size_bytes == 4 ? aco_opcode::ds_write2_b32 : aco_opcode::ds_write2_b64;
2870       base_offset = base_offset / elem_size_bytes;
2871       bld.ds(op, address_offset, val0, val1, m,
2872              base_offset + start[0], base_offset + start[1]);
2873       return;
2874    }
2875
2876    for (unsigned i = 0; i < 2; i++) {
2877       if (count[i] == 0)
2878          continue;
2879
2880       unsigned elem_size_words = elem_size_bytes / 4;
2881       ds_write_helper(ctx, m, address, data, start[i] * elem_size_words, count[i] * elem_size_words,
2882                       base_offset, start[i] * elem_size_bytes, align);
2883    }
2884    return;
2885 }
2886
2887 unsigned calculate_lds_alignment(isel_context *ctx, unsigned const_offset)
2888 {
2889    unsigned align = 16;
2890    if (const_offset)
2891       align = std::min(align, 1u << (ffs(const_offset) - 1));
2892
2893    return align;
2894 }
2895
2896
2897 Temp create_vec_from_array(isel_context *ctx, Temp arr[], unsigned cnt, RegType reg_type, unsigned split_cnt = 0u, Temp dst = Temp())
2898 {
2899    Builder bld(ctx->program, ctx->block);
2900
2901    if (!dst.id())
2902       dst = bld.tmp(RegClass(reg_type, cnt * arr[0].size()));
2903
2904    std::array<Temp, NIR_MAX_VEC_COMPONENTS> allocated_vec;
2905    aco_ptr<Pseudo_instruction> instr {create_instruction<Pseudo_instruction>(aco_opcode::p_create_vector, Format::PSEUDO, cnt, 1)};
2906    instr->definitions[0] = Definition(dst);
2907
2908    for (unsigned i = 0; i < cnt; ++i) {
2909       assert(arr[i].size() == arr[0].size());
2910       allocated_vec[i] = arr[i];
2911       instr->operands[i] = Operand(arr[i]);
2912    }
2913
2914    bld.insert(std::move(instr));
2915
2916    if (split_cnt)
2917       emit_split_vector(ctx, dst, split_cnt);
2918    else
2919       ctx->allocated_vec.emplace(dst.id(), allocated_vec); /* emit_split_vector already does this */
2920
2921    return dst;
2922 }
2923
2924 inline unsigned resolve_excess_vmem_const_offset(Builder &bld, Temp &voffset, unsigned const_offset)
2925 {
2926    if (const_offset >= 4096) {
2927       unsigned excess_const_offset = const_offset / 4096u * 4096u;
2928       const_offset %= 4096u;
2929
2930       if (!voffset.id())
2931          voffset = bld.copy(bld.def(v1), Operand(excess_const_offset));
2932       else if (unlikely(voffset.regClass() == s1))
2933          voffset = bld.sop2(aco_opcode::s_add_u32, bld.def(s1), bld.def(s1, scc), Operand(excess_const_offset), Operand(voffset));
2934       else if (likely(voffset.regClass() == v1))
2935          voffset = bld.vadd32(bld.def(v1), Operand(voffset), Operand(excess_const_offset));
2936       else
2937          unreachable("Unsupported register class of voffset");
2938    }
2939
2940    return const_offset;
2941 }
2942
2943 void emit_single_mubuf_store(isel_context *ctx, Temp descriptor, Temp voffset, Temp soffset, Temp vdata,
2944                              unsigned const_offset = 0u, bool allow_reorder = true, bool slc = false)
2945 {
2946    assert(vdata.id());
2947    assert(vdata.size() != 3 || ctx->program->chip_class != GFX6);
2948    assert(vdata.size() >= 1 && vdata.size() <= 4);
2949
2950    Builder bld(ctx->program, ctx->block);
2951    aco_opcode op = (aco_opcode) ((unsigned) aco_opcode::buffer_store_dword + vdata.size() - 1);
2952    const_offset = resolve_excess_vmem_const_offset(bld, voffset, const_offset);
2953
2954    Operand voffset_op = voffset.id() ? Operand(as_vgpr(ctx, voffset)) : Operand(v1);
2955    Operand soffset_op = soffset.id() ? Operand(soffset) : Operand(0u);
2956    Builder::Result r = bld.mubuf(op, Operand(descriptor), voffset_op, soffset_op, Operand(vdata), const_offset,
2957                                  /* offen */ !voffset_op.isUndefined(), /* idxen*/ false, /* addr64 */ false,
2958                                  /* disable_wqm */ false, /* glc */ true, /* dlc*/ false, /* slc */ slc);
2959
2960    static_cast<MUBUF_instruction *>(r.instr)->can_reorder = allow_reorder;
2961 }
2962
2963 void store_vmem_mubuf(isel_context *ctx, Temp src, Temp descriptor, Temp voffset, Temp soffset,
2964                                    unsigned base_const_offset, unsigned elem_size_bytes, unsigned write_mask,
2965                                    bool allow_combining = true, bool reorder = true, bool slc = false)
2966 {
2967    Builder bld(ctx->program, ctx->block);
2968    assert(elem_size_bytes == 4 || elem_size_bytes == 8);
2969    assert(write_mask);
2970
2971    if (elem_size_bytes == 8) {
2972       elem_size_bytes = 4;
2973       write_mask = widen_mask(write_mask, 2);
2974    }
2975
2976    while (write_mask) {
2977       int start = 0;
2978       int count = 0;
2979       u_bit_scan_consecutive_range(&write_mask, &start, &count);
2980       assert(count > 0);
2981       assert(start >= 0);
2982
2983       while (count > 0) {
2984          unsigned sub_count = allow_combining ? MIN2(count, 4) : 1;
2985          unsigned const_offset = (unsigned) start * elem_size_bytes + base_const_offset;
2986
2987          /* GFX6 doesn't have buffer_store_dwordx3, so make sure not to emit that here either. */
2988          if (unlikely(ctx->program->chip_class == GFX6 && sub_count == 3))
2989             sub_count = 2;
2990
2991          Temp elem = extract_subvector(ctx, src, start, sub_count, RegType::vgpr);
2992          emit_single_mubuf_store(ctx, descriptor, voffset, soffset, elem, const_offset, reorder, slc);
2993
2994          count -= sub_count;
2995          start += sub_count;
2996       }
2997
2998       assert(count == 0);
2999    }
3000 }
3001
3002 Temp emit_single_mubuf_load(isel_context *ctx, Temp descriptor, Temp voffset, Temp soffset,
3003                             unsigned const_offset, unsigned size_dwords, bool allow_reorder = true)
3004 {
3005    assert(size_dwords != 3 || ctx->program->chip_class != GFX6);
3006    assert(size_dwords >= 1 && size_dwords <= 4);
3007
3008    Builder bld(ctx->program, ctx->block);
3009    Temp vdata = bld.tmp(RegClass(RegType::vgpr, size_dwords));
3010    aco_opcode op = (aco_opcode) ((unsigned) aco_opcode::buffer_load_dword + size_dwords - 1);
3011    const_offset = resolve_excess_vmem_const_offset(bld, voffset, const_offset);
3012
3013    Operand voffset_op = voffset.id() ? Operand(as_vgpr(ctx, voffset)) : Operand(v1);
3014    Operand soffset_op = soffset.id() ? Operand(soffset) : Operand(0u);
3015    Builder::Result r = bld.mubuf(op, Definition(vdata), Operand(descriptor), voffset_op, soffset_op, const_offset,
3016                                  /* offen */ !voffset_op.isUndefined(), /* idxen*/ false, /* addr64 */ false,
3017                                  /* disable_wqm */ false, /* glc */ true,
3018                                  /* dlc*/ ctx->program->chip_class >= GFX10, /* slc */ false);
3019
3020    static_cast<MUBUF_instruction *>(r.instr)->can_reorder = allow_reorder;
3021
3022    return vdata;
3023 }
3024
3025 void load_vmem_mubuf(isel_context *ctx, Temp dst, Temp descriptor, Temp voffset, Temp soffset,
3026                      unsigned base_const_offset, unsigned elem_size_bytes, unsigned num_components,
3027                      unsigned stride = 0u, bool allow_combining = true, bool allow_reorder = true)
3028 {
3029    assert(elem_size_bytes == 4 || elem_size_bytes == 8);
3030    assert((num_components * elem_size_bytes / 4) == dst.size());
3031    assert(!!stride != allow_combining);
3032
3033    Builder bld(ctx->program, ctx->block);
3034    unsigned split_cnt = num_components;
3035
3036    if (elem_size_bytes == 8) {
3037       elem_size_bytes = 4;
3038       num_components *= 2;
3039    }
3040
3041    if (!stride)
3042       stride = elem_size_bytes;
3043
3044    unsigned load_size = 1;
3045    if (allow_combining) {
3046       if ((num_components % 4) == 0)
3047          load_size = 4;
3048       else if ((num_components % 3) == 0 && ctx->program->chip_class != GFX6)
3049          load_size = 3;
3050       else if ((num_components % 2) == 0)
3051          load_size = 2;
3052    }
3053
3054    unsigned num_loads = num_components / load_size;
3055    std::array<Temp, NIR_MAX_VEC_COMPONENTS> elems;
3056
3057    for (unsigned i = 0; i < num_loads; ++i) {
3058       unsigned const_offset = i * stride * load_size + base_const_offset;
3059       elems[i] = emit_single_mubuf_load(ctx, descriptor, voffset, soffset, const_offset, load_size, allow_reorder);
3060    }
3061
3062    create_vec_from_array(ctx, elems.data(), num_loads, RegType::vgpr, split_cnt, dst);
3063 }
3064
3065 std::pair<Temp, unsigned> offset_add_from_nir(isel_context *ctx, const std::pair<Temp, unsigned> &base_offset, nir_src *off_src, unsigned stride = 1u)
3066 {
3067    Builder bld(ctx->program, ctx->block);
3068    Temp offset = base_offset.first;
3069    unsigned const_offset = base_offset.second;
3070
3071    if (!nir_src_is_const(*off_src)) {
3072       Temp indirect_offset_arg = get_ssa_temp(ctx, off_src->ssa);
3073       Temp with_stride;
3074
3075       /* Calculate indirect offset with stride */
3076       if (likely(indirect_offset_arg.regClass() == v1))
3077          with_stride = bld.v_mul_imm(bld.def(v1), indirect_offset_arg, stride);
3078       else if (indirect_offset_arg.regClass() == s1)
3079          with_stride = bld.sop2(aco_opcode::s_mul_i32, bld.def(s1), Operand(stride), indirect_offset_arg);
3080       else
3081          unreachable("Unsupported register class of indirect offset");
3082
3083       /* Add to the supplied base offset */
3084       if (offset.id() == 0)
3085          offset = with_stride;
3086       else if (unlikely(offset.regClass() == s1 && with_stride.regClass() == s1))
3087          offset = bld.sop2(aco_opcode::s_add_u32, bld.def(s1), bld.def(s1, scc), with_stride, offset);
3088       else if (offset.size() == 1 && with_stride.size() == 1)
3089          offset = bld.vadd32(bld.def(v1), with_stride, offset);
3090       else
3091          unreachable("Unsupported register class of indirect offset");
3092    } else {
3093       unsigned const_offset_arg = nir_src_as_uint(*off_src);
3094       const_offset += const_offset_arg * stride;
3095    }
3096
3097    return std::make_pair(offset, const_offset);
3098 }
3099
3100 std::pair<Temp, unsigned> offset_add(isel_context *ctx, const std::pair<Temp, unsigned> &off1, const std::pair<Temp, unsigned> &off2)
3101 {
3102    Builder bld(ctx->program, ctx->block);
3103    Temp offset;
3104
3105    if (off1.first.id() && off2.first.id()) {
3106       if (unlikely(off1.first.regClass() == s1 && off2.first.regClass() == s1))
3107          offset = bld.sop2(aco_opcode::s_add_u32, bld.def(s1), bld.def(s1, scc), off1.first, off2.first);
3108       else if (off1.first.size() == 1 && off2.first.size() == 1)
3109          offset = bld.vadd32(bld.def(v1), off1.first, off2.first);
3110       else
3111          unreachable("Unsupported register class of indirect offset");
3112    } else {
3113       offset = off1.first.id() ? off1.first : off2.first;
3114    }
3115
3116    return std::make_pair(offset, off1.second + off2.second);
3117 }
3118
3119 std::pair<Temp, unsigned> offset_mul(isel_context *ctx, const std::pair<Temp, unsigned> &offs, unsigned multiplier)
3120 {
3121    Builder bld(ctx->program, ctx->block);
3122    unsigned const_offset = offs.second * multiplier;
3123
3124    if (!offs.first.id())
3125       return std::make_pair(offs.first, const_offset);
3126
3127    Temp offset = unlikely(offs.first.regClass() == s1)
3128                  ? bld.sop2(aco_opcode::s_mul_i32, bld.def(s1), Operand(multiplier), offs.first)
3129                  : bld.v_mul_imm(bld.def(v1), offs.first, multiplier);
3130
3131    return std::make_pair(offset, const_offset);
3132 }
3133
3134 std::pair<Temp, unsigned> get_intrinsic_io_basic_offset(isel_context *ctx, nir_intrinsic_instr *instr, unsigned base_stride, unsigned component_stride)
3135 {
3136    Builder bld(ctx->program, ctx->block);
3137
3138    /* base is the driver_location, which is already multiplied by 4, so is in dwords */
3139    unsigned const_offset = nir_intrinsic_base(instr) * base_stride;
3140    /* component is in bytes */
3141    const_offset += nir_intrinsic_component(instr) * component_stride;
3142
3143    /* offset should be interpreted in relation to the base, so the instruction effectively reads/writes another input/output when it has an offset */
3144    nir_src *off_src = nir_get_io_offset_src(instr);
3145    return offset_add_from_nir(ctx, std::make_pair(Temp(), const_offset), off_src, 4u * base_stride);
3146 }
3147
3148 std::pair<Temp, unsigned> get_intrinsic_io_basic_offset(isel_context *ctx, nir_intrinsic_instr *instr, unsigned stride = 1u)
3149 {
3150    return get_intrinsic_io_basic_offset(ctx, instr, stride, stride);
3151 }
3152
3153 void visit_store_vsgs_output(isel_context *ctx, nir_intrinsic_instr *instr)
3154 {
3155    unsigned write_mask = nir_intrinsic_write_mask(instr);
3156    unsigned component = nir_intrinsic_component(instr);
3157    Temp src = get_ssa_temp(ctx, instr->src[0].ssa);
3158    unsigned idx = (nir_intrinsic_base(instr) + component) * 4u;
3159    Operand offset(s1);
3160    Builder bld(ctx->program, ctx->block);
3161
3162    nir_instr *off_instr = instr->src[1].ssa->parent_instr;
3163    if (off_instr->type != nir_instr_type_load_const)
3164       offset = bld.v_mul24_imm(bld.def(v1), get_ssa_temp(ctx, instr->src[1].ssa), 16u);
3165    else
3166       idx += nir_instr_as_load_const(off_instr)->value[0].u32 * 16u;
3167
3168    unsigned elem_size_bytes = instr->src[0].ssa->bit_size / 8u;
3169    if (ctx->stage == vertex_es) {
3170       Temp esgs_ring = bld.smem(aco_opcode::s_load_dwordx4, bld.def(s4), ctx->program->private_segment_buffer, Operand(RING_ESGS_VS * 16u));
3171
3172       Temp elems[NIR_MAX_VEC_COMPONENTS * 2];
3173       if (elem_size_bytes == 8) {
3174          for (unsigned i = 0; i < src.size() / 2; i++) {
3175             Temp elem = emit_extract_vector(ctx, src, i, v2);
3176             elems[i*2] = bld.tmp(v1);
3177             elems[i*2+1] = bld.tmp(v1);
3178             bld.pseudo(aco_opcode::p_split_vector, Definition(elems[i*2]), Definition(elems[i*2+1]), elem);
3179          }
3180          write_mask = widen_mask(write_mask, 2);
3181          elem_size_bytes /= 2u;
3182       } else {
3183          for (unsigned i = 0; i < src.size(); i++)
3184             elems[i] = emit_extract_vector(ctx, src, i, v1);
3185       }
3186
3187       while (write_mask) {
3188          unsigned index = u_bit_scan(&write_mask);
3189          unsigned offset = index * elem_size_bytes;
3190          Temp elem = emit_extract_vector(ctx, src, index, RegClass(RegType::vgpr, elem_size_bytes / 4));
3191
3192          Operand vaddr_offset(v1);
3193          unsigned const_offset = idx + offset;
3194          if (const_offset >= 4096u) {
3195             vaddr_offset = bld.copy(bld.def(v1), Operand(const_offset / 4096u * 4096u));
3196             const_offset %= 4096u;
3197          }
3198
3199          aco_ptr<MTBUF_instruction> mtbuf{create_instruction<MTBUF_instruction>(aco_opcode::tbuffer_store_format_x, Format::MTBUF, 4, 0)};
3200          mtbuf->operands[0] = Operand(esgs_ring);
3201          mtbuf->operands[1] = vaddr_offset;
3202          mtbuf->operands[2] = Operand(get_arg(ctx, ctx->args->es2gs_offset));
3203          mtbuf->operands[3] = Operand(elem);
3204          mtbuf->offen = !vaddr_offset.isUndefined();
3205          mtbuf->dfmt = V_008F0C_BUF_DATA_FORMAT_32;
3206          mtbuf->nfmt = V_008F0C_BUF_NUM_FORMAT_UINT;
3207          mtbuf->offset = const_offset;
3208          mtbuf->glc = true;
3209          mtbuf->slc = true;
3210          mtbuf->barrier = barrier_none;
3211          mtbuf->can_reorder = true;
3212          bld.insert(std::move(mtbuf));
3213       }
3214    } else {
3215       unsigned itemsize = ctx->program->info->vs.es_info.esgs_itemsize;
3216
3217       Temp vertex_idx = emit_mbcnt(ctx, bld.def(v1));
3218       Temp wave_idx = bld.sop2(aco_opcode::s_bfe_u32, bld.def(s1), bld.def(s1, scc), get_arg(ctx, ctx->args->merged_wave_info), Operand(4u << 16 | 24));
3219       vertex_idx = bld.vop2(aco_opcode::v_or_b32, bld.def(v1), vertex_idx,
3220                             bld.v_mul24_imm(bld.def(v1), as_vgpr(ctx, wave_idx), ctx->program->wave_size));
3221
3222       Temp lds_base = bld.v_mul24_imm(bld.def(v1), vertex_idx, itemsize);
3223       if (!offset.isUndefined())
3224          lds_base = bld.vadd32(bld.def(v1), offset, lds_base);
3225
3226       unsigned align = calculate_lds_alignment(ctx, idx);
3227       store_lds(ctx, elem_size_bytes, src, write_mask, lds_base, idx, align);
3228    }
3229 }
3230
3231 void visit_store_output(isel_context *ctx, nir_intrinsic_instr *instr)
3232 {
3233    if (ctx->stage == vertex_vs ||
3234        ctx->stage == fragment_fs ||
3235        ctx->shader->info.stage == MESA_SHADER_GEOMETRY) {
3236       unsigned write_mask = nir_intrinsic_write_mask(instr);
3237       unsigned component = nir_intrinsic_component(instr);
3238       Temp src = get_ssa_temp(ctx, instr->src[0].ssa);
3239       unsigned idx = nir_intrinsic_base(instr) + component;
3240
3241       nir_instr *off_instr = instr->src[1].ssa->parent_instr;
3242       if (off_instr->type != nir_instr_type_load_const) {
3243          fprintf(stderr, "Unimplemented nir_intrinsic_load_input offset\n");
3244          nir_print_instr(off_instr, stderr);
3245          fprintf(stderr, "\n");
3246       }
3247       idx += nir_instr_as_load_const(off_instr)->value[0].u32 * 4u;
3248
3249       if (instr->src[0].ssa->bit_size == 64)
3250          write_mask = widen_mask(write_mask, 2);
3251
3252       for (unsigned i = 0; i < 8; ++i) {
3253          if (write_mask & (1 << i)) {
3254             ctx->outputs.mask[idx / 4u] |= 1 << (idx % 4u);
3255             ctx->outputs.outputs[idx / 4u][idx % 4u] = emit_extract_vector(ctx, src, i, v1);
3256          }
3257          idx++;
3258       }
3259    } else if (ctx->stage == vertex_es ||
3260               (ctx->stage == vertex_geometry_gs && ctx->shader->info.stage == MESA_SHADER_VERTEX)) {
3261       visit_store_vsgs_output(ctx, instr);
3262    } else {
3263       unreachable("Shader stage not implemented");
3264    }
3265 }
3266
3267 void emit_interp_instr(isel_context *ctx, unsigned idx, unsigned component, Temp src, Temp dst, Temp prim_mask)
3268 {
3269    Temp coord1 = emit_extract_vector(ctx, src, 0, v1);
3270    Temp coord2 = emit_extract_vector(ctx, src, 1, v1);
3271
3272    Builder bld(ctx->program, ctx->block);
3273    Temp tmp = bld.vintrp(aco_opcode::v_interp_p1_f32, bld.def(v1), coord1, bld.m0(prim_mask), idx, component);
3274    bld.vintrp(aco_opcode::v_interp_p2_f32, Definition(dst), coord2, bld.m0(prim_mask), tmp, idx, component);
3275 }
3276
3277 void emit_load_frag_coord(isel_context *ctx, Temp dst, unsigned num_components)
3278 {
3279    aco_ptr<Pseudo_instruction> vec(create_instruction<Pseudo_instruction>(aco_opcode::p_create_vector, Format::PSEUDO, num_components, 1));
3280    for (unsigned i = 0; i < num_components; i++)
3281       vec->operands[i] = Operand(get_arg(ctx, ctx->args->ac.frag_pos[i]));
3282    if (G_0286CC_POS_W_FLOAT_ENA(ctx->program->config->spi_ps_input_ena)) {
3283       assert(num_components == 4);
3284       Builder bld(ctx->program, ctx->block);
3285       vec->operands[3] = bld.vop1(aco_opcode::v_rcp_f32, bld.def(v1), get_arg(ctx, ctx->args->ac.frag_pos[3]));
3286    }
3287
3288    for (Operand& op : vec->operands)
3289       op = op.isUndefined() ? Operand(0u) : op;
3290
3291    vec->definitions[0] = Definition(dst);
3292    ctx->block->instructions.emplace_back(std::move(vec));
3293    emit_split_vector(ctx, dst, num_components);
3294    return;
3295 }
3296
3297 void visit_load_interpolated_input(isel_context *ctx, nir_intrinsic_instr *instr)
3298 {
3299    Temp dst = get_ssa_temp(ctx, &instr->dest.ssa);
3300    Temp coords = get_ssa_temp(ctx, instr->src[0].ssa);
3301    unsigned idx = nir_intrinsic_base(instr);
3302    unsigned component = nir_intrinsic_component(instr);
3303    Temp prim_mask = get_arg(ctx, ctx->args->ac.prim_mask);
3304
3305    nir_const_value* offset = nir_src_as_const_value(instr->src[1]);
3306    if (offset) {
3307       assert(offset->u32 == 0);
3308    } else {
3309       /* the lower 15bit of the prim_mask contain the offset into LDS
3310        * while the upper bits contain the number of prims */
3311       Temp offset_src = get_ssa_temp(ctx, instr->src[1].ssa);
3312       assert(offset_src.regClass() == s1 && "TODO: divergent offsets...");
3313       Builder bld(ctx->program, ctx->block);
3314       Temp stride = bld.sop2(aco_opcode::s_lshr_b32, bld.def(s1), bld.def(s1, scc), prim_mask, Operand(16u));
3315       stride = bld.sop1(aco_opcode::s_bcnt1_i32_b32, bld.def(s1), bld.def(s1, scc), stride);
3316       stride = bld.sop2(aco_opcode::s_mul_i32, bld.def(s1), stride, Operand(48u));
3317       offset_src = bld.sop2(aco_opcode::s_mul_i32, bld.def(s1), stride, offset_src);
3318       prim_mask = bld.sop2(aco_opcode::s_add_i32, bld.def(s1, m0), bld.def(s1, scc), offset_src, prim_mask);
3319    }
3320
3321    if (instr->dest.ssa.num_components == 1) {
3322       emit_interp_instr(ctx, idx, component, coords, dst, prim_mask);
3323    } else {
3324       aco_ptr<Pseudo_instruction> vec(create_instruction<Pseudo_instruction>(aco_opcode::p_create_vector, Format::PSEUDO, instr->dest.ssa.num_components, 1));
3325       for (unsigned i = 0; i < instr->dest.ssa.num_components; i++)
3326       {
3327          Temp tmp = {ctx->program->allocateId(), v1};
3328          emit_interp_instr(ctx, idx, component+i, coords, tmp, prim_mask);
3329          vec->operands[i] = Operand(tmp);
3330       }
3331       vec->definitions[0] = Definition(dst);
3332       ctx->block->instructions.emplace_back(std::move(vec));
3333    }
3334 }
3335
3336 bool check_vertex_fetch_size(isel_context *ctx, const ac_data_format_info *vtx_info,
3337                              unsigned offset, unsigned stride, unsigned channels)
3338 {
3339    unsigned vertex_byte_size = vtx_info->chan_byte_size * channels;
3340    if (vtx_info->chan_byte_size != 4 && channels == 3)
3341       return false;
3342    return (ctx->options->chip_class != GFX6 && ctx->options->chip_class != GFX10) ||
3343           (offset % vertex_byte_size == 0 && stride % vertex_byte_size == 0);
3344 }
3345
3346 uint8_t get_fetch_data_format(isel_context *ctx, const ac_data_format_info *vtx_info,
3347                               unsigned offset, unsigned stride, unsigned *channels)
3348 {
3349    if (!vtx_info->chan_byte_size) {
3350       *channels = vtx_info->num_channels;
3351       return vtx_info->chan_format;
3352    }
3353
3354    unsigned num_channels = *channels;
3355    if (!check_vertex_fetch_size(ctx, vtx_info, offset, stride, *channels)) {
3356       unsigned new_channels = num_channels + 1;
3357       /* first, assume more loads is worse and try using a larger data format */
3358       while (new_channels <= 4 && !check_vertex_fetch_size(ctx, vtx_info, offset, stride, new_channels)) {
3359          new_channels++;
3360          /* don't make the attribute potentially out-of-bounds */
3361          if (offset + new_channels * vtx_info->chan_byte_size > stride)
3362             new_channels = 5;
3363       }
3364
3365       if (new_channels == 5) {
3366          /* then try decreasing load size (at the cost of more loads) */
3367          new_channels = *channels;
3368          while (new_channels > 1 && !check_vertex_fetch_size(ctx, vtx_info, offset, stride, new_channels))
3369             new_channels--;
3370       }
3371
3372       if (new_channels < *channels)
3373          *channels = new_channels;
3374       num_channels = new_channels;
3375    }
3376
3377    switch (vtx_info->chan_format) {
3378    case V_008F0C_BUF_DATA_FORMAT_8:
3379       return (uint8_t[]){V_008F0C_BUF_DATA_FORMAT_8, V_008F0C_BUF_DATA_FORMAT_8_8,
3380                          V_008F0C_BUF_DATA_FORMAT_INVALID, V_008F0C_BUF_DATA_FORMAT_8_8_8_8}[num_channels - 1];
3381    case V_008F0C_BUF_DATA_FORMAT_16:
3382       return (uint8_t[]){V_008F0C_BUF_DATA_FORMAT_16, V_008F0C_BUF_DATA_FORMAT_16_16,
3383                          V_008F0C_BUF_DATA_FORMAT_INVALID, V_008F0C_BUF_DATA_FORMAT_16_16_16_16}[num_channels - 1];
3384    case V_008F0C_BUF_DATA_FORMAT_32:
3385       return (uint8_t[]){V_008F0C_BUF_DATA_FORMAT_32, V_008F0C_BUF_DATA_FORMAT_32_32,
3386                          V_008F0C_BUF_DATA_FORMAT_32_32_32, V_008F0C_BUF_DATA_FORMAT_32_32_32_32}[num_channels - 1];
3387    }
3388    unreachable("shouldn't reach here");
3389    return V_008F0C_BUF_DATA_FORMAT_INVALID;
3390 }
3391
3392 /* For 2_10_10_10 formats the alpha is handled as unsigned by pre-vega HW.
3393  * so we may need to fix it up. */
3394 Temp adjust_vertex_fetch_alpha(isel_context *ctx, unsigned adjustment, Temp alpha)
3395 {
3396    Builder bld(ctx->program, ctx->block);
3397
3398    if (adjustment == RADV_ALPHA_ADJUST_SSCALED)
3399       alpha = bld.vop1(aco_opcode::v_cvt_u32_f32, bld.def(v1), alpha);
3400
3401    /* For the integer-like cases, do a natural sign extension.
3402     *
3403     * For the SNORM case, the values are 0.0, 0.333, 0.666, 1.0
3404     * and happen to contain 0, 1, 2, 3 as the two LSBs of the
3405     * exponent.
3406     */
3407    alpha = bld.vop2(aco_opcode::v_lshlrev_b32, bld.def(v1), Operand(adjustment == RADV_ALPHA_ADJUST_SNORM ? 7u : 30u), alpha);
3408    alpha = bld.vop2(aco_opcode::v_ashrrev_i32, bld.def(v1), Operand(30u), alpha);
3409
3410    /* Convert back to the right type. */
3411    if (adjustment == RADV_ALPHA_ADJUST_SNORM) {
3412       alpha = bld.vop1(aco_opcode::v_cvt_f32_i32, bld.def(v1), alpha);
3413       Temp clamp = bld.vopc(aco_opcode::v_cmp_le_f32, bld.hint_vcc(bld.def(bld.lm)), Operand(0xbf800000u), alpha);
3414       alpha = bld.vop2(aco_opcode::v_cndmask_b32, bld.def(v1), Operand(0xbf800000u), alpha, clamp);
3415    } else if (adjustment == RADV_ALPHA_ADJUST_SSCALED) {
3416       alpha = bld.vop1(aco_opcode::v_cvt_f32_i32, bld.def(v1), alpha);
3417    }
3418
3419    return alpha;
3420 }
3421
3422 void visit_load_input(isel_context *ctx, nir_intrinsic_instr *instr)
3423 {
3424    Builder bld(ctx->program, ctx->block);
3425    Temp dst = get_ssa_temp(ctx, &instr->dest.ssa);
3426    if (ctx->shader->info.stage == MESA_SHADER_VERTEX) {
3427
3428       nir_instr *off_instr = instr->src[0].ssa->parent_instr;
3429       if (off_instr->type != nir_instr_type_load_const) {
3430          fprintf(stderr, "Unimplemented nir_intrinsic_load_input offset\n");
3431          nir_print_instr(off_instr, stderr);
3432          fprintf(stderr, "\n");
3433       }
3434       uint32_t offset = nir_instr_as_load_const(off_instr)->value[0].u32;
3435
3436       Temp vertex_buffers = convert_pointer_to_64_bit(ctx, get_arg(ctx, ctx->args->vertex_buffers));
3437
3438       unsigned location = nir_intrinsic_base(instr) / 4 - VERT_ATTRIB_GENERIC0 + offset;
3439       unsigned component = nir_intrinsic_component(instr);
3440       unsigned attrib_binding = ctx->options->key.vs.vertex_attribute_bindings[location];
3441       uint32_t attrib_offset = ctx->options->key.vs.vertex_attribute_offsets[location];
3442       uint32_t attrib_stride = ctx->options->key.vs.vertex_attribute_strides[location];
3443       unsigned attrib_format = ctx->options->key.vs.vertex_attribute_formats[location];
3444
3445       unsigned dfmt = attrib_format & 0xf;
3446       unsigned nfmt = (attrib_format >> 4) & 0x7;
3447       const struct ac_data_format_info *vtx_info = ac_get_data_format_info(dfmt);
3448
3449       unsigned mask = nir_ssa_def_components_read(&instr->dest.ssa) << component;
3450       unsigned num_channels = MIN2(util_last_bit(mask), vtx_info->num_channels);
3451       unsigned alpha_adjust = (ctx->options->key.vs.alpha_adjust >> (location * 2)) & 3;
3452       bool post_shuffle = ctx->options->key.vs.post_shuffle & (1 << location);
3453       if (post_shuffle)
3454          num_channels = MAX2(num_channels, 3);
3455
3456       Operand off = bld.copy(bld.def(s1), Operand(attrib_binding * 16u));
3457       Temp list = bld.smem(aco_opcode::s_load_dwordx4, bld.def(s4), vertex_buffers, off);
3458
3459       Temp index;
3460       if (ctx->options->key.vs.instance_rate_inputs & (1u << location)) {
3461          uint32_t divisor = ctx->options->key.vs.instance_rate_divisors[location];
3462          Temp start_instance = get_arg(ctx, ctx->args->ac.start_instance);
3463          if (divisor) {
3464             Temp instance_id = get_arg(ctx, ctx->args->ac.instance_id);
3465             if (divisor != 1) {
3466                Temp divided = bld.tmp(v1);
3467                emit_v_div_u32(ctx, divided, as_vgpr(ctx, instance_id), divisor);
3468                index = bld.vadd32(bld.def(v1), start_instance, divided);
3469             } else {
3470                index = bld.vadd32(bld.def(v1), start_instance, instance_id);
3471             }
3472          } else {
3473             index = bld.vop1(aco_opcode::v_mov_b32, bld.def(v1), start_instance);
3474          }
3475       } else {
3476          index = bld.vadd32(bld.def(v1),
3477                             get_arg(ctx, ctx->args->ac.base_vertex),
3478                             get_arg(ctx, ctx->args->ac.vertex_id));
3479       }
3480
3481       Temp channels[num_channels];
3482       unsigned channel_start = 0;
3483       bool direct_fetch = false;
3484
3485       /* skip unused channels at the start */
3486       if (vtx_info->chan_byte_size && !post_shuffle) {
3487          channel_start = ffs(mask) - 1;
3488          for (unsigned i = 0; i < channel_start; i++)
3489             channels[i] = Temp(0, s1);
3490       } else if (vtx_info->chan_byte_size && post_shuffle && !(mask & 0x8)) {
3491          num_channels = 3 - (ffs(mask) - 1);
3492       }
3493
3494       /* load channels */
3495       while (channel_start < num_channels) {
3496          unsigned fetch_size = num_channels - channel_start;
3497          unsigned fetch_offset = attrib_offset + channel_start * vtx_info->chan_byte_size;
3498          bool expanded = false;
3499
3500          /* use MUBUF when possible to avoid possible alignment issues */
3501          /* TODO: we could use SDWA to unpack 8/16-bit attributes without extra instructions */
3502          bool use_mubuf = (nfmt == V_008F0C_BUF_NUM_FORMAT_FLOAT ||
3503                            nfmt == V_008F0C_BUF_NUM_FORMAT_UINT ||
3504                            nfmt == V_008F0C_BUF_NUM_FORMAT_SINT) &&
3505                           vtx_info->chan_byte_size == 4;
3506          unsigned fetch_dfmt = V_008F0C_BUF_DATA_FORMAT_INVALID;
3507          if (!use_mubuf) {
3508             fetch_dfmt = get_fetch_data_format(ctx, vtx_info, fetch_offset, attrib_stride, &fetch_size);
3509          } else {
3510             if (fetch_size == 3 && ctx->options->chip_class == GFX6) {
3511                /* GFX6 only supports loading vec3 with MTBUF, expand to vec4. */
3512                fetch_size = 4;
3513                expanded = true;
3514             }
3515          }
3516
3517          Temp fetch_index = index;
3518          if (attrib_stride != 0 && fetch_offset > attrib_stride) {
3519             fetch_index = bld.vadd32(bld.def(v1), Operand(fetch_offset / attrib_stride), fetch_index);
3520             fetch_offset = fetch_offset % attrib_stride;
3521          }
3522
3523          Operand soffset(0u);
3524          if (fetch_offset >= 4096) {
3525             soffset = bld.copy(bld.def(s1), Operand(fetch_offset / 4096 * 4096));
3526             fetch_offset %= 4096;
3527          }
3528
3529          aco_opcode opcode;
3530          switch (fetch_size) {
3531          case 1:
3532             opcode = use_mubuf ? aco_opcode::buffer_load_dword : aco_opcode::tbuffer_load_format_x;
3533             break;
3534          case 2:
3535             opcode = use_mubuf ? aco_opcode::buffer_load_dwordx2 : aco_opcode::tbuffer_load_format_xy;
3536             break;
3537          case 3:
3538             assert(ctx->options->chip_class >= GFX7 ||
3539                    (!use_mubuf && ctx->options->chip_class == GFX6));
3540             opcode = use_mubuf ? aco_opcode::buffer_load_dwordx3 : aco_opcode::tbuffer_load_format_xyz;
3541             break;
3542          case 4:
3543             opcode = use_mubuf ? aco_opcode::buffer_load_dwordx4 : aco_opcode::tbuffer_load_format_xyzw;
3544             break;
3545          default:
3546             unreachable("Unimplemented load_input vector size");
3547          }
3548
3549          Temp fetch_dst;
3550          if (channel_start == 0 && fetch_size == dst.size() && !post_shuffle &&
3551              !expanded && (alpha_adjust == RADV_ALPHA_ADJUST_NONE ||
3552                            num_channels <= 3)) {
3553             direct_fetch = true;
3554             fetch_dst = dst;
3555          } else {
3556             fetch_dst = bld.tmp(RegType::vgpr, fetch_size);
3557          }
3558
3559          if (use_mubuf) {
3560             Instruction *mubuf = bld.mubuf(opcode,
3561                                            Definition(fetch_dst), list, fetch_index, soffset,
3562                                            fetch_offset, false, true).instr;
3563             static_cast<MUBUF_instruction*>(mubuf)->can_reorder = true;
3564          } else {
3565             Instruction *mtbuf = bld.mtbuf(opcode,
3566                                            Definition(fetch_dst), list, fetch_index, soffset,
3567                                            fetch_dfmt, nfmt, fetch_offset, false, true).instr;
3568             static_cast<MTBUF_instruction*>(mtbuf)->can_reorder = true;
3569          }
3570
3571          emit_split_vector(ctx, fetch_dst, fetch_dst.size());
3572
3573          if (fetch_size == 1) {
3574             channels[channel_start] = fetch_dst;
3575          } else {
3576             for (unsigned i = 0; i < MIN2(fetch_size, num_channels - channel_start); i++)
3577                channels[channel_start + i] = emit_extract_vector(ctx, fetch_dst, i, v1);
3578          }
3579
3580          channel_start += fetch_size;
3581       }
3582
3583       if (!direct_fetch) {
3584          bool is_float = nfmt != V_008F0C_BUF_NUM_FORMAT_UINT &&
3585                          nfmt != V_008F0C_BUF_NUM_FORMAT_SINT;
3586
3587          static const unsigned swizzle_normal[4] = {0, 1, 2, 3};
3588          static const unsigned swizzle_post_shuffle[4] = {2, 1, 0, 3};
3589          const unsigned *swizzle = post_shuffle ? swizzle_post_shuffle : swizzle_normal;
3590
3591          aco_ptr<Instruction> vec{create_instruction<Pseudo_instruction>(aco_opcode::p_create_vector, Format::PSEUDO, dst.size(), 1)};
3592          std::array<Temp,NIR_MAX_VEC_COMPONENTS> elems;
3593          unsigned num_temp = 0;
3594          for (unsigned i = 0; i < dst.size(); i++) {
3595             unsigned idx = i + component;
3596             if (swizzle[idx] < num_channels && channels[swizzle[idx]].id()) {
3597                Temp channel = channels[swizzle[idx]];
3598                if (idx == 3 && alpha_adjust != RADV_ALPHA_ADJUST_NONE)
3599                   channel = adjust_vertex_fetch_alpha(ctx, alpha_adjust, channel);
3600                vec->operands[i] = Operand(channel);
3601
3602                num_temp++;
3603                elems[i] = channel;
3604             } else if (is_float && idx == 3) {
3605                vec->operands[i] = Operand(0x3f800000u);
3606             } else if (!is_float && idx == 3) {
3607                vec->operands[i] = Operand(1u);
3608             } else {
3609                vec->operands[i] = Operand(0u);
3610             }
3611          }
3612          vec->definitions[0] = Definition(dst);
3613          ctx->block->instructions.emplace_back(std::move(vec));
3614          emit_split_vector(ctx, dst, dst.size());
3615
3616          if (num_temp == dst.size())
3617             ctx->allocated_vec.emplace(dst.id(), elems);
3618       }
3619    } else if (ctx->shader->info.stage == MESA_SHADER_FRAGMENT) {
3620       unsigned offset_idx = instr->intrinsic == nir_intrinsic_load_input ? 0 : 1;
3621       nir_instr *off_instr = instr->src[offset_idx].ssa->parent_instr;
3622       if (off_instr->type != nir_instr_type_load_const ||
3623           nir_instr_as_load_const(off_instr)->value[0].u32 != 0) {
3624          fprintf(stderr, "Unimplemented nir_intrinsic_load_input offset\n");
3625          nir_print_instr(off_instr, stderr);
3626          fprintf(stderr, "\n");
3627       }
3628
3629       Temp prim_mask = get_arg(ctx, ctx->args->ac.prim_mask);
3630       nir_const_value* offset = nir_src_as_const_value(instr->src[offset_idx]);
3631       if (offset) {
3632          assert(offset->u32 == 0);
3633       } else {
3634          /* the lower 15bit of the prim_mask contain the offset into LDS
3635           * while the upper bits contain the number of prims */
3636          Temp offset_src = get_ssa_temp(ctx, instr->src[offset_idx].ssa);
3637          assert(offset_src.regClass() == s1 && "TODO: divergent offsets...");
3638          Builder bld(ctx->program, ctx->block);
3639          Temp stride = bld.sop2(aco_opcode::s_lshr_b32, bld.def(s1), bld.def(s1, scc), prim_mask, Operand(16u));
3640          stride = bld.sop1(aco_opcode::s_bcnt1_i32_b32, bld.def(s1), bld.def(s1, scc), stride);
3641          stride = bld.sop2(aco_opcode::s_mul_i32, bld.def(s1), stride, Operand(48u));
3642          offset_src = bld.sop2(aco_opcode::s_mul_i32, bld.def(s1), stride, offset_src);
3643          prim_mask = bld.sop2(aco_opcode::s_add_i32, bld.def(s1, m0), bld.def(s1, scc), offset_src, prim_mask);
3644       }
3645
3646       unsigned idx = nir_intrinsic_base(instr);
3647       unsigned component = nir_intrinsic_component(instr);
3648       unsigned vertex_id = 2; /* P0 */
3649
3650       if (instr->intrinsic == nir_intrinsic_load_input_vertex) {
3651          nir_const_value* src0 = nir_src_as_const_value(instr->src[0]);
3652          switch (src0->u32) {
3653          case 0:
3654             vertex_id = 2; /* P0 */
3655             break;
3656          case 1:
3657             vertex_id = 0; /* P10 */
3658             break;
3659          case 2:
3660             vertex_id = 1; /* P20 */
3661             break;
3662          default:
3663             unreachable("invalid vertex index");
3664          }
3665       }
3666
3667       if (dst.size() == 1) {
3668          bld.vintrp(aco_opcode::v_interp_mov_f32, Definition(dst), Operand(vertex_id), bld.m0(prim_mask), idx, component);
3669       } else {
3670          aco_ptr<Pseudo_instruction> vec{create_instruction<Pseudo_instruction>(aco_opcode::p_create_vector, Format::PSEUDO, dst.size(), 1)};
3671          for (unsigned i = 0; i < dst.size(); i++)
3672             vec->operands[i] = bld.vintrp(aco_opcode::v_interp_mov_f32, bld.def(v1), Operand(vertex_id), bld.m0(prim_mask), idx, component + i);
3673          vec->definitions[0] = Definition(dst);
3674          bld.insert(std::move(vec));
3675       }
3676
3677    } else {
3678       unreachable("Shader stage not implemented");
3679    }
3680 }
3681
3682 std::pair<Temp, unsigned> get_gs_per_vertex_input_offset(isel_context *ctx, nir_intrinsic_instr *instr, unsigned base_stride = 1u)
3683 {
3684    assert(ctx->shader->info.stage == MESA_SHADER_GEOMETRY);
3685
3686    Builder bld(ctx->program, ctx->block);
3687    nir_src *vertex_src = nir_get_io_vertex_index_src(instr);
3688    Temp vertex_offset;
3689
3690    if (!nir_src_is_const(*vertex_src)) {
3691       /* better code could be created, but this case probably doesn't happen
3692        * much in practice */
3693       Temp indirect_vertex = as_vgpr(ctx, get_ssa_temp(ctx, vertex_src->ssa));
3694       for (unsigned i = 0; i < ctx->shader->info.gs.vertices_in; i++) {
3695          Temp elem;
3696
3697          if (ctx->stage == vertex_geometry_gs) {
3698             elem = get_arg(ctx, ctx->args->gs_vtx_offset[i / 2u * 2u]);
3699             if (i % 2u)
3700                elem = bld.vop2(aco_opcode::v_lshrrev_b32, bld.def(v1), Operand(16u), elem);
3701          } else {
3702             elem = get_arg(ctx, ctx->args->gs_vtx_offset[i]);
3703          }
3704
3705          if (vertex_offset.id()) {
3706             Temp cond = bld.vopc(aco_opcode::v_cmp_eq_u32, bld.hint_vcc(bld.def(bld.lm)),
3707                                  Operand(i), indirect_vertex);
3708             vertex_offset = bld.vop2(aco_opcode::v_cndmask_b32, bld.def(v1), vertex_offset, elem, cond);
3709          } else {
3710             vertex_offset = elem;
3711          }
3712       }
3713
3714       if (ctx->stage == vertex_geometry_gs)
3715          vertex_offset = bld.vop2(aco_opcode::v_and_b32, bld.def(v1), Operand(0xffffu), vertex_offset);
3716    } else {
3717       unsigned vertex = nir_src_as_uint(*vertex_src);
3718       if (ctx->stage == vertex_geometry_gs)
3719          vertex_offset = bld.vop3(aco_opcode::v_bfe_u32, bld.def(v1),
3720                                   get_arg(ctx, ctx->args->gs_vtx_offset[vertex / 2u * 2u]),
3721                                   Operand((vertex % 2u) * 16u), Operand(16u));
3722       else
3723          vertex_offset = get_arg(ctx, ctx->args->gs_vtx_offset[vertex]);
3724    }
3725
3726    std::pair<Temp, unsigned> offs = get_intrinsic_io_basic_offset(ctx, instr, base_stride);
3727    offs = offset_add(ctx, offs, std::make_pair(vertex_offset, 0u));
3728    return offset_mul(ctx, offs, 4u);
3729 }
3730
3731 void visit_load_gs_per_vertex_input(isel_context *ctx, nir_intrinsic_instr *instr)
3732 {
3733    assert(ctx->shader->info.stage == MESA_SHADER_GEOMETRY);
3734
3735    Builder bld(ctx->program, ctx->block);
3736    Temp dst = get_ssa_temp(ctx, &instr->dest.ssa);
3737    unsigned elem_size_bytes = instr->dest.ssa.bit_size / 8;
3738
3739    if (ctx->stage == geometry_gs) {
3740       std::pair<Temp, unsigned> offs = get_gs_per_vertex_input_offset(ctx, instr, ctx->program->wave_size);
3741       Temp ring = bld.smem(aco_opcode::s_load_dwordx4, bld.def(s4), ctx->program->private_segment_buffer, Operand(RING_ESGS_GS * 16u));
3742       load_vmem_mubuf(ctx, dst, ring, offs.first, Temp(), offs.second, elem_size_bytes, instr->dest.ssa.num_components, 4u * ctx->program->wave_size, false, true);
3743    } else if (ctx->stage == vertex_geometry_gs) {
3744       std::pair<Temp, unsigned> offs = get_gs_per_vertex_input_offset(ctx, instr);
3745       unsigned lds_align = calculate_lds_alignment(ctx, offs.second);
3746       load_lds(ctx, elem_size_bytes, dst, offs.first, offs.second, lds_align);
3747    } else {
3748       unreachable("Unsupported GS stage.");
3749    }
3750 }
3751
3752 void visit_load_per_vertex_input(isel_context *ctx, nir_intrinsic_instr *instr)
3753 {
3754    switch (ctx->shader->info.stage) {
3755    case MESA_SHADER_GEOMETRY:
3756       visit_load_gs_per_vertex_input(ctx, instr);
3757       break;
3758    default:
3759       unreachable("Unimplemented shader stage");
3760    }
3761 }
3762
3763 void visit_load_tess_coord(isel_context *ctx, nir_intrinsic_instr *instr)
3764 {
3765    assert(ctx->shader->info.stage == MESA_SHADER_TESS_EVAL);
3766
3767    Builder bld(ctx->program, ctx->block);
3768    Temp dst = get_ssa_temp(ctx, &instr->dest.ssa);
3769
3770    Operand tes_u(get_arg(ctx, ctx->args->tes_u));
3771    Operand tes_v(get_arg(ctx, ctx->args->tes_v));
3772    Operand tes_w(0u);
3773
3774    if (ctx->shader->info.tess.primitive_mode == GL_TRIANGLES) {
3775       Temp tmp = bld.vop2(aco_opcode::v_add_f32, bld.def(v1), tes_u, tes_v);
3776       tmp = bld.vop2(aco_opcode::v_sub_f32, bld.def(v1), Operand(0x3f800000u /* 1.0f */), tmp);
3777       tes_w = Operand(tmp);
3778    }
3779
3780    Temp tess_coord = bld.pseudo(aco_opcode::p_create_vector, Definition(dst), tes_u, tes_v, tes_w);
3781    emit_split_vector(ctx, tess_coord, 3);
3782 }
3783
3784 Temp load_desc_ptr(isel_context *ctx, unsigned desc_set)
3785 {
3786    if (ctx->program->info->need_indirect_descriptor_sets) {
3787       Builder bld(ctx->program, ctx->block);
3788       Temp ptr64 = convert_pointer_to_64_bit(ctx, get_arg(ctx, ctx->args->descriptor_sets[0]));
3789       Operand off = bld.copy(bld.def(s1), Operand(desc_set << 2));
3790       return bld.smem(aco_opcode::s_load_dword, bld.def(s1), ptr64, off);//, false, false, false);
3791    }
3792
3793    return get_arg(ctx, ctx->args->descriptor_sets[desc_set]);
3794 }
3795
3796
3797 void visit_load_resource(isel_context *ctx, nir_intrinsic_instr *instr)
3798 {
3799    Builder bld(ctx->program, ctx->block);
3800    Temp index = get_ssa_temp(ctx, instr->src[0].ssa);
3801    if (!ctx->divergent_vals[instr->dest.ssa.index])
3802       index = bld.as_uniform(index);
3803    unsigned desc_set = nir_intrinsic_desc_set(instr);
3804    unsigned binding = nir_intrinsic_binding(instr);
3805
3806    Temp desc_ptr;
3807    radv_pipeline_layout *pipeline_layout = ctx->options->layout;
3808    radv_descriptor_set_layout *layout = pipeline_layout->set[desc_set].layout;
3809    unsigned offset = layout->binding[binding].offset;
3810    unsigned stride;
3811    if (layout->binding[binding].type == VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER_DYNAMIC ||
3812        layout->binding[binding].type == VK_DESCRIPTOR_TYPE_STORAGE_BUFFER_DYNAMIC) {
3813       unsigned idx = pipeline_layout->set[desc_set].dynamic_offset_start + layout->binding[binding].dynamic_offset_offset;
3814       desc_ptr = get_arg(ctx, ctx->args->ac.push_constants);
3815       offset = pipeline_layout->push_constant_size + 16 * idx;
3816       stride = 16;
3817    } else {
3818       desc_ptr = load_desc_ptr(ctx, desc_set);
3819       stride = layout->binding[binding].size;
3820    }
3821
3822    nir_const_value* nir_const_index = nir_src_as_const_value(instr->src[0]);
3823    unsigned const_index = nir_const_index ? nir_const_index->u32 : 0;
3824    if (stride != 1) {
3825       if (nir_const_index) {
3826          const_index = const_index * stride;
3827       } else if (index.type() == RegType::vgpr) {
3828          bool index24bit = layout->binding[binding].array_size <= 0x1000000;
3829          index = bld.v_mul_imm(bld.def(v1), index, stride, index24bit);
3830       } else {
3831          index = bld.sop2(aco_opcode::s_mul_i32, bld.def(s1), Operand(stride), Operand(index));
3832       }
3833    }
3834    if (offset) {
3835       if (nir_const_index) {
3836          const_index = const_index + offset;
3837       } else if (index.type() == RegType::vgpr) {
3838          index = bld.vadd32(bld.def(v1), Operand(offset), index);
3839       } else {
3840          index = bld.sop2(aco_opcode::s_add_i32, bld.def(s1), bld.def(s1, scc), Operand(offset), Operand(index));
3841       }
3842    }
3843
3844    if (nir_const_index && const_index == 0) {
3845       index = desc_ptr;
3846    } else if (index.type() == RegType::vgpr) {
3847       index = bld.vadd32(bld.def(v1),
3848                          nir_const_index ? Operand(const_index) : Operand(index),
3849                          Operand(desc_ptr));
3850    } else {
3851       index = bld.sop2(aco_opcode::s_add_i32, bld.def(s1), bld.def(s1, scc),
3852                        nir_const_index ? Operand(const_index) : Operand(index),
3853                        Operand(desc_ptr));
3854    }
3855
3856    bld.copy(Definition(get_ssa_temp(ctx, &instr->dest.ssa)), index);
3857 }
3858
3859 void load_buffer(isel_context *ctx, unsigned num_components, Temp dst,
3860                  Temp rsrc, Temp offset, bool glc=false, bool readonly=true)
3861 {
3862    Builder bld(ctx->program, ctx->block);
3863
3864    unsigned num_bytes = dst.size() * 4;
3865    bool dlc = glc && ctx->options->chip_class >= GFX10;
3866
3867    aco_opcode op;
3868    if (dst.type() == RegType::vgpr || (ctx->options->chip_class < GFX8 && !readonly)) {
3869       Operand vaddr = offset.type() == RegType::vgpr ? Operand(offset) : Operand(v1);
3870       Operand soffset = offset.type() == RegType::sgpr ? Operand(offset) : Operand((uint32_t) 0);
3871       unsigned const_offset = 0;
3872
3873       Temp lower = Temp();
3874       if (num_bytes > 16) {
3875          assert(num_components == 3 || num_components == 4);
3876          op = aco_opcode::buffer_load_dwordx4;
3877          lower = bld.tmp(v4);
3878          aco_ptr<MUBUF_instruction> mubuf{create_instruction<MUBUF_instruction>(op, Format::MUBUF, 3, 1)};
3879          mubuf->definitions[0] = Definition(lower);
3880          mubuf->operands[0] = Operand(rsrc);
3881          mubuf->operands[1] = vaddr;
3882          mubuf->operands[2] = soffset;
3883          mubuf->offen = (offset.type() == RegType::vgpr);
3884          mubuf->glc = glc;
3885          mubuf->dlc = dlc;
3886          mubuf->barrier = readonly ? barrier_none : barrier_buffer;
3887          mubuf->can_reorder = readonly;
3888          bld.insert(std::move(mubuf));
3889          emit_split_vector(ctx, lower, 2);
3890          num_bytes -= 16;
3891          const_offset = 16;
3892       } else if (num_bytes == 12 && ctx->options->chip_class == GFX6) {
3893          /* GFX6 doesn't support loading vec3, expand to vec4. */
3894          num_bytes = 16;
3895       }
3896
3897       switch (num_bytes) {
3898          case 4:
3899             op = aco_opcode::buffer_load_dword;
3900             break;
3901          case 8:
3902             op = aco_opcode::buffer_load_dwordx2;
3903             break;
3904          case 12:
3905             assert(ctx->options->chip_class > GFX6);
3906             op = aco_opcode::buffer_load_dwordx3;
3907             break;
3908          case 16:
3909             op = aco_opcode::buffer_load_dwordx4;
3910             break;
3911          default:
3912             unreachable("Load SSBO not implemented for this size.");
3913       }
3914       aco_ptr<MUBUF_instruction> mubuf{create_instruction<MUBUF_instruction>(op, Format::MUBUF, 3, 1)};
3915       mubuf->operands[0] = Operand(rsrc);
3916       mubuf->operands[1] = vaddr;
3917       mubuf->operands[2] = soffset;
3918       mubuf->offen = (offset.type() == RegType::vgpr);
3919       mubuf->glc = glc;
3920       mubuf->dlc = dlc;
3921       mubuf->barrier = readonly ? barrier_none : barrier_buffer;
3922       mubuf->can_reorder = readonly;
3923       mubuf->offset = const_offset;
3924       aco_ptr<Instruction> instr = std::move(mubuf);
3925
3926       if (dst.size() > 4) {
3927          assert(lower != Temp());
3928          Temp upper = bld.tmp(RegType::vgpr, dst.size() - lower.size());
3929          instr->definitions[0] = Definition(upper);
3930          bld.insert(std::move(instr));
3931          if (dst.size() == 8)
3932             emit_split_vector(ctx, upper, 2);
3933          instr.reset(create_instruction<Pseudo_instruction>(aco_opcode::p_create_vector, Format::PSEUDO, dst.size() / 2, 1));
3934          instr->operands[0] = Operand(emit_extract_vector(ctx, lower, 0, v2));
3935          instr->operands[1] = Operand(emit_extract_vector(ctx, lower, 1, v2));
3936          instr->operands[2] = Operand(emit_extract_vector(ctx, upper, 0, v2));
3937          if (dst.size() == 8)
3938             instr->operands[3] = Operand(emit_extract_vector(ctx, upper, 1, v2));
3939       } else if (dst.size() == 3 && ctx->options->chip_class == GFX6) {
3940          Temp vec = bld.tmp(v4);
3941          instr->definitions[0] = Definition(vec);
3942          bld.insert(std::move(instr));
3943          emit_split_vector(ctx, vec, 4);
3944
3945          instr.reset(create_instruction<Pseudo_instruction>(aco_opcode::p_create_vector, Format::PSEUDO, 3, 1));
3946          instr->operands[0] = Operand(emit_extract_vector(ctx, vec, 0, v1));
3947          instr->operands[1] = Operand(emit_extract_vector(ctx, vec, 1, v1));
3948          instr->operands[2] = Operand(emit_extract_vector(ctx, vec, 2, v1));
3949       }
3950
3951       if (dst.type() == RegType::sgpr) {
3952          Temp vec = bld.tmp(RegType::vgpr, dst.size());
3953          instr->definitions[0] = Definition(vec);
3954          bld.insert(std::move(instr));
3955          expand_vector(ctx, vec, dst, num_components, (1 << num_components) - 1);
3956       } else {
3957          instr->definitions[0] = Definition(dst);
3958          bld.insert(std::move(instr));
3959          emit_split_vector(ctx, dst, num_components);
3960       }
3961    } else {
3962       switch (num_bytes) {
3963          case 4:
3964             op = aco_opcode::s_buffer_load_dword;
3965             break;
3966          case 8:
3967             op = aco_opcode::s_buffer_load_dwordx2;
3968             break;
3969          case 12:
3970          case 16:
3971             op = aco_opcode::s_buffer_load_dwordx4;
3972             break;
3973          case 24:
3974          case 32:
3975             op = aco_opcode::s_buffer_load_dwordx8;
3976             break;
3977          default:
3978             unreachable("Load SSBO not implemented for this size.");
3979       }
3980       aco_ptr<SMEM_instruction> load{create_instruction<SMEM_instruction>(op, Format::SMEM, 2, 1)};
3981       load->operands[0] = Operand(rsrc);
3982       load->operands[1] = Operand(bld.as_uniform(offset));
3983       assert(load->operands[1].getTemp().type() == RegType::sgpr);
3984       load->definitions[0] = Definition(dst);
3985       load->glc = glc;
3986       load->dlc = dlc;
3987       load->barrier = readonly ? barrier_none : barrier_buffer;
3988       load->can_reorder = false; // FIXME: currently, it doesn't seem beneficial due to how our scheduler works
3989       assert(ctx->options->chip_class >= GFX8 || !glc);
3990
3991       /* trim vector */
3992       if (dst.size() == 3) {
3993          Temp vec = bld.tmp(s4);
3994          load->definitions[0] = Definition(vec);
3995          bld.insert(std::move(load));
3996          emit_split_vector(ctx, vec, 4);
3997
3998          bld.pseudo(aco_opcode::p_create_vector, Definition(dst),
3999                     emit_extract_vector(ctx, vec, 0, s1),
4000                     emit_extract_vector(ctx, vec, 1, s1),
4001                     emit_extract_vector(ctx, vec, 2, s1));
4002       } else if (dst.size() == 6) {
4003          Temp vec = bld.tmp(s8);
4004          load->definitions[0] = Definition(vec);
4005          bld.insert(std::move(load));
4006          emit_split_vector(ctx, vec, 4);
4007
4008          bld.pseudo(aco_opcode::p_create_vector, Definition(dst),
4009                     emit_extract_vector(ctx, vec, 0, s2),
4010                     emit_extract_vector(ctx, vec, 1, s2),
4011                     emit_extract_vector(ctx, vec, 2, s2));
4012       } else {
4013          bld.insert(std::move(load));
4014       }
4015       emit_split_vector(ctx, dst, num_components);
4016    }
4017 }
4018
4019 void visit_load_ubo(isel_context *ctx, nir_intrinsic_instr *instr)
4020 {
4021    Temp dst = get_ssa_temp(ctx, &instr->dest.ssa);
4022    Temp rsrc = get_ssa_temp(ctx, instr->src[0].ssa);
4023
4024    Builder bld(ctx->program, ctx->block);
4025
4026    nir_intrinsic_instr* idx_instr = nir_instr_as_intrinsic(instr->src[0].ssa->parent_instr);
4027    unsigned desc_set = nir_intrinsic_desc_set(idx_instr);
4028    unsigned binding = nir_intrinsic_binding(idx_instr);
4029    radv_descriptor_set_layout *layout = ctx->options->layout->set[desc_set].layout;
4030
4031    if (layout->binding[binding].type == VK_DESCRIPTOR_TYPE_INLINE_UNIFORM_BLOCK_EXT) {
4032       uint32_t desc_type = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
4033                            S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
4034                            S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
4035                            S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W);
4036       if (ctx->options->chip_class >= GFX10) {
4037          desc_type |= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_FLOAT) |
4038                       S_008F0C_OOB_SELECT(V_008F0C_OOB_SELECT_RAW) |
4039                       S_008F0C_RESOURCE_LEVEL(1);
4040       } else {
4041          desc_type |= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
4042                       S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32);
4043       }
4044       Temp upper_dwords = bld.pseudo(aco_opcode::p_create_vector, bld.def(s3),
4045                                      Operand(S_008F04_BASE_ADDRESS_HI(ctx->options->address32_hi)),
4046                                      Operand(0xFFFFFFFFu),
4047                                      Operand(desc_type));
4048       rsrc = bld.pseudo(aco_opcode::p_create_vector, bld.def(s4),
4049                         rsrc, upper_dwords);
4050    } else {
4051       rsrc = convert_pointer_to_64_bit(ctx, rsrc);
4052       rsrc = bld.smem(aco_opcode::s_load_dwordx4, bld.def(s4), rsrc, Operand(0u));
4053    }
4054
4055    load_buffer(ctx, instr->num_components, dst, rsrc, get_ssa_temp(ctx, instr->src[1].ssa));
4056 }
4057
4058 void visit_load_push_constant(isel_context *ctx, nir_intrinsic_instr *instr)
4059 {
4060    Builder bld(ctx->program, ctx->block);
4061    Temp dst = get_ssa_temp(ctx, &instr->dest.ssa);
4062
4063    unsigned offset = nir_intrinsic_base(instr);
4064    nir_const_value *index_cv = nir_src_as_const_value(instr->src[0]);
4065    if (index_cv && instr->dest.ssa.bit_size == 32) {
4066
4067       unsigned count = instr->dest.ssa.num_components;
4068       unsigned start = (offset + index_cv->u32) / 4u;
4069       start -= ctx->args->ac.base_inline_push_consts;
4070       if (start + count <= ctx->args->ac.num_inline_push_consts) {
4071          std::array<Temp,NIR_MAX_VEC_COMPONENTS> elems;
4072          aco_ptr<Pseudo_instruction> vec{create_instruction<Pseudo_instruction>(aco_opcode::p_create_vector, Format::PSEUDO, count, 1)};
4073          for (unsigned i = 0; i < count; ++i) {
4074             elems[i] = get_arg(ctx, ctx->args->ac.inline_push_consts[start + i]);
4075             vec->operands[i] = Operand{elems[i]};
4076          }
4077          vec->definitions[0] = Definition(dst);
4078          ctx->block->instructions.emplace_back(std::move(vec));
4079          ctx->allocated_vec.emplace(dst.id(), elems);
4080          return;
4081       }
4082    }
4083
4084    Temp index = bld.as_uniform(get_ssa_temp(ctx, instr->src[0].ssa));
4085    if (offset != 0) // TODO check if index != 0 as well
4086       index = bld.sop2(aco_opcode::s_add_i32, bld.def(s1), bld.def(s1, scc), Operand(offset), index);
4087    Temp ptr = convert_pointer_to_64_bit(ctx, get_arg(ctx, ctx->args->ac.push_constants));
4088    Temp vec = dst;
4089    bool trim = false;
4090    aco_opcode op;
4091
4092    switch (dst.size()) {
4093    case 1:
4094       op = aco_opcode::s_load_dword;
4095       break;
4096    case 2:
4097       op = aco_opcode::s_load_dwordx2;
4098       break;
4099    case 3:
4100       vec = bld.tmp(s4);
4101       trim = true;
4102    case 4:
4103       op = aco_opcode::s_load_dwordx4;
4104       break;
4105    case 6:
4106       vec = bld.tmp(s8);
4107       trim = true;
4108    case 8:
4109       op = aco_opcode::s_load_dwordx8;
4110       break;
4111    default:
4112       unreachable("unimplemented or forbidden load_push_constant.");
4113    }
4114
4115    bld.smem(op, Definition(vec), ptr, index);
4116
4117    if (trim) {
4118       emit_split_vector(ctx, vec, 4);
4119       RegClass rc = dst.size() == 3 ? s1 : s2;
4120       bld.pseudo(aco_opcode::p_create_vector, Definition(dst),
4121                  emit_extract_vector(ctx, vec, 0, rc),
4122                  emit_extract_vector(ctx, vec, 1, rc),
4123                  emit_extract_vector(ctx, vec, 2, rc));
4124
4125    }
4126    emit_split_vector(ctx, dst, instr->dest.ssa.num_components);
4127 }
4128
4129 void visit_load_constant(isel_context *ctx, nir_intrinsic_instr *instr)
4130 {
4131    Temp dst = get_ssa_temp(ctx, &instr->dest.ssa);
4132
4133    Builder bld(ctx->program, ctx->block);
4134
4135    uint32_t desc_type = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
4136                         S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
4137                         S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
4138                         S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W);
4139    if (ctx->options->chip_class >= GFX10) {
4140       desc_type |= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_FLOAT) |
4141                    S_008F0C_OOB_SELECT(V_008F0C_OOB_SELECT_RAW) |
4142                    S_008F0C_RESOURCE_LEVEL(1);
4143    } else {
4144       desc_type |= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
4145                    S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32);
4146    }
4147
4148    unsigned base = nir_intrinsic_base(instr);
4149    unsigned range = nir_intrinsic_range(instr);
4150
4151    Temp offset = get_ssa_temp(ctx, instr->src[0].ssa);
4152    if (base && offset.type() == RegType::sgpr)
4153       offset = bld.sop2(aco_opcode::s_add_u32, bld.def(s1), bld.def(s1, scc), offset, Operand(base));
4154    else if (base && offset.type() == RegType::vgpr)
4155       offset = bld.vadd32(bld.def(v1), Operand(base), offset);
4156
4157    Temp rsrc = bld.pseudo(aco_opcode::p_create_vector, bld.def(s4),
4158                           bld.sop1(aco_opcode::p_constaddr, bld.def(s2), bld.def(s1, scc), Operand(ctx->constant_data_offset)),
4159                           Operand(MIN2(base + range, ctx->shader->constant_data_size)),
4160                           Operand(desc_type));
4161
4162    load_buffer(ctx, instr->num_components, dst, rsrc, offset);
4163 }
4164
4165 void visit_discard_if(isel_context *ctx, nir_intrinsic_instr *instr)
4166 {
4167    if (ctx->cf_info.loop_nest_depth || ctx->cf_info.parent_if.is_divergent)
4168       ctx->cf_info.exec_potentially_empty_discard = true;
4169
4170    ctx->program->needs_exact = true;
4171
4172    // TODO: optimize uniform conditions
4173    Builder bld(ctx->program, ctx->block);
4174    Temp src = get_ssa_temp(ctx, instr->src[0].ssa);
4175    assert(src.regClass() == bld.lm);
4176    src = bld.sop2(Builder::s_and, bld.def(bld.lm), bld.def(s1, scc), src, Operand(exec, bld.lm));
4177    bld.pseudo(aco_opcode::p_discard_if, src);
4178    ctx->block->kind |= block_kind_uses_discard_if;
4179    return;
4180 }
4181
4182 void visit_discard(isel_context* ctx, nir_intrinsic_instr *instr)
4183 {
4184    Builder bld(ctx->program, ctx->block);
4185
4186    if (ctx->cf_info.loop_nest_depth || ctx->cf_info.parent_if.is_divergent)
4187       ctx->cf_info.exec_potentially_empty_discard = true;
4188
4189    bool divergent = ctx->cf_info.parent_if.is_divergent ||
4190                     ctx->cf_info.parent_loop.has_divergent_continue;
4191
4192    if (ctx->block->loop_nest_depth &&
4193        ((nir_instr_is_last(&instr->instr) && !divergent) || divergent)) {
4194       /* we handle discards the same way as jump instructions */
4195       append_logical_end(ctx->block);
4196
4197       /* in loops, discard behaves like break */
4198       Block *linear_target = ctx->cf_info.parent_loop.exit;
4199       ctx->block->kind |= block_kind_discard;
4200
4201       if (!divergent) {
4202          /* uniform discard - loop ends here */
4203          assert(nir_instr_is_last(&instr->instr));
4204          ctx->block->kind |= block_kind_uniform;
4205          ctx->cf_info.has_branch = true;
4206          bld.branch(aco_opcode::p_branch);
4207          add_linear_edge(ctx->block->index, linear_target);
4208          return;
4209       }
4210
4211       /* we add a break right behind the discard() instructions */
4212       ctx->block->kind |= block_kind_break;
4213       unsigned idx = ctx->block->index;
4214
4215       /* remove critical edges from linear CFG */
4216       bld.branch(aco_opcode::p_branch);
4217       Block* break_block = ctx->program->create_and_insert_block();
4218       break_block->loop_nest_depth = ctx->cf_info.loop_nest_depth;
4219       break_block->kind |= block_kind_uniform;
4220       add_linear_edge(idx, break_block);
4221       add_linear_edge(break_block->index, linear_target);
4222       bld.reset(break_block);
4223       bld.branch(aco_opcode::p_branch);
4224
4225       Block* continue_block = ctx->program->create_and_insert_block();
4226       continue_block->loop_nest_depth = ctx->cf_info.loop_nest_depth;
4227       add_linear_edge(idx, continue_block);
4228       append_logical_start(continue_block);
4229       ctx->block = continue_block;
4230
4231       return;
4232    }
4233
4234    /* it can currently happen that NIR doesn't remove the unreachable code */
4235    if (!nir_instr_is_last(&instr->instr)) {
4236       ctx->program->needs_exact = true;
4237       /* save exec somewhere temporarily so that it doesn't get
4238        * overwritten before the discard from outer exec masks */
4239       Temp cond = bld.sop2(Builder::s_and, bld.def(bld.lm), bld.def(s1, scc), Operand(0xFFFFFFFF), Operand(exec, bld.lm));
4240       bld.pseudo(aco_opcode::p_discard_if, cond);
4241       ctx->block->kind |= block_kind_uses_discard_if;
4242       return;
4243    }
4244
4245    /* This condition is incorrect for uniformly branched discards in a loop
4246     * predicated by a divergent condition, but the above code catches that case
4247     * and the discard would end up turning into a discard_if.
4248     * For example:
4249     * if (divergent) {
4250     *    while (...) {
4251     *       if (uniform) {
4252     *          discard;
4253     *       }
4254     *    }
4255     * }
4256     */
4257    if (!ctx->cf_info.parent_if.is_divergent) {
4258       /* program just ends here */
4259       ctx->block->kind |= block_kind_uniform;
4260       bld.exp(aco_opcode::exp, Operand(v1), Operand(v1), Operand(v1), Operand(v1),
4261               0 /* enabled mask */, 9 /* dest */,
4262               false /* compressed */, true/* done */, true /* valid mask */);
4263       bld.sopp(aco_opcode::s_endpgm);
4264       // TODO: it will potentially be followed by a branch which is dead code to sanitize NIR phis
4265    } else {
4266       ctx->block->kind |= block_kind_discard;
4267       /* branch and linear edge is added by visit_if() */
4268    }
4269 }
4270
4271 enum aco_descriptor_type {
4272    ACO_DESC_IMAGE,
4273    ACO_DESC_FMASK,
4274    ACO_DESC_SAMPLER,
4275    ACO_DESC_BUFFER,
4276    ACO_DESC_PLANE_0,
4277    ACO_DESC_PLANE_1,
4278    ACO_DESC_PLANE_2,
4279 };
4280
4281 static bool
4282 should_declare_array(isel_context *ctx, enum glsl_sampler_dim sampler_dim, bool is_array) {
4283    if (sampler_dim == GLSL_SAMPLER_DIM_BUF)
4284       return false;
4285    ac_image_dim dim = ac_get_sampler_dim(ctx->options->chip_class, sampler_dim, is_array);
4286    return dim == ac_image_cube ||
4287           dim == ac_image_1darray ||
4288           dim == ac_image_2darray ||
4289           dim == ac_image_2darraymsaa;
4290 }
4291
4292 Temp get_sampler_desc(isel_context *ctx, nir_deref_instr *deref_instr,
4293                       enum aco_descriptor_type desc_type,
4294                       const nir_tex_instr *tex_instr, bool image, bool write)
4295 {
4296 /* FIXME: we should lower the deref with some new nir_intrinsic_load_desc
4297    std::unordered_map<uint64_t, Temp>::iterator it = ctx->tex_desc.find((uint64_t) desc_type << 32 | deref_instr->dest.ssa.index);
4298    if (it != ctx->tex_desc.end())
4299       return it->second;
4300 */
4301    Temp index = Temp();
4302    bool index_set = false;
4303    unsigned constant_index = 0;
4304    unsigned descriptor_set;
4305    unsigned base_index;
4306    Builder bld(ctx->program, ctx->block);
4307
4308    if (!deref_instr) {
4309       assert(tex_instr && !image);
4310       descriptor_set = 0;
4311       base_index = tex_instr->sampler_index;
4312    } else {
4313       while(deref_instr->deref_type != nir_deref_type_var) {
4314          unsigned array_size = glsl_get_aoa_size(deref_instr->type);
4315          if (!array_size)
4316             array_size = 1;
4317
4318          assert(deref_instr->deref_type == nir_deref_type_array);
4319          nir_const_value *const_value = nir_src_as_const_value(deref_instr->arr.index);
4320          if (const_value) {
4321             constant_index += array_size * const_value->u32;
4322          } else {
4323             Temp indirect = get_ssa_temp(ctx, deref_instr->arr.index.ssa);
4324             if (indirect.type() == RegType::vgpr)
4325                indirect = bld.vop1(aco_opcode::v_readfirstlane_b32, bld.def(s1), indirect);
4326
4327             if (array_size != 1)
4328                indirect = bld.sop2(aco_opcode::s_mul_i32, bld.def(s1), Operand(array_size), indirect);
4329
4330             if (!index_set) {
4331                index = indirect;
4332                index_set = true;
4333             } else {
4334                index = bld.sop2(aco_opcode::s_add_i32, bld.def(s1), bld.def(s1, scc), index, indirect);
4335             }
4336          }
4337
4338          deref_instr = nir_src_as_deref(deref_instr->parent);
4339       }
4340       descriptor_set = deref_instr->var->data.descriptor_set;
4341       base_index = deref_instr->var->data.binding;
4342    }
4343
4344    Temp list = load_desc_ptr(ctx, descriptor_set);
4345    list = convert_pointer_to_64_bit(ctx, list);
4346
4347    struct radv_descriptor_set_layout *layout = ctx->options->layout->set[descriptor_set].layout;
4348    struct radv_descriptor_set_binding_layout *binding = layout->binding + base_index;
4349    unsigned offset = binding->offset;
4350    unsigned stride = binding->size;
4351    aco_opcode opcode;
4352    RegClass type;
4353
4354    assert(base_index < layout->binding_count);
4355
4356    switch (desc_type) {
4357    case ACO_DESC_IMAGE:
4358       type = s8;
4359       opcode = aco_opcode::s_load_dwordx8;
4360       break;
4361    case ACO_DESC_FMASK:
4362       type = s8;
4363       opcode = aco_opcode::s_load_dwordx8;
4364       offset += 32;
4365       break;
4366    case ACO_DESC_SAMPLER:
4367       type = s4;
4368       opcode = aco_opcode::s_load_dwordx4;
4369       if (binding->type == VK_DESCRIPTOR_TYPE_COMBINED_IMAGE_SAMPLER)
4370          offset += radv_combined_image_descriptor_sampler_offset(binding);
4371       break;
4372    case ACO_DESC_BUFFER:
4373       type = s4;
4374       opcode = aco_opcode::s_load_dwordx4;
4375       break;
4376    case ACO_DESC_PLANE_0:
4377    case ACO_DESC_PLANE_1:
4378       type = s8;
4379       opcode = aco_opcode::s_load_dwordx8;
4380       offset += 32 * (desc_type - ACO_DESC_PLANE_0);
4381       break;
4382    case ACO_DESC_PLANE_2:
4383       type = s4;
4384       opcode = aco_opcode::s_load_dwordx4;
4385       offset += 64;
4386       break;
4387    default:
4388       unreachable("invalid desc_type\n");
4389    }
4390
4391    offset += constant_index * stride;
4392
4393    if (desc_type == ACO_DESC_SAMPLER && binding->immutable_samplers_offset &&
4394       (!index_set || binding->immutable_samplers_equal)) {
4395       if (binding->immutable_samplers_equal)
4396          constant_index = 0;
4397
4398       const uint32_t *samplers = radv_immutable_samplers(layout, binding);
4399       return bld.pseudo(aco_opcode::p_create_vector, bld.def(s4),
4400                         Operand(samplers[constant_index * 4 + 0]),
4401                         Operand(samplers[constant_index * 4 + 1]),
4402                         Operand(samplers[constant_index * 4 + 2]),
4403                         Operand(samplers[constant_index * 4 + 3]));
4404    }
4405
4406    Operand off;
4407    if (!index_set) {
4408       off = bld.copy(bld.def(s1), Operand(offset));
4409    } else {
4410       off = Operand((Temp)bld.sop2(aco_opcode::s_add_i32, bld.def(s1), bld.def(s1, scc), Operand(offset),
4411                                    bld.sop2(aco_opcode::s_mul_i32, bld.def(s1), Operand(stride), index)));
4412    }
4413
4414    Temp res = bld.smem(opcode, bld.def(type), list, off);
4415
4416    if (desc_type == ACO_DESC_PLANE_2) {
4417       Temp components[8];
4418       for (unsigned i = 0; i < 8; i++)
4419          components[i] = bld.tmp(s1);
4420       bld.pseudo(aco_opcode::p_split_vector,
4421                  Definition(components[0]),
4422                  Definition(components[1]),
4423                  Definition(components[2]),
4424                  Definition(components[3]),
4425                  res);
4426
4427       Temp desc2 = get_sampler_desc(ctx, deref_instr, ACO_DESC_PLANE_1, tex_instr, image, write);
4428       bld.pseudo(aco_opcode::p_split_vector,
4429                  bld.def(s1), bld.def(s1), bld.def(s1), bld.def(s1),
4430                  Definition(components[4]),
4431                  Definition(components[5]),
4432                  Definition(components[6]),
4433                  Definition(components[7]),
4434                  desc2);
4435
4436       res = bld.pseudo(aco_opcode::p_create_vector, bld.def(s8),
4437                        components[0], components[1], components[2], components[3],
4438                        components[4], components[5], components[6], components[7]);
4439    }
4440
4441    return res;
4442 }
4443
4444 static int image_type_to_components_count(enum glsl_sampler_dim dim, bool array)
4445 {
4446    switch (dim) {
4447    case GLSL_SAMPLER_DIM_BUF:
4448       return 1;
4449    case GLSL_SAMPLER_DIM_1D:
4450       return array ? 2 : 1;
4451    case GLSL_SAMPLER_DIM_2D:
4452       return array ? 3 : 2;
4453    case GLSL_SAMPLER_DIM_MS:
4454       return array ? 4 : 3;
4455    case GLSL_SAMPLER_DIM_3D:
4456    case GLSL_SAMPLER_DIM_CUBE:
4457       return 3;
4458    case GLSL_SAMPLER_DIM_RECT:
4459    case GLSL_SAMPLER_DIM_SUBPASS:
4460       return 2;
4461    case GLSL_SAMPLER_DIM_SUBPASS_MS:
4462       return 3;
4463    default:
4464       break;
4465    }
4466    return 0;
4467 }
4468
4469
4470 /* Adjust the sample index according to FMASK.
4471  *
4472  * For uncompressed MSAA surfaces, FMASK should return 0x76543210,
4473  * which is the identity mapping. Each nibble says which physical sample
4474  * should be fetched to get that sample.
4475  *
4476  * For example, 0x11111100 means there are only 2 samples stored and
4477  * the second sample covers 3/4 of the pixel. When reading samples 0
4478  * and 1, return physical sample 0 (determined by the first two 0s
4479  * in FMASK), otherwise return physical sample 1.
4480  *
4481  * The sample index should be adjusted as follows:
4482  *   sample_index = (fmask >> (sample_index * 4)) & 0xF;
4483  */
4484 static Temp adjust_sample_index_using_fmask(isel_context *ctx, bool da, std::vector<Temp>& coords, Operand sample_index, Temp fmask_desc_ptr)
4485 {
4486    Builder bld(ctx->program, ctx->block);
4487    Temp fmask = bld.tmp(v1);
4488    unsigned dim = ctx->options->chip_class >= GFX10
4489                   ? ac_get_sampler_dim(ctx->options->chip_class, GLSL_SAMPLER_DIM_2D, da)
4490                   : 0;
4491
4492    Temp coord = da ? bld.pseudo(aco_opcode::p_create_vector, bld.def(v3), coords[0], coords[1], coords[2]) :
4493                      bld.pseudo(aco_opcode::p_create_vector, bld.def(v2), coords[0], coords[1]);
4494    aco_ptr<MIMG_instruction> load{create_instruction<MIMG_instruction>(aco_opcode::image_load, Format::MIMG, 3, 1)};
4495    load->operands[0] = Operand(fmask_desc_ptr);
4496    load->operands[1] = Operand(s4); /* no sampler */
4497    load->operands[2] = Operand(coord);
4498    load->definitions[0] = Definition(fmask);
4499    load->glc = false;
4500    load->dlc = false;
4501    load->dmask = 0x1;
4502    load->unrm = true;
4503    load->da = da;
4504    load->dim = dim;
4505    load->can_reorder = true; /* fmask images shouldn't be modified */
4506    ctx->block->instructions.emplace_back(std::move(load));
4507
4508    Operand sample_index4;
4509    if (sample_index.isConstant() && sample_index.constantValue() < 16) {
4510       sample_index4 = Operand(sample_index.constantValue() << 2);
4511    } else if (sample_index.regClass() == s1) {
4512       sample_index4 = bld.sop2(aco_opcode::s_lshl_b32, bld.def(s1), bld.def(s1, scc), sample_index, Operand(2u));
4513    } else {
4514       assert(sample_index.regClass() == v1);
4515       sample_index4 = bld.vop2(aco_opcode::v_lshlrev_b32, bld.def(v1), Operand(2u), sample_index);
4516    }
4517
4518    Temp final_sample;
4519    if (sample_index4.isConstant() && sample_index4.constantValue() == 0)
4520       final_sample = bld.vop2(aco_opcode::v_and_b32, bld.def(v1), Operand(15u), fmask);
4521    else if (sample_index4.isConstant() && sample_index4.constantValue() == 28)
4522       final_sample = bld.vop2(aco_opcode::v_lshrrev_b32, bld.def(v1), Operand(28u), fmask);
4523    else
4524       final_sample = bld.vop3(aco_opcode::v_bfe_u32, bld.def(v1), fmask, sample_index4, Operand(4u));
4525
4526    /* Don't rewrite the sample index if WORD1.DATA_FORMAT of the FMASK
4527     * resource descriptor is 0 (invalid),
4528     */
4529    Temp compare = bld.tmp(bld.lm);
4530    bld.vopc_e64(aco_opcode::v_cmp_lg_u32, Definition(compare),
4531                 Operand(0u), emit_extract_vector(ctx, fmask_desc_ptr, 1, s1)).def(0).setHint(vcc);
4532
4533    Temp sample_index_v = bld.vop1(aco_opcode::v_mov_b32, bld.def(v1), sample_index);
4534
4535    /* Replace the MSAA sample index. */
4536    return bld.vop2(aco_opcode::v_cndmask_b32, bld.def(v1), sample_index_v, final_sample, compare);
4537 }
4538
4539 static Temp get_image_coords(isel_context *ctx, const nir_intrinsic_instr *instr, const struct glsl_type *type)
4540 {
4541
4542    Temp src0 = get_ssa_temp(ctx, instr->src[1].ssa);
4543    enum glsl_sampler_dim dim = glsl_get_sampler_dim(type);
4544    bool is_array = glsl_sampler_type_is_array(type);
4545    ASSERTED bool add_frag_pos = (dim == GLSL_SAMPLER_DIM_SUBPASS || dim == GLSL_SAMPLER_DIM_SUBPASS_MS);
4546    assert(!add_frag_pos && "Input attachments should be lowered.");
4547    bool is_ms = (dim == GLSL_SAMPLER_DIM_MS || dim == GLSL_SAMPLER_DIM_SUBPASS_MS);
4548    bool gfx9_1d = ctx->options->chip_class == GFX9 && dim == GLSL_SAMPLER_DIM_1D;
4549    int count = image_type_to_components_count(dim, is_array);
4550    std::vector<Temp> coords(count);
4551    Builder bld(ctx->program, ctx->block);
4552
4553    if (is_ms) {
4554       count--;
4555       Temp src2 = get_ssa_temp(ctx, instr->src[2].ssa);
4556       /* get sample index */
4557       if (instr->intrinsic == nir_intrinsic_image_deref_load) {
4558          nir_const_value *sample_cv = nir_src_as_const_value(instr->src[2]);
4559          Operand sample_index = sample_cv ? Operand(sample_cv->u32) : Operand(emit_extract_vector(ctx, src2, 0, v1));
4560          std::vector<Temp> fmask_load_address;
4561          for (unsigned i = 0; i < (is_array ? 3 : 2); i++)
4562             fmask_load_address.emplace_back(emit_extract_vector(ctx, src0, i, v1));
4563
4564          Temp fmask_desc_ptr = get_sampler_desc(ctx, nir_instr_as_deref(instr->src[0].ssa->parent_instr), ACO_DESC_FMASK, nullptr, false, false);
4565          coords[count] = adjust_sample_index_using_fmask(ctx, is_array, fmask_load_address, sample_index, fmask_desc_ptr);
4566       } else {
4567          coords[count] = emit_extract_vector(ctx, src2, 0, v1);
4568       }
4569    }
4570
4571    if (gfx9_1d) {
4572       coords[0] = emit_extract_vector(ctx, src0, 0, v1);
4573       coords.resize(coords.size() + 1);
4574       coords[1] = bld.copy(bld.def(v1), Operand(0u));
4575       if (is_array)
4576          coords[2] = emit_extract_vector(ctx, src0, 1, v1);
4577    } else {
4578       for (int i = 0; i < count; i++)
4579          coords[i] = emit_extract_vector(ctx, src0, i, v1);
4580    }
4581
4582    if (instr->intrinsic == nir_intrinsic_image_deref_load ||
4583        instr->intrinsic == nir_intrinsic_image_deref_store) {
4584       int lod_index = instr->intrinsic == nir_intrinsic_image_deref_load ? 3 : 4;
4585       bool level_zero = nir_src_is_const(instr->src[lod_index]) && nir_src_as_uint(instr->src[lod_index]) == 0;
4586
4587       if (!level_zero)
4588          coords.emplace_back(get_ssa_temp(ctx, instr->src[lod_index].ssa));
4589    }
4590
4591    aco_ptr<Pseudo_instruction> vec{create_instruction<Pseudo_instruction>(aco_opcode::p_create_vector, Format::PSEUDO, coords.size(), 1)};
4592    for (unsigned i = 0; i < coords.size(); i++)
4593       vec->operands[i] = Operand(coords[i]);
4594    Temp res = {ctx->program->allocateId(), RegClass(RegType::vgpr, coords.size())};
4595    vec->definitions[0] = Definition(res);
4596    ctx->block->instructions.emplace_back(std::move(vec));
4597    return res;
4598 }
4599
4600
4601 void visit_image_load(isel_context *ctx, nir_intrinsic_instr *instr)
4602 {
4603    Builder bld(ctx->program, ctx->block);
4604    const nir_variable *var = nir_deref_instr_get_variable(nir_instr_as_deref(instr->src[0].ssa->parent_instr));
4605    const struct glsl_type *type = glsl_without_array(var->type);
4606    const enum glsl_sampler_dim dim = glsl_get_sampler_dim(type);
4607    bool is_array = glsl_sampler_type_is_array(type);
4608    Temp dst = get_ssa_temp(ctx, &instr->dest.ssa);
4609
4610    if (dim == GLSL_SAMPLER_DIM_BUF) {
4611       unsigned mask = nir_ssa_def_components_read(&instr->dest.ssa);
4612       unsigned num_channels = util_last_bit(mask);
4613       Temp rsrc = get_sampler_desc(ctx, nir_instr_as_deref(instr->src[0].ssa->parent_instr), ACO_DESC_BUFFER, nullptr, true, true);
4614       Temp vindex = emit_extract_vector(ctx, get_ssa_temp(ctx, instr->src[1].ssa), 0, v1);
4615
4616       aco_opcode opcode;
4617       switch (num_channels) {
4618       case 1:
4619          opcode = aco_opcode::buffer_load_format_x;
4620          break;
4621       case 2:
4622          opcode = aco_opcode::buffer_load_format_xy;
4623          break;
4624       case 3:
4625          opcode = aco_opcode::buffer_load_format_xyz;
4626          break;
4627       case 4:
4628          opcode = aco_opcode::buffer_load_format_xyzw;
4629          break;
4630       default:
4631          unreachable(">4 channel buffer image load");
4632       }
4633       aco_ptr<MUBUF_instruction> load{create_instruction<MUBUF_instruction>(opcode, Format::MUBUF, 3, 1)};
4634       load->operands[0] = Operand(rsrc);
4635       load->operands[1] = Operand(vindex);
4636       load->operands[2] = Operand((uint32_t) 0);
4637       Temp tmp;
4638       if (num_channels == instr->dest.ssa.num_components && dst.type() == RegType::vgpr)
4639          tmp = dst;
4640       else
4641          tmp = {ctx->program->allocateId(), RegClass(RegType::vgpr, num_channels)};
4642       load->definitions[0] = Definition(tmp);
4643       load->idxen = true;
4644       load->glc = var->data.access & (ACCESS_VOLATILE | ACCESS_COHERENT);
4645       load->dlc = load->glc && ctx->options->chip_class >= GFX10;
4646       load->barrier = barrier_image;
4647       ctx->block->instructions.emplace_back(std::move(load));
4648
4649       expand_vector(ctx, tmp, dst, instr->dest.ssa.num_components, (1 << num_channels) - 1);
4650       return;
4651    }
4652
4653    Temp coords = get_image_coords(ctx, instr, type);
4654    Temp resource = get_sampler_desc(ctx, nir_instr_as_deref(instr->src[0].ssa->parent_instr), ACO_DESC_IMAGE, nullptr, true, true);
4655
4656    unsigned dmask = nir_ssa_def_components_read(&instr->dest.ssa);
4657    unsigned num_components = util_bitcount(dmask);
4658    Temp tmp;
4659    if (num_components == instr->dest.ssa.num_components && dst.type() == RegType::vgpr)
4660       tmp = dst;
4661    else
4662       tmp = {ctx->program->allocateId(), RegClass(RegType::vgpr, num_components)};
4663
4664    bool level_zero = nir_src_is_const(instr->src[3]) && nir_src_as_uint(instr->src[3]) == 0;
4665    aco_opcode opcode = level_zero ? aco_opcode::image_load : aco_opcode::image_load_mip;
4666
4667    aco_ptr<MIMG_instruction> load{create_instruction<MIMG_instruction>(opcode, Format::MIMG, 3, 1)};
4668    load->operands[0] = Operand(resource);
4669    load->operands[1] = Operand(s4); /* no sampler */
4670    load->operands[2] = Operand(coords);
4671    load->definitions[0] = Definition(tmp);
4672    load->glc = var->data.access & (ACCESS_VOLATILE | ACCESS_COHERENT) ? 1 : 0;
4673    load->dlc = load->glc && ctx->options->chip_class >= GFX10;
4674    load->dim = ac_get_image_dim(ctx->options->chip_class, dim, is_array);
4675    load->dmask = dmask;
4676    load->unrm = true;
4677    load->da = should_declare_array(ctx, dim, glsl_sampler_type_is_array(type));
4678    load->barrier = barrier_image;
4679    ctx->block->instructions.emplace_back(std::move(load));
4680
4681    expand_vector(ctx, tmp, dst, instr->dest.ssa.num_components, dmask);
4682    return;
4683 }
4684
4685 void visit_image_store(isel_context *ctx, nir_intrinsic_instr *instr)
4686 {
4687    const nir_variable *var = nir_deref_instr_get_variable(nir_instr_as_deref(instr->src[0].ssa->parent_instr));
4688    const struct glsl_type *type = glsl_without_array(var->type);
4689    const enum glsl_sampler_dim dim = glsl_get_sampler_dim(type);
4690    bool is_array = glsl_sampler_type_is_array(type);
4691    Temp data = as_vgpr(ctx, get_ssa_temp(ctx, instr->src[3].ssa));
4692
4693    bool glc = ctx->options->chip_class == GFX6 || var->data.access & (ACCESS_VOLATILE | ACCESS_COHERENT | ACCESS_NON_READABLE) ? 1 : 0;
4694
4695    if (dim == GLSL_SAMPLER_DIM_BUF) {
4696       Temp rsrc = get_sampler_desc(ctx, nir_instr_as_deref(instr->src[0].ssa->parent_instr), ACO_DESC_BUFFER, nullptr, true, true);
4697       Temp vindex = emit_extract_vector(ctx, get_ssa_temp(ctx, instr->src[1].ssa), 0, v1);
4698       aco_opcode opcode;
4699       switch (data.size()) {
4700       case 1:
4701          opcode = aco_opcode::buffer_store_format_x;
4702          break;
4703       case 2:
4704          opcode = aco_opcode::buffer_store_format_xy;
4705          break;
4706       case 3:
4707          opcode = aco_opcode::buffer_store_format_xyz;
4708          break;
4709       case 4:
4710          opcode = aco_opcode::buffer_store_format_xyzw;
4711          break;
4712       default:
4713          unreachable(">4 channel buffer image store");
4714       }
4715       aco_ptr<MUBUF_instruction> store{create_instruction<MUBUF_instruction>(opcode, Format::MUBUF, 4, 0)};
4716       store->operands[0] = Operand(rsrc);
4717       store->operands[1] = Operand(vindex);
4718       store->operands[2] = Operand((uint32_t) 0);
4719       store->operands[3] = Operand(data);
4720       store->idxen = true;
4721       store->glc = glc;
4722       store->dlc = false;
4723       store->disable_wqm = true;
4724       store->barrier = barrier_image;
4725       ctx->program->needs_exact = true;
4726       ctx->block->instructions.emplace_back(std::move(store));
4727       return;
4728    }
4729
4730    assert(data.type() == RegType::vgpr);
4731    Temp coords = get_image_coords(ctx, instr, type);
4732    Temp resource = get_sampler_desc(ctx, nir_instr_as_deref(instr->src[0].ssa->parent_instr), ACO_DESC_IMAGE, nullptr, true, true);
4733
4734    bool level_zero = nir_src_is_const(instr->src[4]) && nir_src_as_uint(instr->src[4]) == 0;
4735    aco_opcode opcode = level_zero ? aco_opcode::image_store : aco_opcode::image_store_mip;
4736
4737    aco_ptr<MIMG_instruction> store{create_instruction<MIMG_instruction>(opcode, Format::MIMG, 3, 0)};
4738    store->operands[0] = Operand(resource);
4739    store->operands[1] = Operand(data);
4740    store->operands[2] = Operand(coords);
4741    store->glc = glc;
4742    store->dlc = false;
4743    store->dim = ac_get_image_dim(ctx->options->chip_class, dim, is_array);
4744    store->dmask = (1 << data.size()) - 1;
4745    store->unrm = true;
4746    store->da = should_declare_array(ctx, dim, glsl_sampler_type_is_array(type));
4747    store->disable_wqm = true;
4748    store->barrier = barrier_image;
4749    ctx->program->needs_exact = true;
4750    ctx->block->instructions.emplace_back(std::move(store));
4751    return;
4752 }
4753
4754 void visit_image_atomic(isel_context *ctx, nir_intrinsic_instr *instr)
4755 {
4756    /* return the previous value if dest is ever used */
4757    bool return_previous = false;
4758    nir_foreach_use_safe(use_src, &instr->dest.ssa) {
4759       return_previous = true;
4760       break;
4761    }
4762    nir_foreach_if_use_safe(use_src, &instr->dest.ssa) {
4763       return_previous = true;
4764       break;
4765    }
4766
4767    const nir_variable *var = nir_deref_instr_get_variable(nir_instr_as_deref(instr->src[0].ssa->parent_instr));
4768    const struct glsl_type *type = glsl_without_array(var->type);
4769    const enum glsl_sampler_dim dim = glsl_get_sampler_dim(type);
4770    bool is_array = glsl_sampler_type_is_array(type);
4771    Builder bld(ctx->program, ctx->block);
4772
4773    Temp data = as_vgpr(ctx, get_ssa_temp(ctx, instr->src[3].ssa));
4774    assert(data.size() == 1 && "64bit ssbo atomics not yet implemented.");
4775
4776    if (instr->intrinsic == nir_intrinsic_image_deref_atomic_comp_swap)
4777       data = bld.pseudo(aco_opcode::p_create_vector, bld.def(v2), get_ssa_temp(ctx, instr->src[4].ssa), data);
4778
4779    aco_opcode buf_op, image_op;
4780    switch (instr->intrinsic) {
4781       case nir_intrinsic_image_deref_atomic_add:
4782          buf_op = aco_opcode::buffer_atomic_add;
4783          image_op = aco_opcode::image_atomic_add;
4784          break;
4785       case nir_intrinsic_image_deref_atomic_umin:
4786          buf_op = aco_opcode::buffer_atomic_umin;
4787          image_op = aco_opcode::image_atomic_umin;
4788          break;
4789       case nir_intrinsic_image_deref_atomic_imin:
4790          buf_op = aco_opcode::buffer_atomic_smin;
4791          image_op = aco_opcode::image_atomic_smin;
4792          break;
4793       case nir_intrinsic_image_deref_atomic_umax:
4794          buf_op = aco_opcode::buffer_atomic_umax;
4795          image_op = aco_opcode::image_atomic_umax;
4796          break;
4797       case nir_intrinsic_image_deref_atomic_imax:
4798          buf_op = aco_opcode::buffer_atomic_smax;
4799          image_op = aco_opcode::image_atomic_smax;
4800          break;
4801       case nir_intrinsic_image_deref_atomic_and:
4802          buf_op = aco_opcode::buffer_atomic_and;
4803          image_op = aco_opcode::image_atomic_and;
4804          break;
4805       case nir_intrinsic_image_deref_atomic_or:
4806          buf_op = aco_opcode::buffer_atomic_or;
4807          image_op = aco_opcode::image_atomic_or;
4808          break;
4809       case nir_intrinsic_image_deref_atomic_xor:
4810          buf_op = aco_opcode::buffer_atomic_xor;
4811          image_op = aco_opcode::image_atomic_xor;
4812          break;
4813       case nir_intrinsic_image_deref_atomic_exchange:
4814          buf_op = aco_opcode::buffer_atomic_swap;
4815          image_op = aco_opcode::image_atomic_swap;
4816          break;
4817       case nir_intrinsic_image_deref_atomic_comp_swap:
4818          buf_op = aco_opcode::buffer_atomic_cmpswap;
4819          image_op = aco_opcode::image_atomic_cmpswap;
4820          break;
4821       default:
4822          unreachable("visit_image_atomic should only be called with nir_intrinsic_image_deref_atomic_* instructions.");
4823    }
4824
4825    Temp dst = get_ssa_temp(ctx, &instr->dest.ssa);
4826
4827    if (dim == GLSL_SAMPLER_DIM_BUF) {
4828       Temp vindex = emit_extract_vector(ctx, get_ssa_temp(ctx, instr->src[1].ssa), 0, v1);
4829       Temp resource = get_sampler_desc(ctx, nir_instr_as_deref(instr->src[0].ssa->parent_instr), ACO_DESC_BUFFER, nullptr, true, true);
4830       //assert(ctx->options->chip_class < GFX9 && "GFX9 stride size workaround not yet implemented.");
4831       aco_ptr<MUBUF_instruction> mubuf{create_instruction<MUBUF_instruction>(buf_op, Format::MUBUF, 4, return_previous ? 1 : 0)};
4832       mubuf->operands[0] = Operand(resource);
4833       mubuf->operands[1] = Operand(vindex);
4834       mubuf->operands[2] = Operand((uint32_t)0);
4835       mubuf->operands[3] = Operand(data);
4836       if (return_previous)
4837          mubuf->definitions[0] = Definition(dst);
4838       mubuf->offset = 0;
4839       mubuf->idxen = true;
4840       mubuf->glc = return_previous;
4841       mubuf->dlc = false; /* Not needed for atomics */
4842       mubuf->disable_wqm = true;
4843       mubuf->barrier = barrier_image;
4844       ctx->program->needs_exact = true;
4845       ctx->block->instructions.emplace_back(std::move(mubuf));
4846       return;
4847    }
4848
4849    Temp coords = get_image_coords(ctx, instr, type);
4850    Temp resource = get_sampler_desc(ctx, nir_instr_as_deref(instr->src[0].ssa->parent_instr), ACO_DESC_IMAGE, nullptr, true, true);
4851    aco_ptr<MIMG_instruction> mimg{create_instruction<MIMG_instruction>(image_op, Format::MIMG, 3, return_previous ? 1 : 0)};
4852    mimg->operands[0] = Operand(resource);
4853    mimg->operands[1] = Operand(data);
4854    mimg->operands[2] = Operand(coords);
4855    if (return_previous)
4856       mimg->definitions[0] = Definition(dst);
4857    mimg->glc = return_previous;
4858    mimg->dlc = false; /* Not needed for atomics */
4859    mimg->dim = ac_get_image_dim(ctx->options->chip_class, dim, is_array);
4860    mimg->dmask = (1 << data.size()) - 1;
4861    mimg->unrm = true;
4862    mimg->da = should_declare_array(ctx, dim, glsl_sampler_type_is_array(type));
4863    mimg->disable_wqm = true;
4864    mimg->barrier = barrier_image;
4865    ctx->program->needs_exact = true;
4866    ctx->block->instructions.emplace_back(std::move(mimg));
4867    return;
4868 }
4869
4870 void get_buffer_size(isel_context *ctx, Temp desc, Temp dst, bool in_elements)
4871 {
4872    if (in_elements && ctx->options->chip_class == GFX8) {
4873       /* we only have to divide by 1, 2, 4, 8, 12 or 16 */
4874       Builder bld(ctx->program, ctx->block);
4875
4876       Temp size = emit_extract_vector(ctx, desc, 2, s1);
4877
4878       Temp size_div3 = bld.vop3(aco_opcode::v_mul_hi_u32, bld.def(v1), bld.copy(bld.def(v1), Operand(0xaaaaaaabu)), size);
4879       size_div3 = bld.sop2(aco_opcode::s_lshr_b32, bld.def(s1), bld.as_uniform(size_div3), Operand(1u));
4880
4881       Temp stride = emit_extract_vector(ctx, desc, 1, s1);
4882       stride = bld.sop2(aco_opcode::s_bfe_u32, bld.def(s1), bld.def(s1, scc), stride, Operand((5u << 16) | 16u));
4883
4884       Temp is12 = bld.sopc(aco_opcode::s_cmp_eq_i32, bld.def(s1, scc), stride, Operand(12u));
4885       size = bld.sop2(aco_opcode::s_cselect_b32, bld.def(s1), size_div3, size, bld.scc(is12));
4886
4887       Temp shr_dst = dst.type() == RegType::vgpr ? bld.tmp(s1) : dst;
4888       bld.sop2(aco_opcode::s_lshr_b32, Definition(shr_dst), bld.def(s1, scc),
4889                size, bld.sop1(aco_opcode::s_ff1_i32_b32, bld.def(s1), stride));
4890       if (dst.type() == RegType::vgpr)
4891          bld.copy(Definition(dst), shr_dst);
4892
4893       /* TODO: we can probably calculate this faster with v_skip when stride != 12 */
4894    } else {
4895       emit_extract_vector(ctx, desc, 2, dst);
4896    }
4897 }
4898
4899 void visit_image_size(isel_context *ctx, nir_intrinsic_instr *instr)
4900 {
4901    const nir_variable *var = nir_deref_instr_get_variable(nir_instr_as_deref(instr->src[0].ssa->parent_instr));
4902    const struct glsl_type *type = glsl_without_array(var->type);
4903    const enum glsl_sampler_dim dim = glsl_get_sampler_dim(type);
4904    bool is_array = glsl_sampler_type_is_array(type);
4905    Builder bld(ctx->program, ctx->block);
4906
4907    if (glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_BUF) {
4908       Temp desc = get_sampler_desc(ctx, nir_instr_as_deref(instr->src[0].ssa->parent_instr), ACO_DESC_BUFFER, NULL, true, false);
4909       return get_buffer_size(ctx, desc, get_ssa_temp(ctx, &instr->dest.ssa), true);
4910    }
4911
4912    /* LOD */
4913    Temp lod = bld.vop1(aco_opcode::v_mov_b32, bld.def(v1), Operand(0u));
4914
4915    /* Resource */
4916    Temp resource = get_sampler_desc(ctx, nir_instr_as_deref(instr->src[0].ssa->parent_instr), ACO_DESC_IMAGE, NULL, true, false);
4917
4918    Temp dst = get_ssa_temp(ctx, &instr->dest.ssa);
4919
4920    aco_ptr<MIMG_instruction> mimg{create_instruction<MIMG_instruction>(aco_opcode::image_get_resinfo, Format::MIMG, 3, 1)};
4921    mimg->operands[0] = Operand(resource);
4922    mimg->operands[1] = Operand(s4); /* no sampler */
4923    mimg->operands[2] = Operand(lod);
4924    uint8_t& dmask = mimg->dmask;
4925    mimg->dim = ac_get_image_dim(ctx->options->chip_class, dim, is_array);
4926    mimg->dmask = (1 << instr->dest.ssa.num_components) - 1;
4927    mimg->da = glsl_sampler_type_is_array(type);
4928    mimg->can_reorder = true;
4929    Definition& def = mimg->definitions[0];
4930    ctx->block->instructions.emplace_back(std::move(mimg));
4931
4932    if (glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_CUBE &&
4933        glsl_sampler_type_is_array(type)) {
4934
4935       assert(instr->dest.ssa.num_components == 3);
4936       Temp tmp = {ctx->program->allocateId(), v3};
4937       def = Definition(tmp);
4938       emit_split_vector(ctx, tmp, 3);
4939
4940       /* divide 3rd value by 6 by multiplying with magic number */
4941       Temp c = bld.copy(bld.def(s1), Operand((uint32_t) 0x2AAAAAAB));
4942       Temp by_6 = bld.vop3(aco_opcode::v_mul_hi_i32, bld.def(v1), emit_extract_vector(ctx, tmp, 2, v1), c);
4943
4944       bld.pseudo(aco_opcode::p_create_vector, Definition(dst),
4945                  emit_extract_vector(ctx, tmp, 0, v1),
4946                  emit_extract_vector(ctx, tmp, 1, v1),
4947                  by_6);
4948
4949    } else if (ctx->options->chip_class == GFX9 &&
4950               glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_1D &&
4951               glsl_sampler_type_is_array(type)) {
4952       assert(instr->dest.ssa.num_components == 2);
4953       def = Definition(dst);
4954       dmask = 0x5;
4955    } else {
4956       def = Definition(dst);
4957    }
4958
4959    emit_split_vector(ctx, dst, instr->dest.ssa.num_components);
4960 }
4961
4962 void visit_load_ssbo(isel_context *ctx, nir_intrinsic_instr *instr)
4963 {
4964    Builder bld(ctx->program, ctx->block);
4965    unsigned num_components = instr->num_components;
4966
4967    Temp dst = get_ssa_temp(ctx, &instr->dest.ssa);
4968    Temp rsrc = convert_pointer_to_64_bit(ctx, get_ssa_temp(ctx, instr->src[0].ssa));
4969    rsrc = bld.smem(aco_opcode::s_load_dwordx4, bld.def(s4), rsrc, Operand(0u));
4970
4971    bool glc = nir_intrinsic_access(instr) & (ACCESS_VOLATILE | ACCESS_COHERENT);
4972    load_buffer(ctx, num_components, dst, rsrc, get_ssa_temp(ctx, instr->src[1].ssa), glc, false);
4973 }
4974
4975 void visit_store_ssbo(isel_context *ctx, nir_intrinsic_instr *instr)
4976 {
4977    Builder bld(ctx->program, ctx->block);
4978    Temp data = get_ssa_temp(ctx, instr->src[0].ssa);
4979    unsigned elem_size_bytes = instr->src[0].ssa->bit_size / 8;
4980    unsigned writemask = nir_intrinsic_write_mask(instr);
4981    Temp offset = get_ssa_temp(ctx, instr->src[2].ssa);
4982
4983    Temp rsrc = convert_pointer_to_64_bit(ctx, get_ssa_temp(ctx, instr->src[1].ssa));
4984    rsrc = bld.smem(aco_opcode::s_load_dwordx4, bld.def(s4), rsrc, Operand(0u));
4985
4986    bool smem = !ctx->divergent_vals[instr->src[2].ssa->index] &&
4987                ctx->options->chip_class >= GFX8;
4988    if (smem)
4989       offset = bld.as_uniform(offset);
4990    bool smem_nonfs = smem && ctx->stage != fragment_fs;
4991
4992    while (writemask) {
4993       int start, count;
4994       u_bit_scan_consecutive_range(&writemask, &start, &count);
4995       if (count == 3 && (smem || ctx->options->chip_class == GFX6)) {
4996          /* GFX6 doesn't support storing vec3, split it. */
4997          writemask |= 1u << (start + 2);
4998          count = 2;
4999       }
5000       int num_bytes = count * elem_size_bytes;
5001
5002       if (num_bytes > 16) {
5003          assert(elem_size_bytes == 8);
5004          writemask |= (((count - 2) << 1) - 1) << (start + 2);
5005          count = 2;
5006          num_bytes = 16;
5007       }
5008
5009       // TODO: check alignment of sub-dword stores
5010       // TODO: split 3 bytes. there is no store instruction for that
5011
5012       Temp write_data;
5013       if (count != instr->num_components) {
5014          emit_split_vector(ctx, data, instr->num_components);
5015          aco_ptr<Pseudo_instruction> vec{create_instruction<Pseudo_instruction>(aco_opcode::p_create_vector, Format::PSEUDO, count, 1)};
5016          for (int i = 0; i < count; i++) {
5017             Temp elem = emit_extract_vector(ctx, data, start + i, RegClass(data.type(), elem_size_bytes / 4));
5018             vec->operands[i] = Operand(smem_nonfs ? bld.as_uniform(elem) : elem);
5019          }
5020          write_data = bld.tmp(!smem ? RegType::vgpr : smem_nonfs ? RegType::sgpr : data.type(), count * elem_size_bytes / 4);
5021          vec->definitions[0] = Definition(write_data);
5022          ctx->block->instructions.emplace_back(std::move(vec));
5023       } else if (!smem && data.type() != RegType::vgpr) {
5024          assert(num_bytes % 4 == 0);
5025          write_data = bld.copy(bld.def(RegType::vgpr, num_bytes / 4), data);
5026       } else if (smem_nonfs && data.type() == RegType::vgpr) {
5027          assert(num_bytes % 4 == 0);
5028          write_data = bld.as_uniform(data);
5029       } else {
5030          write_data = data;
5031       }
5032
5033       aco_opcode vmem_op, smem_op;
5034       switch (num_bytes) {
5035          case 4:
5036             vmem_op = aco_opcode::buffer_store_dword;
5037             smem_op = aco_opcode::s_buffer_store_dword;
5038             break;
5039          case 8:
5040             vmem_op = aco_opcode::buffer_store_dwordx2;
5041             smem_op = aco_opcode::s_buffer_store_dwordx2;
5042             break;
5043          case 12:
5044             vmem_op = aco_opcode::buffer_store_dwordx3;
5045             smem_op = aco_opcode::last_opcode;
5046             assert(!smem && ctx->options->chip_class > GFX6);
5047             break;
5048          case 16:
5049             vmem_op = aco_opcode::buffer_store_dwordx4;
5050             smem_op = aco_opcode::s_buffer_store_dwordx4;
5051             break;
5052          default:
5053             unreachable("Store SSBO not implemented for this size.");
5054       }
5055       if (ctx->stage == fragment_fs)
5056          smem_op = aco_opcode::p_fs_buffer_store_smem;
5057
5058       if (smem) {
5059          aco_ptr<SMEM_instruction> store{create_instruction<SMEM_instruction>(smem_op, Format::SMEM, 3, 0)};
5060          store->operands[0] = Operand(rsrc);
5061          if (start) {
5062             Temp off = bld.sop2(aco_opcode::s_add_i32, bld.def(s1), bld.def(s1, scc),
5063                                 offset, Operand(start * elem_size_bytes));
5064             store->operands[1] = Operand(off);
5065          } else {
5066             store->operands[1] = Operand(offset);
5067          }
5068          if (smem_op != aco_opcode::p_fs_buffer_store_smem)
5069             store->operands[1].setFixed(m0);
5070          store->operands[2] = Operand(write_data);
5071          store->glc = nir_intrinsic_access(instr) & (ACCESS_VOLATILE | ACCESS_COHERENT | ACCESS_NON_READABLE);
5072          store->dlc = false;
5073          store->disable_wqm = true;
5074          store->barrier = barrier_buffer;
5075          ctx->block->instructions.emplace_back(std::move(store));
5076          ctx->program->wb_smem_l1_on_end = true;
5077          if (smem_op == aco_opcode::p_fs_buffer_store_smem) {
5078             ctx->block->kind |= block_kind_needs_lowering;
5079             ctx->program->needs_exact = true;
5080          }
5081       } else {
5082          aco_ptr<MUBUF_instruction> store{create_instruction<MUBUF_instruction>(vmem_op, Format::MUBUF, 4, 0)};
5083          store->operands[0] = Operand(rsrc);
5084          store->operands[1] = offset.type() == RegType::vgpr ? Operand(offset) : Operand(v1);
5085          store->operands[2] = offset.type() == RegType::sgpr ? Operand(offset) : Operand((uint32_t) 0);
5086          store->operands[3] = Operand(write_data);
5087          store->offset = start * elem_size_bytes;
5088          store->offen = (offset.type() == RegType::vgpr);
5089          store->glc = nir_intrinsic_access(instr) & (ACCESS_VOLATILE | ACCESS_COHERENT | ACCESS_NON_READABLE);
5090          store->dlc = false;
5091          store->disable_wqm = true;
5092          store->barrier = barrier_buffer;
5093          ctx->program->needs_exact = true;
5094          ctx->block->instructions.emplace_back(std::move(store));
5095       }
5096    }
5097 }
5098
5099 void visit_atomic_ssbo(isel_context *ctx, nir_intrinsic_instr *instr)
5100 {
5101    /* return the previous value if dest is ever used */
5102    bool return_previous = false;
5103    nir_foreach_use_safe(use_src, &instr->dest.ssa) {
5104       return_previous = true;
5105       break;
5106    }
5107    nir_foreach_if_use_safe(use_src, &instr->dest.ssa) {
5108       return_previous = true;
5109       break;
5110    }
5111
5112    Builder bld(ctx->program, ctx->block);
5113    Temp data = as_vgpr(ctx, get_ssa_temp(ctx, instr->src[2].ssa));
5114
5115    if (instr->intrinsic == nir_intrinsic_ssbo_atomic_comp_swap)
5116       data = bld.pseudo(aco_opcode::p_create_vector, bld.def(RegType::vgpr, data.size() * 2),
5117                         get_ssa_temp(ctx, instr->src[3].ssa), data);
5118
5119    Temp offset = get_ssa_temp(ctx, instr->src[1].ssa);
5120    Temp rsrc = convert_pointer_to_64_bit(ctx, get_ssa_temp(ctx, instr->src[0].ssa));
5121    rsrc = bld.smem(aco_opcode::s_load_dwordx4, bld.def(s4), rsrc, Operand(0u));
5122
5123    Temp dst = get_ssa_temp(ctx, &instr->dest.ssa);
5124
5125    aco_opcode op32, op64;
5126    switch (instr->intrinsic) {
5127       case nir_intrinsic_ssbo_atomic_add:
5128          op32 = aco_opcode::buffer_atomic_add;
5129          op64 = aco_opcode::buffer_atomic_add_x2;
5130          break;
5131       case nir_intrinsic_ssbo_atomic_imin:
5132          op32 = aco_opcode::buffer_atomic_smin;
5133          op64 = aco_opcode::buffer_atomic_smin_x2;
5134          break;
5135       case nir_intrinsic_ssbo_atomic_umin:
5136          op32 = aco_opcode::buffer_atomic_umin;
5137          op64 = aco_opcode::buffer_atomic_umin_x2;
5138          break;
5139       case nir_intrinsic_ssbo_atomic_imax:
5140          op32 = aco_opcode::buffer_atomic_smax;
5141          op64 = aco_opcode::buffer_atomic_smax_x2;
5142          break;
5143       case nir_intrinsic_ssbo_atomic_umax:
5144          op32 = aco_opcode::buffer_atomic_umax;
5145          op64 = aco_opcode::buffer_atomic_umax_x2;
5146          break;
5147       case nir_intrinsic_ssbo_atomic_and:
5148          op32 = aco_opcode::buffer_atomic_and;
5149          op64 = aco_opcode::buffer_atomic_and_x2;
5150          break;
5151       case nir_intrinsic_ssbo_atomic_or:
5152          op32 = aco_opcode::buffer_atomic_or;
5153          op64 = aco_opcode::buffer_atomic_or_x2;
5154          break;
5155       case nir_intrinsic_ssbo_atomic_xor:
5156          op32 = aco_opcode::buffer_atomic_xor;
5157          op64 = aco_opcode::buffer_atomic_xor_x2;
5158          break;
5159       case nir_intrinsic_ssbo_atomic_exchange:
5160          op32 = aco_opcode::buffer_atomic_swap;
5161          op64 = aco_opcode::buffer_atomic_swap_x2;
5162          break;
5163       case nir_intrinsic_ssbo_atomic_comp_swap:
5164          op32 = aco_opcode::buffer_atomic_cmpswap;
5165          op64 = aco_opcode::buffer_atomic_cmpswap_x2;
5166          break;
5167       default:
5168          unreachable("visit_atomic_ssbo should only be called with nir_intrinsic_ssbo_atomic_* instructions.");
5169    }
5170    aco_opcode op = instr->dest.ssa.bit_size == 32 ? op32 : op64;
5171    aco_ptr<MUBUF_instruction> mubuf{create_instruction<MUBUF_instruction>(op, Format::MUBUF, 4, return_previous ? 1 : 0)};
5172    mubuf->operands[0] = Operand(rsrc);
5173    mubuf->operands[1] = offset.type() == RegType::vgpr ? Operand(offset) : Operand(v1);
5174    mubuf->operands[2] = offset.type() == RegType::sgpr ? Operand(offset) : Operand((uint32_t) 0);
5175    mubuf->operands[3] = Operand(data);
5176    if (return_previous)
5177       mubuf->definitions[0] = Definition(dst);
5178    mubuf->offset = 0;
5179    mubuf->offen = (offset.type() == RegType::vgpr);
5180    mubuf->glc = return_previous;
5181    mubuf->dlc = false; /* Not needed for atomics */
5182    mubuf->disable_wqm = true;
5183    mubuf->barrier = barrier_buffer;
5184    ctx->program->needs_exact = true;
5185    ctx->block->instructions.emplace_back(std::move(mubuf));
5186 }
5187
5188 void visit_get_buffer_size(isel_context *ctx, nir_intrinsic_instr *instr) {
5189
5190    Temp index = convert_pointer_to_64_bit(ctx, get_ssa_temp(ctx, instr->src[0].ssa));
5191    Builder bld(ctx->program, ctx->block);
5192    Temp desc = bld.smem(aco_opcode::s_load_dwordx4, bld.def(s4), index, Operand(0u));
5193    get_buffer_size(ctx, desc, get_ssa_temp(ctx, &instr->dest.ssa), false);
5194 }
5195
5196 Temp get_gfx6_global_rsrc(Builder& bld, Temp addr)
5197 {
5198    uint32_t rsrc_conf = S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
5199                         S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32);
5200
5201    if (addr.type() == RegType::vgpr)
5202       return bld.pseudo(aco_opcode::p_create_vector, bld.def(s4), Operand(0u), Operand(0u), Operand(-1u), Operand(rsrc_conf));
5203    return bld.pseudo(aco_opcode::p_create_vector, bld.def(s4), addr, Operand(-1u), Operand(rsrc_conf));
5204 }
5205
5206 void visit_load_global(isel_context *ctx, nir_intrinsic_instr *instr)
5207 {
5208    Builder bld(ctx->program, ctx->block);
5209    unsigned num_components = instr->num_components;
5210    unsigned num_bytes = num_components * instr->dest.ssa.bit_size / 8;
5211
5212    Temp dst = get_ssa_temp(ctx, &instr->dest.ssa);
5213    Temp addr = get_ssa_temp(ctx, instr->src[0].ssa);
5214
5215    bool glc = nir_intrinsic_access(instr) & (ACCESS_VOLATILE | ACCESS_COHERENT);
5216    bool dlc = glc && ctx->options->chip_class >= GFX10;
5217    aco_opcode op;
5218    if (dst.type() == RegType::vgpr || (glc && ctx->options->chip_class < GFX8)) {
5219       bool global = ctx->options->chip_class >= GFX9;
5220
5221       if (ctx->options->chip_class >= GFX7) {
5222          aco_opcode op;
5223          switch (num_bytes) {
5224          case 4:
5225             op = global ? aco_opcode::global_load_dword : aco_opcode::flat_load_dword;
5226             break;
5227          case 8:
5228             op = global ? aco_opcode::global_load_dwordx2 : aco_opcode::flat_load_dwordx2;
5229             break;
5230          case 12:
5231             op = global ? aco_opcode::global_load_dwordx3 : aco_opcode::flat_load_dwordx3;
5232             break;
5233          case 16:
5234             op = global ? aco_opcode::global_load_dwordx4 : aco_opcode::flat_load_dwordx4;
5235             break;
5236          default:
5237             unreachable("load_global not implemented for this size.");
5238          }
5239
5240          aco_ptr<FLAT_instruction> flat{create_instruction<FLAT_instruction>(op, global ? Format::GLOBAL : Format::FLAT, 2, 1)};
5241          flat->operands[0] = Operand(addr);
5242          flat->operands[1] = Operand(s1);
5243          flat->glc = glc;
5244          flat->dlc = dlc;
5245          flat->barrier = barrier_buffer;
5246
5247          if (dst.type() == RegType::sgpr) {
5248             Temp vec = bld.tmp(RegType::vgpr, dst.size());
5249             flat->definitions[0] = Definition(vec);
5250             ctx->block->instructions.emplace_back(std::move(flat));
5251             bld.pseudo(aco_opcode::p_as_uniform, Definition(dst), vec);
5252          } else {
5253             flat->definitions[0] = Definition(dst);
5254             ctx->block->instructions.emplace_back(std::move(flat));
5255          }
5256          emit_split_vector(ctx, dst, num_components);
5257       } else {
5258          assert(ctx->options->chip_class == GFX6);
5259
5260          /* GFX6 doesn't support loading vec3, expand to vec4. */
5261          num_bytes = num_bytes == 12 ? 16 : num_bytes;
5262
5263          aco_opcode op;
5264          switch (num_bytes) {
5265          case 4:
5266             op = aco_opcode::buffer_load_dword;
5267             break;
5268          case 8:
5269             op = aco_opcode::buffer_load_dwordx2;
5270             break;
5271          case 16:
5272             op = aco_opcode::buffer_load_dwordx4;
5273             break;
5274          default:
5275             unreachable("load_global not implemented for this size.");
5276          }
5277
5278          Temp rsrc = get_gfx6_global_rsrc(bld, addr);
5279
5280          aco_ptr<MUBUF_instruction> mubuf{create_instruction<MUBUF_instruction>(op, Format::MUBUF, 3, 1)};
5281          mubuf->operands[0] = Operand(rsrc);
5282          mubuf->operands[1] = addr.type() == RegType::vgpr ? Operand(addr) : Operand(v1);
5283          mubuf->operands[2] = Operand(0u);
5284          mubuf->glc = glc;
5285          mubuf->dlc = false;
5286          mubuf->offset = 0;
5287          mubuf->addr64 = addr.type() == RegType::vgpr;
5288          mubuf->disable_wqm = false;
5289          mubuf->barrier = barrier_buffer;
5290          aco_ptr<Instruction> instr = std::move(mubuf);
5291
5292          /* expand vector */
5293          if (dst.size() == 3) {
5294             Temp vec = bld.tmp(v4);
5295             instr->definitions[0] = Definition(vec);
5296             bld.insert(std::move(instr));
5297             emit_split_vector(ctx, vec, 4);
5298
5299             instr.reset(create_instruction<Pseudo_instruction>(aco_opcode::p_create_vector, Format::PSEUDO, 3, 1));
5300             instr->operands[0] = Operand(emit_extract_vector(ctx, vec, 0, v1));
5301             instr->operands[1] = Operand(emit_extract_vector(ctx, vec, 1, v1));
5302             instr->operands[2] = Operand(emit_extract_vector(ctx, vec, 2, v1));
5303          }
5304
5305          if (dst.type() == RegType::sgpr) {
5306             Temp vec = bld.tmp(RegType::vgpr, dst.size());
5307             instr->definitions[0] = Definition(vec);
5308             bld.insert(std::move(instr));
5309             expand_vector(ctx, vec, dst, num_components, (1 << num_components) - 1);
5310             bld.pseudo(aco_opcode::p_as_uniform, Definition(dst), vec);
5311          } else {
5312             instr->definitions[0] = Definition(dst);
5313             bld.insert(std::move(instr));
5314             emit_split_vector(ctx, dst, num_components);
5315          }
5316       }
5317    } else {
5318       switch (num_bytes) {
5319          case 4:
5320             op = aco_opcode::s_load_dword;
5321             break;
5322          case 8:
5323             op = aco_opcode::s_load_dwordx2;
5324             break;
5325          case 12:
5326          case 16:
5327             op = aco_opcode::s_load_dwordx4;
5328             break;
5329          default:
5330             unreachable("load_global not implemented for this size.");
5331       }
5332       aco_ptr<SMEM_instruction> load{create_instruction<SMEM_instruction>(op, Format::SMEM, 2, 1)};
5333       load->operands[0] = Operand(addr);
5334       load->operands[1] = Operand(0u);
5335       load->definitions[0] = Definition(dst);
5336       load->glc = glc;
5337       load->dlc = dlc;
5338       load->barrier = barrier_buffer;
5339       assert(ctx->options->chip_class >= GFX8 || !glc);
5340
5341       if (dst.size() == 3) {
5342          /* trim vector */
5343          Temp vec = bld.tmp(s4);
5344          load->definitions[0] = Definition(vec);
5345          ctx->block->instructions.emplace_back(std::move(load));
5346          emit_split_vector(ctx, vec, 4);
5347
5348          bld.pseudo(aco_opcode::p_create_vector, Definition(dst),
5349                     emit_extract_vector(ctx, vec, 0, s1),
5350                     emit_extract_vector(ctx, vec, 1, s1),
5351                     emit_extract_vector(ctx, vec, 2, s1));
5352       } else {
5353          ctx->block->instructions.emplace_back(std::move(load));
5354       }
5355    }
5356 }
5357
5358 void visit_store_global(isel_context *ctx, nir_intrinsic_instr *instr)
5359 {
5360    Builder bld(ctx->program, ctx->block);
5361    unsigned elem_size_bytes = instr->src[0].ssa->bit_size / 8;
5362
5363    Temp data = as_vgpr(ctx, get_ssa_temp(ctx, instr->src[0].ssa));
5364    Temp addr = get_ssa_temp(ctx, instr->src[1].ssa);
5365
5366    if (ctx->options->chip_class >= GFX7)
5367       addr = as_vgpr(ctx, addr);
5368
5369    unsigned writemask = nir_intrinsic_write_mask(instr);
5370    while (writemask) {
5371       int start, count;
5372       u_bit_scan_consecutive_range(&writemask, &start, &count);
5373       if (count == 3 && ctx->options->chip_class == GFX6) {
5374          /* GFX6 doesn't support storing vec3, split it. */
5375          writemask |= 1u << (start + 2);
5376          count = 2;
5377       }
5378       unsigned num_bytes = count * elem_size_bytes;
5379
5380       Temp write_data = data;
5381       if (count != instr->num_components) {
5382          aco_ptr<Pseudo_instruction> vec{create_instruction<Pseudo_instruction>(aco_opcode::p_create_vector, Format::PSEUDO, count, 1)};
5383          for (int i = 0; i < count; i++)
5384             vec->operands[i] = Operand(emit_extract_vector(ctx, data, start + i, v1));
5385          write_data = bld.tmp(RegType::vgpr, count);
5386          vec->definitions[0] = Definition(write_data);
5387          ctx->block->instructions.emplace_back(std::move(vec));
5388       }
5389
5390       bool glc = nir_intrinsic_access(instr) & (ACCESS_VOLATILE | ACCESS_COHERENT | ACCESS_NON_READABLE);
5391       unsigned offset = start * elem_size_bytes;
5392
5393       if (ctx->options->chip_class >= GFX7) {
5394          if (offset > 0 && ctx->options->chip_class < GFX9) {
5395             Temp addr0 = bld.tmp(v1), addr1 = bld.tmp(v1);
5396             Temp new_addr0 = bld.tmp(v1), new_addr1 = bld.tmp(v1);
5397             Temp carry = bld.tmp(bld.lm);
5398             bld.pseudo(aco_opcode::p_split_vector, Definition(addr0), Definition(addr1), addr);
5399
5400             bld.vop2(aco_opcode::v_add_co_u32, Definition(new_addr0), bld.hint_vcc(Definition(carry)),
5401                      Operand(offset), addr0);
5402             bld.vop2(aco_opcode::v_addc_co_u32, Definition(new_addr1), bld.def(bld.lm),
5403                      Operand(0u), addr1,
5404                      carry).def(1).setHint(vcc);
5405
5406             addr = bld.pseudo(aco_opcode::p_create_vector, bld.def(v2), new_addr0, new_addr1);
5407
5408             offset = 0;
5409          }
5410
5411          bool global = ctx->options->chip_class >= GFX9;
5412          aco_opcode op;
5413          switch (num_bytes) {
5414          case 4:
5415             op = global ? aco_opcode::global_store_dword : aco_opcode::flat_store_dword;
5416             break;
5417          case 8:
5418             op = global ? aco_opcode::global_store_dwordx2 : aco_opcode::flat_store_dwordx2;
5419             break;
5420          case 12:
5421             op = global ? aco_opcode::global_store_dwordx3 : aco_opcode::flat_store_dwordx3;
5422             break;
5423          case 16:
5424             op = global ? aco_opcode::global_store_dwordx4 : aco_opcode::flat_store_dwordx4;
5425             break;
5426          default:
5427             unreachable("store_global not implemented for this size.");
5428          }
5429
5430          aco_ptr<FLAT_instruction> flat{create_instruction<FLAT_instruction>(op, global ? Format::GLOBAL : Format::FLAT, 3, 0)};
5431          flat->operands[0] = Operand(addr);
5432          flat->operands[1] = Operand(s1);
5433          flat->operands[2] = Operand(data);
5434          flat->glc = glc;
5435          flat->dlc = false;
5436          flat->offset = offset;
5437          flat->disable_wqm = true;
5438          flat->barrier = barrier_buffer;
5439          ctx->program->needs_exact = true;
5440          ctx->block->instructions.emplace_back(std::move(flat));
5441       } else {
5442          assert(ctx->options->chip_class == GFX6);
5443
5444          aco_opcode op;
5445          switch (num_bytes) {
5446          case 4:
5447             op = aco_opcode::buffer_store_dword;
5448             break;
5449          case 8:
5450             op = aco_opcode::buffer_store_dwordx2;
5451             break;
5452          case 16:
5453             op = aco_opcode::buffer_store_dwordx4;
5454             break;
5455          default:
5456             unreachable("store_global not implemented for this size.");
5457          }
5458
5459          Temp rsrc = get_gfx6_global_rsrc(bld, addr);
5460
5461          aco_ptr<MUBUF_instruction> mubuf{create_instruction<MUBUF_instruction>(op, Format::MUBUF, 4, 0)};
5462          mubuf->operands[0] = Operand(rsrc);
5463          mubuf->operands[1] = addr.type() == RegType::vgpr ? Operand(addr) : Operand(v1);
5464          mubuf->operands[2] = Operand(0u);
5465          mubuf->operands[3] = Operand(write_data);
5466          mubuf->glc = glc;
5467          mubuf->dlc = false;
5468          mubuf->offset = offset;
5469          mubuf->addr64 = addr.type() == RegType::vgpr;
5470          mubuf->disable_wqm = true;
5471          mubuf->barrier = barrier_buffer;
5472          ctx->program->needs_exact = true;
5473          ctx->block->instructions.emplace_back(std::move(mubuf));
5474       }
5475    }
5476 }
5477
5478 void visit_global_atomic(isel_context *ctx, nir_intrinsic_instr *instr)
5479 {
5480    /* return the previous value if dest is ever used */
5481    bool return_previous = false;
5482    nir_foreach_use_safe(use_src, &instr->dest.ssa) {
5483       return_previous = true;
5484       break;
5485    }
5486    nir_foreach_if_use_safe(use_src, &instr->dest.ssa) {
5487       return_previous = true;
5488       break;
5489    }
5490
5491    Builder bld(ctx->program, ctx->block);
5492    Temp addr = get_ssa_temp(ctx, instr->src[0].ssa);
5493    Temp data = as_vgpr(ctx, get_ssa_temp(ctx, instr->src[1].ssa));
5494
5495    if (ctx->options->chip_class >= GFX7)
5496       addr = as_vgpr(ctx, addr);
5497
5498    if (instr->intrinsic == nir_intrinsic_global_atomic_comp_swap)
5499       data = bld.pseudo(aco_opcode::p_create_vector, bld.def(RegType::vgpr, data.size() * 2),
5500                         get_ssa_temp(ctx, instr->src[2].ssa), data);
5501
5502    Temp dst = get_ssa_temp(ctx, &instr->dest.ssa);
5503
5504    aco_opcode op32, op64;
5505
5506    if (ctx->options->chip_class >= GFX7) {
5507       bool global = ctx->options->chip_class >= GFX9;
5508       switch (instr->intrinsic) {
5509          case nir_intrinsic_global_atomic_add:
5510             op32 = global ? aco_opcode::global_atomic_add : aco_opcode::flat_atomic_add;
5511             op64 = global ? aco_opcode::global_atomic_add_x2 : aco_opcode::flat_atomic_add_x2;
5512             break;
5513          case nir_intrinsic_global_atomic_imin:
5514             op32 = global ? aco_opcode::global_atomic_smin : aco_opcode::flat_atomic_smin;
5515             op64 = global ? aco_opcode::global_atomic_smin_x2 : aco_opcode::flat_atomic_smin_x2;
5516             break;
5517          case nir_intrinsic_global_atomic_umin:
5518             op32 = global ? aco_opcode::global_atomic_umin : aco_opcode::flat_atomic_umin;
5519             op64 = global ? aco_opcode::global_atomic_umin_x2 : aco_opcode::flat_atomic_umin_x2;
5520             break;
5521          case nir_intrinsic_global_atomic_imax:
5522             op32 = global ? aco_opcode::global_atomic_smax : aco_opcode::flat_atomic_smax;
5523             op64 = global ? aco_opcode::global_atomic_smax_x2 : aco_opcode::flat_atomic_smax_x2;
5524             break;
5525          case nir_intrinsic_global_atomic_umax:
5526             op32 = global ? aco_opcode::global_atomic_umax : aco_opcode::flat_atomic_umax;
5527             op64 = global ? aco_opcode::global_atomic_umax_x2 : aco_opcode::flat_atomic_umax_x2;
5528             break;
5529          case nir_intrinsic_global_atomic_and:
5530             op32 = global ? aco_opcode::global_atomic_and : aco_opcode::flat_atomic_and;
5531             op64 = global ? aco_opcode::global_atomic_and_x2 : aco_opcode::flat_atomic_and_x2;
5532             break;
5533          case nir_intrinsic_global_atomic_or:
5534             op32 = global ? aco_opcode::global_atomic_or : aco_opcode::flat_atomic_or;
5535             op64 = global ? aco_opcode::global_atomic_or_x2 : aco_opcode::flat_atomic_or_x2;
5536             break;
5537          case nir_intrinsic_global_atomic_xor:
5538             op32 = global ? aco_opcode::global_atomic_xor : aco_opcode::flat_atomic_xor;
5539             op64 = global ? aco_opcode::global_atomic_xor_x2 : aco_opcode::flat_atomic_xor_x2;
5540             break;
5541          case nir_intrinsic_global_atomic_exchange:
5542             op32 = global ? aco_opcode::global_atomic_swap : aco_opcode::flat_atomic_swap;
5543             op64 = global ? aco_opcode::global_atomic_swap_x2 : aco_opcode::flat_atomic_swap_x2;
5544             break;
5545          case nir_intrinsic_global_atomic_comp_swap:
5546             op32 = global ? aco_opcode::global_atomic_cmpswap : aco_opcode::flat_atomic_cmpswap;
5547             op64 = global ? aco_opcode::global_atomic_cmpswap_x2 : aco_opcode::flat_atomic_cmpswap_x2;
5548             break;
5549          default:
5550             unreachable("visit_atomic_global should only be called with nir_intrinsic_global_atomic_* instructions.");
5551       }
5552
5553       aco_opcode op = instr->dest.ssa.bit_size == 32 ? op32 : op64;
5554       aco_ptr<FLAT_instruction> flat{create_instruction<FLAT_instruction>(op, global ? Format::GLOBAL : Format::FLAT, 3, return_previous ? 1 : 0)};
5555       flat->operands[0] = Operand(addr);
5556       flat->operands[1] = Operand(s1);
5557       flat->operands[2] = Operand(data);
5558       if (return_previous)
5559          flat->definitions[0] = Definition(dst);
5560       flat->glc = return_previous;
5561       flat->dlc = false; /* Not needed for atomics */
5562       flat->offset = 0;
5563       flat->disable_wqm = true;
5564       flat->barrier = barrier_buffer;
5565       ctx->program->needs_exact = true;
5566       ctx->block->instructions.emplace_back(std::move(flat));
5567    } else {
5568       assert(ctx->options->chip_class == GFX6);
5569
5570       switch (instr->intrinsic) {
5571          case nir_intrinsic_global_atomic_add:
5572             op32 = aco_opcode::buffer_atomic_add;
5573             op64 = aco_opcode::buffer_atomic_add_x2;
5574             break;
5575          case nir_intrinsic_global_atomic_imin:
5576             op32 = aco_opcode::buffer_atomic_smin;
5577             op64 = aco_opcode::buffer_atomic_smin_x2;
5578             break;
5579          case nir_intrinsic_global_atomic_umin:
5580             op32 = aco_opcode::buffer_atomic_umin;
5581             op64 = aco_opcode::buffer_atomic_umin_x2;
5582             break;
5583          case nir_intrinsic_global_atomic_imax:
5584             op32 = aco_opcode::buffer_atomic_smax;
5585             op64 = aco_opcode::buffer_atomic_smax_x2;
5586             break;
5587          case nir_intrinsic_global_atomic_umax:
5588             op32 = aco_opcode::buffer_atomic_umax;
5589             op64 = aco_opcode::buffer_atomic_umax_x2;
5590             break;
5591          case nir_intrinsic_global_atomic_and:
5592             op32 = aco_opcode::buffer_atomic_and;
5593             op64 = aco_opcode::buffer_atomic_and_x2;
5594             break;
5595          case nir_intrinsic_global_atomic_or:
5596             op32 = aco_opcode::buffer_atomic_or;
5597             op64 = aco_opcode::buffer_atomic_or_x2;
5598             break;
5599          case nir_intrinsic_global_atomic_xor:
5600             op32 = aco_opcode::buffer_atomic_xor;
5601             op64 = aco_opcode::buffer_atomic_xor_x2;
5602             break;
5603          case nir_intrinsic_global_atomic_exchange:
5604             op32 = aco_opcode::buffer_atomic_swap;
5605             op64 = aco_opcode::buffer_atomic_swap_x2;
5606             break;
5607          case nir_intrinsic_global_atomic_comp_swap:
5608             op32 = aco_opcode::buffer_atomic_cmpswap;
5609             op64 = aco_opcode::buffer_atomic_cmpswap_x2;
5610             break;
5611          default:
5612             unreachable("visit_atomic_global should only be called with nir_intrinsic_global_atomic_* instructions.");
5613       }
5614
5615       Temp rsrc = get_gfx6_global_rsrc(bld, addr);
5616
5617       aco_opcode op = instr->dest.ssa.bit_size == 32 ? op32 : op64;
5618
5619       aco_ptr<MUBUF_instruction> mubuf{create_instruction<MUBUF_instruction>(op, Format::MUBUF, 4, return_previous ? 1 : 0)};
5620       mubuf->operands[0] = Operand(rsrc);
5621       mubuf->operands[1] = addr.type() == RegType::vgpr ? Operand(addr) : Operand(v1);
5622       mubuf->operands[2] = Operand(0u);
5623       mubuf->operands[3] = Operand(data);
5624       if (return_previous)
5625          mubuf->definitions[0] = Definition(dst);
5626       mubuf->glc = return_previous;
5627       mubuf->dlc = false;
5628       mubuf->offset = 0;
5629       mubuf->addr64 = addr.type() == RegType::vgpr;
5630       mubuf->disable_wqm = true;
5631       mubuf->barrier = barrier_buffer;
5632       ctx->program->needs_exact = true;
5633       ctx->block->instructions.emplace_back(std::move(mubuf));
5634    }
5635 }
5636
5637 void emit_memory_barrier(isel_context *ctx, nir_intrinsic_instr *instr) {
5638    Builder bld(ctx->program, ctx->block);
5639    switch(instr->intrinsic) {
5640       case nir_intrinsic_group_memory_barrier:
5641       case nir_intrinsic_memory_barrier:
5642          bld.barrier(aco_opcode::p_memory_barrier_common);
5643          break;
5644       case nir_intrinsic_memory_barrier_buffer:
5645          bld.barrier(aco_opcode::p_memory_barrier_buffer);
5646          break;
5647       case nir_intrinsic_memory_barrier_image:
5648          bld.barrier(aco_opcode::p_memory_barrier_image);
5649          break;
5650       case nir_intrinsic_memory_barrier_tcs_patch:
5651       case nir_intrinsic_memory_barrier_shared:
5652          bld.barrier(aco_opcode::p_memory_barrier_shared);
5653          break;
5654       default:
5655          unreachable("Unimplemented memory barrier intrinsic");
5656          break;
5657    }
5658 }
5659
5660 void visit_load_shared(isel_context *ctx, nir_intrinsic_instr *instr)
5661 {
5662    // TODO: implement sparse reads using ds_read2_b32 and nir_ssa_def_components_read()
5663    Temp dst = get_ssa_temp(ctx, &instr->dest.ssa);
5664    assert(instr->dest.ssa.bit_size >= 32 && "Bitsize not supported in load_shared.");
5665    Temp address = as_vgpr(ctx, get_ssa_temp(ctx, instr->src[0].ssa));
5666    Builder bld(ctx->program, ctx->block);
5667
5668    unsigned elem_size_bytes = instr->dest.ssa.bit_size / 8;
5669    unsigned align = nir_intrinsic_align_mul(instr) ? nir_intrinsic_align(instr) : elem_size_bytes;
5670    load_lds(ctx, elem_size_bytes, dst, address, nir_intrinsic_base(instr), align);
5671 }
5672
5673 void visit_store_shared(isel_context *ctx, nir_intrinsic_instr *instr)
5674 {
5675    unsigned writemask = nir_intrinsic_write_mask(instr);
5676    Temp data = get_ssa_temp(ctx, instr->src[0].ssa);
5677    Temp address = as_vgpr(ctx, get_ssa_temp(ctx, instr->src[1].ssa));
5678    unsigned elem_size_bytes = instr->src[0].ssa->bit_size / 8;
5679    assert(elem_size_bytes >= 4 && "Only 32bit & 64bit store_shared currently supported.");
5680
5681    unsigned align = nir_intrinsic_align_mul(instr) ? nir_intrinsic_align(instr) : elem_size_bytes;
5682    store_lds(ctx, elem_size_bytes, data, writemask, address, nir_intrinsic_base(instr), align);
5683 }
5684
5685 void visit_shared_atomic(isel_context *ctx, nir_intrinsic_instr *instr)
5686 {
5687    unsigned offset = nir_intrinsic_base(instr);
5688    Operand m = load_lds_size_m0(ctx);
5689    Temp data = as_vgpr(ctx, get_ssa_temp(ctx, instr->src[1].ssa));
5690    Temp address = as_vgpr(ctx, get_ssa_temp(ctx, instr->src[0].ssa));
5691
5692    unsigned num_operands = 3;
5693    aco_opcode op32, op64, op32_rtn, op64_rtn;
5694    switch(instr->intrinsic) {
5695       case nir_intrinsic_shared_atomic_add:
5696          op32 = aco_opcode::ds_add_u32;
5697          op64 = aco_opcode::ds_add_u64;
5698          op32_rtn = aco_opcode::ds_add_rtn_u32;
5699          op64_rtn = aco_opcode::ds_add_rtn_u64;
5700          break;
5701       case nir_intrinsic_shared_atomic_imin:
5702          op32 = aco_opcode::ds_min_i32;
5703          op64 = aco_opcode::ds_min_i64;
5704          op32_rtn = aco_opcode::ds_min_rtn_i32;
5705          op64_rtn = aco_opcode::ds_min_rtn_i64;
5706          break;
5707       case nir_intrinsic_shared_atomic_umin:
5708          op32 = aco_opcode::ds_min_u32;
5709          op64 = aco_opcode::ds_min_u64;
5710          op32_rtn = aco_opcode::ds_min_rtn_u32;
5711          op64_rtn = aco_opcode::ds_min_rtn_u64;
5712          break;
5713       case nir_intrinsic_shared_atomic_imax:
5714          op32 = aco_opcode::ds_max_i32;
5715          op64 = aco_opcode::ds_max_i64;
5716          op32_rtn = aco_opcode::ds_max_rtn_i32;
5717          op64_rtn = aco_opcode::ds_max_rtn_i64;
5718          break;
5719       case nir_intrinsic_shared_atomic_umax:
5720          op32 = aco_opcode::ds_max_u32;
5721          op64 = aco_opcode::ds_max_u64;
5722          op32_rtn = aco_opcode::ds_max_rtn_u32;
5723          op64_rtn = aco_opcode::ds_max_rtn_u64;
5724          break;
5725       case nir_intrinsic_shared_atomic_and:
5726          op32 = aco_opcode::ds_and_b32;
5727          op64 = aco_opcode::ds_and_b64;
5728          op32_rtn = aco_opcode::ds_and_rtn_b32;
5729          op64_rtn = aco_opcode::ds_and_rtn_b64;
5730          break;
5731       case nir_intrinsic_shared_atomic_or:
5732          op32 = aco_opcode::ds_or_b32;
5733          op64 = aco_opcode::ds_or_b64;
5734          op32_rtn = aco_opcode::ds_or_rtn_b32;
5735          op64_rtn = aco_opcode::ds_or_rtn_b64;
5736          break;
5737       case nir_intrinsic_shared_atomic_xor:
5738          op32 = aco_opcode::ds_xor_b32;
5739          op64 = aco_opcode::ds_xor_b64;
5740          op32_rtn = aco_opcode::ds_xor_rtn_b32;
5741          op64_rtn = aco_opcode::ds_xor_rtn_b64;
5742          break;
5743       case nir_intrinsic_shared_atomic_exchange:
5744          op32 = aco_opcode::ds_write_b32;
5745          op64 = aco_opcode::ds_write_b64;
5746          op32_rtn = aco_opcode::ds_wrxchg_rtn_b32;
5747          op64_rtn = aco_opcode::ds_wrxchg2_rtn_b64;
5748          break;
5749       case nir_intrinsic_shared_atomic_comp_swap:
5750          op32 = aco_opcode::ds_cmpst_b32;
5751          op64 = aco_opcode::ds_cmpst_b64;
5752          op32_rtn = aco_opcode::ds_cmpst_rtn_b32;
5753          op64_rtn = aco_opcode::ds_cmpst_rtn_b64;
5754          num_operands = 4;
5755          break;
5756       default:
5757          unreachable("Unhandled shared atomic intrinsic");
5758    }
5759
5760    /* return the previous value if dest is ever used */
5761    bool return_previous = false;
5762    nir_foreach_use_safe(use_src, &instr->dest.ssa) {
5763       return_previous = true;
5764       break;
5765    }
5766    nir_foreach_if_use_safe(use_src, &instr->dest.ssa) {
5767       return_previous = true;
5768       break;
5769    }
5770
5771    aco_opcode op;
5772    if (data.size() == 1) {
5773       assert(instr->dest.ssa.bit_size == 32);
5774       op = return_previous ? op32_rtn : op32;
5775    } else {
5776       assert(instr->dest.ssa.bit_size == 64);
5777       op = return_previous ? op64_rtn : op64;
5778    }
5779
5780    if (offset > 65535) {
5781       Builder bld(ctx->program, ctx->block);
5782       address = bld.vadd32(bld.def(v1), Operand(offset), address);
5783       offset = 0;
5784    }
5785
5786    aco_ptr<DS_instruction> ds;
5787    ds.reset(create_instruction<DS_instruction>(op, Format::DS, num_operands, return_previous ? 1 : 0));
5788    ds->operands[0] = Operand(address);
5789    ds->operands[1] = Operand(data);
5790    if (num_operands == 4)
5791       ds->operands[2] = Operand(get_ssa_temp(ctx, instr->src[2].ssa));
5792    ds->operands[num_operands - 1] = m;
5793    ds->offset0 = offset;
5794    if (return_previous)
5795       ds->definitions[0] = Definition(get_ssa_temp(ctx, &instr->dest.ssa));
5796    ctx->block->instructions.emplace_back(std::move(ds));
5797 }
5798
5799 Temp get_scratch_resource(isel_context *ctx)
5800 {
5801    Builder bld(ctx->program, ctx->block);
5802    Temp scratch_addr = ctx->program->private_segment_buffer;
5803    if (ctx->stage != compute_cs)
5804       scratch_addr = bld.smem(aco_opcode::s_load_dwordx2, bld.def(s2), scratch_addr, Operand(0u));
5805
5806    uint32_t rsrc_conf = S_008F0C_ADD_TID_ENABLE(1) |
5807                         S_008F0C_INDEX_STRIDE(ctx->program->wave_size == 64 ? 3 : 2);;
5808
5809    if (ctx->program->chip_class >= GFX10) {
5810       rsrc_conf |= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_FLOAT) |
5811                    S_008F0C_OOB_SELECT(V_008F0C_OOB_SELECT_RAW) |
5812                    S_008F0C_RESOURCE_LEVEL(1);
5813    } else if (ctx->program->chip_class <= GFX7) { /* dfmt modifies stride on GFX8/GFX9 when ADD_TID_EN=1 */
5814       rsrc_conf |= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
5815                    S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32);
5816    }
5817
5818    /* older generations need element size = 16 bytes. element size removed in GFX9 */
5819    if (ctx->program->chip_class <= GFX8)
5820       rsrc_conf |= S_008F0C_ELEMENT_SIZE(3);
5821
5822    return bld.pseudo(aco_opcode::p_create_vector, bld.def(s4), scratch_addr, Operand(-1u), Operand(rsrc_conf));
5823 }
5824
5825 void visit_load_scratch(isel_context *ctx, nir_intrinsic_instr *instr) {
5826    assert(instr->dest.ssa.bit_size == 32 || instr->dest.ssa.bit_size == 64);
5827    Builder bld(ctx->program, ctx->block);
5828    Temp rsrc = get_scratch_resource(ctx);
5829    Temp offset = as_vgpr(ctx, get_ssa_temp(ctx, instr->src[0].ssa));
5830    Temp dst = get_ssa_temp(ctx, &instr->dest.ssa);
5831
5832    aco_opcode op;
5833    switch (dst.size()) {
5834       case 1:
5835          op = aco_opcode::buffer_load_dword;
5836          break;
5837       case 2:
5838          op = aco_opcode::buffer_load_dwordx2;
5839          break;
5840       case 3:
5841          op = aco_opcode::buffer_load_dwordx3;
5842          break;
5843       case 4:
5844          op = aco_opcode::buffer_load_dwordx4;
5845          break;
5846       case 6:
5847       case 8: {
5848          std::array<Temp,NIR_MAX_VEC_COMPONENTS> elems;
5849          Temp lower = bld.mubuf(aco_opcode::buffer_load_dwordx4,
5850                                 bld.def(v4), rsrc, offset,
5851                                 ctx->program->scratch_offset, 0, true);
5852          Temp upper = bld.mubuf(dst.size() == 6 ? aco_opcode::buffer_load_dwordx2 :
5853                                                   aco_opcode::buffer_load_dwordx4,
5854                                 dst.size() == 6 ? bld.def(v2) : bld.def(v4),
5855                                 rsrc, offset, ctx->program->scratch_offset, 16, true);
5856          emit_split_vector(ctx, lower, 2);
5857          elems[0] = emit_extract_vector(ctx, lower, 0, v2);
5858          elems[1] = emit_extract_vector(ctx, lower, 1, v2);
5859          if (dst.size() == 8) {
5860             emit_split_vector(ctx, upper, 2);
5861             elems[2] = emit_extract_vector(ctx, upper, 0, v2);
5862             elems[3] = emit_extract_vector(ctx, upper, 1, v2);
5863          } else {
5864             elems[2] = upper;
5865          }
5866
5867          aco_ptr<Instruction> vec{create_instruction<Pseudo_instruction>(aco_opcode::p_create_vector,
5868                                                                          Format::PSEUDO, dst.size() / 2, 1)};
5869          for (unsigned i = 0; i < dst.size() / 2; i++)
5870             vec->operands[i] = Operand(elems[i]);
5871          vec->definitions[0] = Definition(dst);
5872          bld.insert(std::move(vec));
5873          ctx->allocated_vec.emplace(dst.id(), elems);
5874          return;
5875       }
5876       default:
5877          unreachable("Wrong dst size for nir_intrinsic_load_scratch");
5878    }
5879
5880    bld.mubuf(op, Definition(dst), rsrc, offset, ctx->program->scratch_offset, 0, true);
5881    emit_split_vector(ctx, dst, instr->num_components);
5882 }
5883
5884 void visit_store_scratch(isel_context *ctx, nir_intrinsic_instr *instr) {
5885    assert(instr->src[0].ssa->bit_size == 32 || instr->src[0].ssa->bit_size == 64);
5886    Builder bld(ctx->program, ctx->block);
5887    Temp rsrc = get_scratch_resource(ctx);
5888    Temp data = as_vgpr(ctx, get_ssa_temp(ctx, instr->src[0].ssa));
5889    Temp offset = as_vgpr(ctx, get_ssa_temp(ctx, instr->src[1].ssa));
5890
5891    unsigned elem_size_bytes = instr->src[0].ssa->bit_size / 8;
5892    unsigned writemask = nir_intrinsic_write_mask(instr);
5893
5894    while (writemask) {
5895       int start, count;
5896       u_bit_scan_consecutive_range(&writemask, &start, &count);
5897       int num_bytes = count * elem_size_bytes;
5898
5899       if (num_bytes > 16) {
5900          assert(elem_size_bytes == 8);
5901          writemask |= (((count - 2) << 1) - 1) << (start + 2);
5902          count = 2;
5903          num_bytes = 16;
5904       }
5905
5906       // TODO: check alignment of sub-dword stores
5907       // TODO: split 3 bytes. there is no store instruction for that
5908
5909       Temp write_data;
5910       if (count != instr->num_components) {
5911          aco_ptr<Pseudo_instruction> vec{create_instruction<Pseudo_instruction>(aco_opcode::p_create_vector, Format::PSEUDO, count, 1)};
5912          for (int i = 0; i < count; i++) {
5913             Temp elem = emit_extract_vector(ctx, data, start + i, RegClass(RegType::vgpr, elem_size_bytes / 4));
5914             vec->operands[i] = Operand(elem);
5915          }
5916          write_data = bld.tmp(RegClass(RegType::vgpr, count * elem_size_bytes / 4));
5917          vec->definitions[0] = Definition(write_data);
5918          ctx->block->instructions.emplace_back(std::move(vec));
5919       } else {
5920          write_data = data;
5921       }
5922
5923       aco_opcode op;
5924       switch (num_bytes) {
5925          case 4:
5926             op = aco_opcode::buffer_store_dword;
5927             break;
5928          case 8:
5929             op = aco_opcode::buffer_store_dwordx2;
5930             break;
5931          case 12:
5932             op = aco_opcode::buffer_store_dwordx3;
5933             break;
5934          case 16:
5935             op = aco_opcode::buffer_store_dwordx4;
5936             break;
5937          default:
5938             unreachable("Invalid data size for nir_intrinsic_store_scratch.");
5939       }
5940
5941       bld.mubuf(op, rsrc, offset, ctx->program->scratch_offset, write_data, start * elem_size_bytes, true);
5942    }
5943 }
5944
5945 void visit_load_sample_mask_in(isel_context *ctx, nir_intrinsic_instr *instr) {
5946    uint8_t log2_ps_iter_samples;
5947    if (ctx->program->info->ps.force_persample) {
5948       log2_ps_iter_samples =
5949          util_logbase2(ctx->options->key.fs.num_samples);
5950    } else {
5951       log2_ps_iter_samples = ctx->options->key.fs.log2_ps_iter_samples;
5952    }
5953
5954    /* The bit pattern matches that used by fixed function fragment
5955     * processing. */
5956    static const unsigned ps_iter_masks[] = {
5957       0xffff, /* not used */
5958       0x5555,
5959       0x1111,
5960       0x0101,
5961       0x0001,
5962    };
5963    assert(log2_ps_iter_samples < ARRAY_SIZE(ps_iter_masks));
5964
5965    Builder bld(ctx->program, ctx->block);
5966
5967    Temp sample_id = bld.vop3(aco_opcode::v_bfe_u32, bld.def(v1),
5968                              get_arg(ctx, ctx->args->ac.ancillary), Operand(8u), Operand(4u));
5969    Temp ps_iter_mask = bld.vop1(aco_opcode::v_mov_b32, bld.def(v1), Operand(ps_iter_masks[log2_ps_iter_samples]));
5970    Temp mask = bld.vop2(aco_opcode::v_lshlrev_b32, bld.def(v1), sample_id, ps_iter_mask);
5971    Temp dst = get_ssa_temp(ctx, &instr->dest.ssa);
5972    bld.vop2(aco_opcode::v_and_b32, Definition(dst), mask, get_arg(ctx, ctx->args->ac.sample_coverage));
5973 }
5974
5975 void visit_emit_vertex_with_counter(isel_context *ctx, nir_intrinsic_instr *instr) {
5976    Builder bld(ctx->program, ctx->block);
5977
5978    unsigned stream = nir_intrinsic_stream_id(instr);
5979    Temp next_vertex = as_vgpr(ctx, get_ssa_temp(ctx, instr->src[0].ssa));
5980    next_vertex = bld.v_mul_imm(bld.def(v1), next_vertex, 4u);
5981    nir_const_value *next_vertex_cv = nir_src_as_const_value(instr->src[0]);
5982
5983    /* get GSVS ring */
5984    Temp gsvs_ring = bld.smem(aco_opcode::s_load_dwordx4, bld.def(s4), ctx->program->private_segment_buffer, Operand(RING_GSVS_GS * 16u));
5985
5986    unsigned num_components =
5987       ctx->program->info->gs.num_stream_output_components[stream];
5988    assert(num_components);
5989
5990    unsigned stride = 4u * num_components * ctx->shader->info.gs.vertices_out;
5991    unsigned stream_offset = 0;
5992    for (unsigned i = 0; i < stream; i++) {
5993       unsigned prev_stride = 4u * ctx->program->info->gs.num_stream_output_components[i] * ctx->shader->info.gs.vertices_out;
5994       stream_offset += prev_stride * ctx->program->wave_size;
5995    }
5996
5997    /* Limit on the stride field for <= GFX7. */
5998    assert(stride < (1 << 14));
5999
6000    Temp gsvs_dwords[4];
6001    for (unsigned i = 0; i < 4; i++)
6002       gsvs_dwords[i] = bld.tmp(s1);
6003    bld.pseudo(aco_opcode::p_split_vector,
6004               Definition(gsvs_dwords[0]),
6005               Definition(gsvs_dwords[1]),
6006               Definition(gsvs_dwords[2]),
6007               Definition(gsvs_dwords[3]),
6008               gsvs_ring);
6009
6010    if (stream_offset) {
6011       Temp stream_offset_tmp = bld.copy(bld.def(s1), Operand(stream_offset));
6012
6013       Temp carry = bld.tmp(s1);
6014       gsvs_dwords[0] = bld.sop2(aco_opcode::s_add_u32, bld.def(s1), bld.scc(Definition(carry)), gsvs_dwords[0], stream_offset_tmp);
6015       gsvs_dwords[1] = bld.sop2(aco_opcode::s_addc_u32, bld.def(s1), bld.def(s1, scc), gsvs_dwords[1], Operand(0u), bld.scc(carry));
6016    }
6017
6018    gsvs_dwords[1] = bld.sop2(aco_opcode::s_or_b32, bld.def(s1), bld.def(s1, scc), gsvs_dwords[1], Operand(S_008F04_STRIDE(stride)));
6019    gsvs_dwords[2] = bld.copy(bld.def(s1), Operand((uint32_t)ctx->program->wave_size));
6020
6021    gsvs_ring = bld.pseudo(aco_opcode::p_create_vector, bld.def(s4),
6022                           gsvs_dwords[0], gsvs_dwords[1], gsvs_dwords[2], gsvs_dwords[3]);
6023
6024    unsigned offset = 0;
6025    for (unsigned i = 0; i <= VARYING_SLOT_VAR31; i++) {
6026       if (ctx->program->info->gs.output_streams[i] != stream)
6027          continue;
6028
6029       for (unsigned j = 0; j < 4; j++) {
6030          if (!(ctx->program->info->gs.output_usage_mask[i] & (1 << j)))
6031             continue;
6032
6033          if (ctx->outputs.mask[i] & (1 << j)) {
6034             Operand vaddr_offset = next_vertex_cv ? Operand(v1) : Operand(next_vertex);
6035             unsigned const_offset = (offset + (next_vertex_cv ? next_vertex_cv->u32 : 0u)) * 4u;
6036             if (const_offset >= 4096u) {
6037                if (vaddr_offset.isUndefined())
6038                   vaddr_offset = bld.copy(bld.def(v1), Operand(const_offset / 4096u * 4096u));
6039                else
6040                   vaddr_offset = bld.vadd32(bld.def(v1), Operand(const_offset / 4096u * 4096u), vaddr_offset);
6041                const_offset %= 4096u;
6042             }
6043
6044             aco_ptr<MTBUF_instruction> mtbuf{create_instruction<MTBUF_instruction>(aco_opcode::tbuffer_store_format_x, Format::MTBUF, 4, 0)};
6045             mtbuf->operands[0] = Operand(gsvs_ring);
6046             mtbuf->operands[1] = vaddr_offset;
6047             mtbuf->operands[2] = Operand(get_arg(ctx, ctx->args->gs2vs_offset));
6048             mtbuf->operands[3] = Operand(ctx->outputs.outputs[i][j]);
6049             mtbuf->offen = !vaddr_offset.isUndefined();
6050             mtbuf->dfmt = V_008F0C_BUF_DATA_FORMAT_32;
6051             mtbuf->nfmt = V_008F0C_BUF_NUM_FORMAT_UINT;
6052             mtbuf->offset = const_offset;
6053             mtbuf->glc = true;
6054             mtbuf->slc = true;
6055             mtbuf->barrier = barrier_gs_data;
6056             mtbuf->can_reorder = true;
6057             bld.insert(std::move(mtbuf));
6058          }
6059
6060          offset += ctx->shader->info.gs.vertices_out;
6061       }
6062
6063       /* outputs for the next vertex are undefined and keeping them around can
6064        * create invalid IR with control flow */
6065       ctx->outputs.mask[i] = 0;
6066    }
6067
6068    bld.sopp(aco_opcode::s_sendmsg, bld.m0(ctx->gs_wave_id), -1, sendmsg_gs(false, true, stream));
6069 }
6070
6071 Temp emit_boolean_reduce(isel_context *ctx, nir_op op, unsigned cluster_size, Temp src)
6072 {
6073    Builder bld(ctx->program, ctx->block);
6074
6075    if (cluster_size == 1) {
6076       return src;
6077    } if (op == nir_op_iand && cluster_size == 4) {
6078       //subgroupClusteredAnd(val, 4) -> ~wqm(exec & ~val)
6079       Temp tmp = bld.sop2(Builder::s_andn2, bld.def(bld.lm), bld.def(s1, scc), Operand(exec, bld.lm), src);
6080       return bld.sop1(Builder::s_not, bld.def(bld.lm), bld.def(s1, scc),
6081                       bld.sop1(Builder::s_wqm, bld.def(bld.lm), bld.def(s1, scc), tmp));
6082    } else if (op == nir_op_ior && cluster_size == 4) {
6083       //subgroupClusteredOr(val, 4) -> wqm(val & exec)
6084       return bld.sop1(Builder::s_wqm, bld.def(bld.lm), bld.def(s1, scc),
6085                       bld.sop2(Builder::s_and, bld.def(bld.lm), bld.def(s1, scc), src, Operand(exec, bld.lm)));
6086    } else if (op == nir_op_iand && cluster_size == ctx->program->wave_size) {
6087       //subgroupAnd(val) -> (exec & ~val) == 0
6088       Temp tmp = bld.sop2(Builder::s_andn2, bld.def(bld.lm), bld.def(s1, scc), Operand(exec, bld.lm), src).def(1).getTemp();
6089       Temp cond = bool_to_vector_condition(ctx, emit_wqm(ctx, tmp));
6090       return bld.sop1(Builder::s_not, bld.def(bld.lm), bld.def(s1, scc), cond);
6091    } else if (op == nir_op_ior && cluster_size == ctx->program->wave_size) {
6092       //subgroupOr(val) -> (val & exec) != 0
6093       Temp tmp = bld.sop2(Builder::s_and, bld.def(bld.lm), bld.def(s1, scc), src, Operand(exec, bld.lm)).def(1).getTemp();
6094       return bool_to_vector_condition(ctx, tmp);
6095    } else if (op == nir_op_ixor && cluster_size == ctx->program->wave_size) {
6096       //subgroupXor(val) -> s_bcnt1_i32_b64(val & exec) & 1
6097       Temp tmp = bld.sop2(Builder::s_and, bld.def(bld.lm), bld.def(s1, scc), src, Operand(exec, bld.lm));
6098       tmp = bld.sop1(Builder::s_bcnt1_i32, bld.def(s1), bld.def(s1, scc), tmp);
6099       tmp = bld.sop2(aco_opcode::s_and_b32, bld.def(s1), bld.def(s1, scc), tmp, Operand(1u)).def(1).getTemp();
6100       return bool_to_vector_condition(ctx, tmp);
6101    } else {
6102       //subgroupClustered{And,Or,Xor}(val, n) ->
6103       //lane_id = v_mbcnt_hi_u32_b32(-1, v_mbcnt_lo_u32_b32(-1, 0)) ;  just v_mbcnt_lo_u32_b32 on wave32
6104       //cluster_offset = ~(n - 1) & lane_id
6105       //cluster_mask = ((1 << n) - 1)
6106       //subgroupClusteredAnd():
6107       //   return ((val | ~exec) >> cluster_offset) & cluster_mask == cluster_mask
6108       //subgroupClusteredOr():
6109       //   return ((val & exec) >> cluster_offset) & cluster_mask != 0
6110       //subgroupClusteredXor():
6111       //   return v_bnt_u32_b32(((val & exec) >> cluster_offset) & cluster_mask, 0) & 1 != 0
6112       Temp lane_id = emit_mbcnt(ctx, bld.def(v1));
6113       Temp cluster_offset = bld.vop2(aco_opcode::v_and_b32, bld.def(v1), Operand(~uint32_t(cluster_size - 1)), lane_id);
6114
6115       Temp tmp;
6116       if (op == nir_op_iand)
6117          tmp = bld.sop2(Builder::s_orn2, bld.def(bld.lm), bld.def(s1, scc), src, Operand(exec, bld.lm));
6118       else
6119          tmp = bld.sop2(Builder::s_and, bld.def(bld.lm), bld.def(s1, scc), src, Operand(exec, bld.lm));
6120
6121       uint32_t cluster_mask = cluster_size == 32 ? -1 : (1u << cluster_size) - 1u;
6122
6123       if (ctx->program->chip_class <= GFX7)
6124          tmp = bld.vop3(aco_opcode::v_lshr_b64, bld.def(v2), tmp, cluster_offset);
6125       else if (ctx->program->wave_size == 64)
6126          tmp = bld.vop3(aco_opcode::v_lshrrev_b64, bld.def(v2), cluster_offset, tmp);
6127       else
6128          tmp = bld.vop2_e64(aco_opcode::v_lshrrev_b32, bld.def(v1), cluster_offset, tmp);
6129       tmp = emit_extract_vector(ctx, tmp, 0, v1);
6130       if (cluster_mask != 0xffffffff)
6131          tmp = bld.vop2(aco_opcode::v_and_b32, bld.def(v1), Operand(cluster_mask), tmp);
6132
6133       Definition cmp_def = Definition();
6134       if (op == nir_op_iand) {
6135          cmp_def = bld.vopc(aco_opcode::v_cmp_eq_u32, bld.def(bld.lm), Operand(cluster_mask), tmp).def(0);
6136       } else if (op == nir_op_ior) {
6137          cmp_def = bld.vopc(aco_opcode::v_cmp_lg_u32, bld.def(bld.lm), Operand(0u), tmp).def(0);
6138       } else if (op == nir_op_ixor) {
6139          tmp = bld.vop2(aco_opcode::v_and_b32, bld.def(v1), Operand(1u),
6140                         bld.vop3(aco_opcode::v_bcnt_u32_b32, bld.def(v1), tmp, Operand(0u)));
6141          cmp_def = bld.vopc(aco_opcode::v_cmp_lg_u32, bld.def(bld.lm), Operand(0u), tmp).def(0);
6142       }
6143       cmp_def.setHint(vcc);
6144       return cmp_def.getTemp();
6145    }
6146 }
6147
6148 Temp emit_boolean_exclusive_scan(isel_context *ctx, nir_op op, Temp src)
6149 {
6150    Builder bld(ctx->program, ctx->block);
6151
6152    //subgroupExclusiveAnd(val) -> mbcnt(exec & ~val) == 0
6153    //subgroupExclusiveOr(val) -> mbcnt(val & exec) != 0
6154    //subgroupExclusiveXor(val) -> mbcnt(val & exec) & 1 != 0
6155    Temp tmp;
6156    if (op == nir_op_iand)
6157       tmp = bld.sop2(Builder::s_andn2, bld.def(bld.lm), bld.def(s1, scc), Operand(exec, bld.lm), src);
6158    else
6159       tmp = bld.sop2(Builder::s_and, bld.def(s2), bld.def(s1, scc), src, Operand(exec, bld.lm));
6160
6161    Builder::Result lohi = bld.pseudo(aco_opcode::p_split_vector, bld.def(s1), bld.def(s1), tmp);
6162    Temp lo = lohi.def(0).getTemp();
6163    Temp hi = lohi.def(1).getTemp();
6164    Temp mbcnt = emit_mbcnt(ctx, bld.def(v1), Operand(lo), Operand(hi));
6165
6166    Definition cmp_def = Definition();
6167    if (op == nir_op_iand)
6168       cmp_def = bld.vopc(aco_opcode::v_cmp_eq_u32, bld.def(bld.lm), Operand(0u), mbcnt).def(0);
6169    else if (op == nir_op_ior)
6170       cmp_def = bld.vopc(aco_opcode::v_cmp_lg_u32, bld.def(bld.lm), Operand(0u), mbcnt).def(0);
6171    else if (op == nir_op_ixor)
6172       cmp_def = bld.vopc(aco_opcode::v_cmp_lg_u32, bld.def(bld.lm), Operand(0u),
6173                          bld.vop2(aco_opcode::v_and_b32, bld.def(v1), Operand(1u), mbcnt)).def(0);
6174    cmp_def.setHint(vcc);
6175    return cmp_def.getTemp();
6176 }
6177
6178 Temp emit_boolean_inclusive_scan(isel_context *ctx, nir_op op, Temp src)
6179 {
6180    Builder bld(ctx->program, ctx->block);
6181
6182    //subgroupInclusiveAnd(val) -> subgroupExclusiveAnd(val) && val
6183    //subgroupInclusiveOr(val) -> subgroupExclusiveOr(val) || val
6184    //subgroupInclusiveXor(val) -> subgroupExclusiveXor(val) ^^ val
6185    Temp tmp = emit_boolean_exclusive_scan(ctx, op, src);
6186    if (op == nir_op_iand)
6187       return bld.sop2(Builder::s_and, bld.def(bld.lm), bld.def(s1, scc), tmp, src);
6188    else if (op == nir_op_ior)
6189       return bld.sop2(Builder::s_or, bld.def(bld.lm), bld.def(s1, scc), tmp, src);
6190    else if (op == nir_op_ixor)
6191       return bld.sop2(Builder::s_xor, bld.def(bld.lm), bld.def(s1, scc), tmp, src);
6192
6193    assert(false);
6194    return Temp();
6195 }
6196
6197 void emit_uniform_subgroup(isel_context *ctx, nir_intrinsic_instr *instr, Temp src)
6198 {
6199    Builder bld(ctx->program, ctx->block);
6200    Definition dst(get_ssa_temp(ctx, &instr->dest.ssa));
6201    if (src.regClass().type() == RegType::vgpr) {
6202       bld.pseudo(aco_opcode::p_as_uniform, dst, src);
6203    } else if (src.regClass() == s1) {
6204       bld.sop1(aco_opcode::s_mov_b32, dst, src);
6205    } else if (src.regClass() == s2) {
6206       bld.sop1(aco_opcode::s_mov_b64, dst, src);
6207    } else {
6208       fprintf(stderr, "Unimplemented NIR instr bit size: ");
6209       nir_print_instr(&instr->instr, stderr);
6210       fprintf(stderr, "\n");
6211    }
6212 }
6213
6214 void emit_interp_center(isel_context *ctx, Temp dst, Temp pos1, Temp pos2)
6215 {
6216    Builder bld(ctx->program, ctx->block);
6217    Temp persp_center = get_arg(ctx, ctx->args->ac.persp_center);
6218    Temp p1 = emit_extract_vector(ctx, persp_center, 0, v1);
6219    Temp p2 = emit_extract_vector(ctx, persp_center, 1, v1);
6220
6221    Temp ddx_1, ddx_2, ddy_1, ddy_2;
6222    uint32_t dpp_ctrl0 = dpp_quad_perm(0, 0, 0, 0);
6223    uint32_t dpp_ctrl1 = dpp_quad_perm(1, 1, 1, 1);
6224    uint32_t dpp_ctrl2 = dpp_quad_perm(2, 2, 2, 2);
6225
6226    /* Build DD X/Y */
6227    if (ctx->program->chip_class >= GFX8) {
6228       Temp tl_1 = bld.vop1_dpp(aco_opcode::v_mov_b32, bld.def(v1), p1, dpp_ctrl0);
6229       ddx_1 = bld.vop2_dpp(aco_opcode::v_sub_f32, bld.def(v1), p1, tl_1, dpp_ctrl1);
6230       ddy_1 = bld.vop2_dpp(aco_opcode::v_sub_f32, bld.def(v1), p1, tl_1, dpp_ctrl2);
6231       Temp tl_2 = bld.vop1_dpp(aco_opcode::v_mov_b32, bld.def(v1), p2, dpp_ctrl0);
6232       ddx_2 = bld.vop2_dpp(aco_opcode::v_sub_f32, bld.def(v1), p2, tl_2, dpp_ctrl1);
6233       ddy_2 = bld.vop2_dpp(aco_opcode::v_sub_f32, bld.def(v1), p2, tl_2, dpp_ctrl2);
6234    } else {
6235       Temp tl_1 = bld.ds(aco_opcode::ds_swizzle_b32, bld.def(v1), p1, (1 << 15) | dpp_ctrl0);
6236       ddx_1 = bld.ds(aco_opcode::ds_swizzle_b32, bld.def(v1), p1, (1 << 15) | dpp_ctrl1);
6237       ddx_1 = bld.vop2(aco_opcode::v_sub_f32, bld.def(v1), ddx_1, tl_1);
6238       ddx_2 = bld.ds(aco_opcode::ds_swizzle_b32, bld.def(v1), p1, (1 << 15) | dpp_ctrl2);
6239       ddx_2 = bld.vop2(aco_opcode::v_sub_f32, bld.def(v1), ddx_2, tl_1);
6240       Temp tl_2 = bld.ds(aco_opcode::ds_swizzle_b32, bld.def(v1), p2, (1 << 15) | dpp_ctrl0);
6241       ddy_1 = bld.ds(aco_opcode::ds_swizzle_b32, bld.def(v1), p2, (1 << 15) | dpp_ctrl1);
6242       ddy_1 = bld.vop2(aco_opcode::v_sub_f32, bld.def(v1), ddy_1, tl_2);
6243       ddy_2 = bld.ds(aco_opcode::ds_swizzle_b32, bld.def(v1), p2, (1 << 15) | dpp_ctrl2);
6244       ddy_2 = bld.vop2(aco_opcode::v_sub_f32, bld.def(v1), ddy_2, tl_2);
6245    }
6246
6247    /* res_k = p_k + ddx_k * pos1 + ddy_k * pos2 */
6248    Temp tmp1 = bld.vop3(aco_opcode::v_mad_f32, bld.def(v1), ddx_1, pos1, p1);
6249    Temp tmp2 = bld.vop3(aco_opcode::v_mad_f32, bld.def(v1), ddx_2, pos1, p2);
6250    tmp1 = bld.vop3(aco_opcode::v_mad_f32, bld.def(v1), ddy_1, pos2, tmp1);
6251    tmp2 = bld.vop3(aco_opcode::v_mad_f32, bld.def(v1), ddy_2, pos2, tmp2);
6252    Temp wqm1 = bld.tmp(v1);
6253    emit_wqm(ctx, tmp1, wqm1, true);
6254    Temp wqm2 = bld.tmp(v1);
6255    emit_wqm(ctx, tmp2, wqm2, true);
6256    bld.pseudo(aco_opcode::p_create_vector, Definition(dst), wqm1, wqm2);
6257    return;
6258 }
6259
6260 void visit_intrinsic(isel_context *ctx, nir_intrinsic_instr *instr)
6261 {
6262    Builder bld(ctx->program, ctx->block);
6263    switch(instr->intrinsic) {
6264    case nir_intrinsic_load_barycentric_sample:
6265    case nir_intrinsic_load_barycentric_pixel:
6266    case nir_intrinsic_load_barycentric_centroid: {
6267       glsl_interp_mode mode = (glsl_interp_mode)nir_intrinsic_interp_mode(instr);
6268       Temp bary = Temp(0, s2);
6269       switch (mode) {
6270       case INTERP_MODE_SMOOTH:
6271       case INTERP_MODE_NONE:
6272          if (instr->intrinsic == nir_intrinsic_load_barycentric_pixel)
6273             bary = get_arg(ctx, ctx->args->ac.persp_center);
6274          else if (instr->intrinsic == nir_intrinsic_load_barycentric_centroid)
6275             bary = ctx->persp_centroid;
6276          else if (instr->intrinsic == nir_intrinsic_load_barycentric_sample)
6277             bary = get_arg(ctx, ctx->args->ac.persp_sample);
6278          break;
6279       case INTERP_MODE_NOPERSPECTIVE:
6280          if (instr->intrinsic == nir_intrinsic_load_barycentric_pixel)
6281             bary = get_arg(ctx, ctx->args->ac.linear_center);
6282          else if (instr->intrinsic == nir_intrinsic_load_barycentric_centroid)
6283             bary = ctx->linear_centroid;
6284          else if (instr->intrinsic == nir_intrinsic_load_barycentric_sample)
6285             bary = get_arg(ctx, ctx->args->ac.linear_sample);
6286          break;
6287       default:
6288          break;
6289       }
6290       Temp dst = get_ssa_temp(ctx, &instr->dest.ssa);
6291       Temp p1 = emit_extract_vector(ctx, bary, 0, v1);
6292       Temp p2 = emit_extract_vector(ctx, bary, 1, v1);
6293       bld.pseudo(aco_opcode::p_create_vector, Definition(dst),
6294                  Operand(p1), Operand(p2));
6295       emit_split_vector(ctx, dst, 2);
6296       break;
6297    }
6298    case nir_intrinsic_load_barycentric_model: {
6299       Temp model = get_arg(ctx, ctx->args->ac.pull_model);
6300
6301       Temp dst = get_ssa_temp(ctx, &instr->dest.ssa);
6302       Temp p1 = emit_extract_vector(ctx, model, 0, v1);
6303       Temp p2 = emit_extract_vector(ctx, model, 1, v1);
6304       Temp p3 = emit_extract_vector(ctx, model, 2, v1);
6305       bld.pseudo(aco_opcode::p_create_vector, Definition(dst),
6306                  Operand(p1), Operand(p2), Operand(p3));
6307       emit_split_vector(ctx, dst, 3);
6308       break;
6309    }
6310    case nir_intrinsic_load_barycentric_at_sample: {
6311       uint32_t sample_pos_offset = RING_PS_SAMPLE_POSITIONS * 16;
6312       switch (ctx->options->key.fs.num_samples) {
6313          case 2: sample_pos_offset += 1 << 3; break;
6314          case 4: sample_pos_offset += 3 << 3; break;
6315          case 8: sample_pos_offset += 7 << 3; break;
6316          default: break;
6317       }
6318       Temp sample_pos;
6319       Temp addr = get_ssa_temp(ctx, instr->src[0].ssa);
6320       nir_const_value* const_addr = nir_src_as_const_value(instr->src[0]);
6321       Temp private_segment_buffer = ctx->program->private_segment_buffer;
6322       if (addr.type() == RegType::sgpr) {
6323          Operand offset;
6324          if (const_addr) {
6325             sample_pos_offset += const_addr->u32 << 3;
6326             offset = Operand(sample_pos_offset);
6327          } else if (ctx->options->chip_class >= GFX9) {
6328             offset = bld.sop2(aco_opcode::s_lshl3_add_u32, bld.def(s1), bld.def(s1, scc), addr, Operand(sample_pos_offset));
6329          } else {
6330             offset = bld.sop2(aco_opcode::s_lshl_b32, bld.def(s1), bld.def(s1, scc), addr, Operand(3u));
6331             offset = bld.sop2(aco_opcode::s_add_u32, bld.def(s1), bld.def(s1, scc), addr, Operand(sample_pos_offset));
6332          }
6333
6334          Operand off = bld.copy(bld.def(s1), Operand(offset));
6335          sample_pos = bld.smem(aco_opcode::s_load_dwordx2, bld.def(s2), private_segment_buffer, off);
6336
6337       } else if (ctx->options->chip_class >= GFX9) {
6338          addr = bld.vop2(aco_opcode::v_lshlrev_b32, bld.def(v1), Operand(3u), addr);
6339          sample_pos = bld.global(aco_opcode::global_load_dwordx2, bld.def(v2), addr, private_segment_buffer, sample_pos_offset);
6340       } else if (ctx->options->chip_class >= GFX7) {
6341          /* addr += private_segment_buffer + sample_pos_offset */
6342          Temp tmp0 = bld.tmp(s1);
6343          Temp tmp1 = bld.tmp(s1);
6344          bld.pseudo(aco_opcode::p_split_vector, Definition(tmp0), Definition(tmp1), private_segment_buffer);
6345          Definition scc_tmp = bld.def(s1, scc);
6346          tmp0 = bld.sop2(aco_opcode::s_add_u32, bld.def(s1), scc_tmp, tmp0, Operand(sample_pos_offset));
6347          tmp1 = bld.sop2(aco_opcode::s_addc_u32, bld.def(s1), bld.def(s1, scc), tmp1, Operand(0u), bld.scc(scc_tmp.getTemp()));
6348          addr = bld.vop2(aco_opcode::v_lshlrev_b32, bld.def(v1), Operand(3u), addr);
6349          Temp pck0 = bld.tmp(v1);
6350          Temp carry = bld.vadd32(Definition(pck0), tmp0, addr, true).def(1).getTemp();
6351          tmp1 = as_vgpr(ctx, tmp1);
6352          Temp pck1 = bld.vop2_e64(aco_opcode::v_addc_co_u32, bld.def(v1), bld.hint_vcc(bld.def(bld.lm)), tmp1, Operand(0u), carry);
6353          addr = bld.pseudo(aco_opcode::p_create_vector, bld.def(v2), pck0, pck1);
6354
6355          /* sample_pos = flat_load_dwordx2 addr */
6356          sample_pos = bld.flat(aco_opcode::flat_load_dwordx2, bld.def(v2), addr, Operand(s1));
6357       } else {
6358          assert(ctx->options->chip_class == GFX6);
6359
6360          uint32_t rsrc_conf = S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
6361                               S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32);
6362          Temp rsrc = bld.pseudo(aco_opcode::p_create_vector, bld.def(s4), private_segment_buffer, Operand(0u), Operand(rsrc_conf));
6363
6364          addr = bld.vop2(aco_opcode::v_lshlrev_b32, bld.def(v1), Operand(3u), addr);
6365          addr = bld.pseudo(aco_opcode::p_create_vector, bld.def(v2), addr, Operand(0u));
6366
6367          sample_pos = bld.tmp(v2);
6368
6369          aco_ptr<MUBUF_instruction> load{create_instruction<MUBUF_instruction>(aco_opcode::buffer_load_dwordx2, Format::MUBUF, 3, 1)};
6370          load->definitions[0] = Definition(sample_pos);
6371          load->operands[0] = Operand(rsrc);
6372          load->operands[1] = Operand(addr);
6373          load->operands[2] = Operand(0u);
6374          load->offset = sample_pos_offset;
6375          load->offen = 0;
6376          load->addr64 = true;
6377          load->glc = false;
6378          load->dlc = false;
6379          load->disable_wqm = false;
6380          load->barrier = barrier_none;
6381          load->can_reorder = true;
6382          ctx->block->instructions.emplace_back(std::move(load));
6383       }
6384
6385       /* sample_pos -= 0.5 */
6386       Temp pos1 = bld.tmp(RegClass(sample_pos.type(), 1));
6387       Temp pos2 = bld.tmp(RegClass(sample_pos.type(), 1));
6388       bld.pseudo(aco_opcode::p_split_vector, Definition(pos1), Definition(pos2), sample_pos);
6389       pos1 = bld.vop2_e64(aco_opcode::v_sub_f32, bld.def(v1), pos1, Operand(0x3f000000u));
6390       pos2 = bld.vop2_e64(aco_opcode::v_sub_f32, bld.def(v1), pos2, Operand(0x3f000000u));
6391
6392       emit_interp_center(ctx, get_ssa_temp(ctx, &instr->dest.ssa), pos1, pos2);
6393       break;
6394    }
6395    case nir_intrinsic_load_barycentric_at_offset: {
6396       Temp offset = get_ssa_temp(ctx, instr->src[0].ssa);
6397       RegClass rc = RegClass(offset.type(), 1);
6398       Temp pos1 = bld.tmp(rc), pos2 = bld.tmp(rc);
6399       bld.pseudo(aco_opcode::p_split_vector, Definition(pos1), Definition(pos2), offset);
6400       emit_interp_center(ctx, get_ssa_temp(ctx, &instr->dest.ssa), pos1, pos2);
6401       break;
6402    }
6403    case nir_intrinsic_load_front_face: {
6404       bld.vopc(aco_opcode::v_cmp_lg_u32, Definition(get_ssa_temp(ctx, &instr->dest.ssa)),
6405                Operand(0u), get_arg(ctx, ctx->args->ac.front_face)).def(0).setHint(vcc);
6406       break;
6407    }
6408    case nir_intrinsic_load_view_index: {
6409       if (ctx->stage & (sw_vs | sw_gs | sw_tcs | sw_tes)) {
6410          Temp dst = get_ssa_temp(ctx, &instr->dest.ssa);
6411          bld.copy(Definition(dst), Operand(get_arg(ctx, ctx->args->ac.view_index)));
6412          break;
6413       }
6414
6415       /* fallthrough */
6416    }
6417    case nir_intrinsic_load_layer_id: {
6418       unsigned idx = nir_intrinsic_base(instr);
6419       bld.vintrp(aco_opcode::v_interp_mov_f32, Definition(get_ssa_temp(ctx, &instr->dest.ssa)),
6420                  Operand(2u), bld.m0(get_arg(ctx, ctx->args->ac.prim_mask)), idx, 0);
6421       break;
6422    }
6423    case nir_intrinsic_load_frag_coord: {
6424       emit_load_frag_coord(ctx, get_ssa_temp(ctx, &instr->dest.ssa), 4);
6425       break;
6426    }
6427    case nir_intrinsic_load_sample_pos: {
6428       Temp posx = get_arg(ctx, ctx->args->ac.frag_pos[0]);
6429       Temp posy = get_arg(ctx, ctx->args->ac.frag_pos[1]);
6430       bld.pseudo(aco_opcode::p_create_vector, Definition(get_ssa_temp(ctx, &instr->dest.ssa)),
6431                  posx.id() ? bld.vop1(aco_opcode::v_fract_f32, bld.def(v1), posx) : Operand(0u),
6432                  posy.id() ? bld.vop1(aco_opcode::v_fract_f32, bld.def(v1), posy) : Operand(0u));
6433       break;
6434    }
6435    case nir_intrinsic_load_tess_coord:
6436       visit_load_tess_coord(ctx, instr);
6437       break;
6438    case nir_intrinsic_load_interpolated_input:
6439       visit_load_interpolated_input(ctx, instr);
6440       break;
6441    case nir_intrinsic_store_output:
6442       visit_store_output(ctx, instr);
6443       break;
6444    case nir_intrinsic_load_input:
6445    case nir_intrinsic_load_input_vertex:
6446       visit_load_input(ctx, instr);
6447       break;
6448    case nir_intrinsic_load_per_vertex_input:
6449       visit_load_per_vertex_input(ctx, instr);
6450       break;
6451    case nir_intrinsic_load_ubo:
6452       visit_load_ubo(ctx, instr);
6453       break;
6454    case nir_intrinsic_load_push_constant:
6455       visit_load_push_constant(ctx, instr);
6456       break;
6457    case nir_intrinsic_load_constant:
6458       visit_load_constant(ctx, instr);
6459       break;
6460    case nir_intrinsic_vulkan_resource_index:
6461       visit_load_resource(ctx, instr);
6462       break;
6463    case nir_intrinsic_discard:
6464       visit_discard(ctx, instr);
6465       break;
6466    case nir_intrinsic_discard_if:
6467       visit_discard_if(ctx, instr);
6468       break;
6469    case nir_intrinsic_load_shared:
6470       visit_load_shared(ctx, instr);
6471       break;
6472    case nir_intrinsic_store_shared:
6473       visit_store_shared(ctx, instr);
6474       break;
6475    case nir_intrinsic_shared_atomic_add:
6476    case nir_intrinsic_shared_atomic_imin:
6477    case nir_intrinsic_shared_atomic_umin:
6478    case nir_intrinsic_shared_atomic_imax:
6479    case nir_intrinsic_shared_atomic_umax:
6480    case nir_intrinsic_shared_atomic_and:
6481    case nir_intrinsic_shared_atomic_or:
6482    case nir_intrinsic_shared_atomic_xor:
6483    case nir_intrinsic_shared_atomic_exchange:
6484    case nir_intrinsic_shared_atomic_comp_swap:
6485       visit_shared_atomic(ctx, instr);
6486       break;
6487    case nir_intrinsic_image_deref_load:
6488       visit_image_load(ctx, instr);
6489       break;
6490    case nir_intrinsic_image_deref_store:
6491       visit_image_store(ctx, instr);
6492       break;
6493    case nir_intrinsic_image_deref_atomic_add:
6494    case nir_intrinsic_image_deref_atomic_umin:
6495    case nir_intrinsic_image_deref_atomic_imin:
6496    case nir_intrinsic_image_deref_atomic_umax:
6497    case nir_intrinsic_image_deref_atomic_imax:
6498    case nir_intrinsic_image_deref_atomic_and:
6499    case nir_intrinsic_image_deref_atomic_or:
6500    case nir_intrinsic_image_deref_atomic_xor:
6501    case nir_intrinsic_image_deref_atomic_exchange:
6502    case nir_intrinsic_image_deref_atomic_comp_swap:
6503       visit_image_atomic(ctx, instr);
6504       break;
6505    case nir_intrinsic_image_deref_size:
6506       visit_image_size(ctx, instr);
6507       break;
6508    case nir_intrinsic_load_ssbo:
6509       visit_load_ssbo(ctx, instr);
6510       break;
6511    case nir_intrinsic_store_ssbo:
6512       visit_store_ssbo(ctx, instr);
6513       break;
6514    case nir_intrinsic_load_global:
6515       visit_load_global(ctx, instr);
6516       break;
6517    case nir_intrinsic_store_global:
6518       visit_store_global(ctx, instr);
6519       break;
6520    case nir_intrinsic_global_atomic_add:
6521    case nir_intrinsic_global_atomic_imin:
6522    case nir_intrinsic_global_atomic_umin:
6523    case nir_intrinsic_global_atomic_imax:
6524    case nir_intrinsic_global_atomic_umax:
6525    case nir_intrinsic_global_atomic_and:
6526    case nir_intrinsic_global_atomic_or:
6527    case nir_intrinsic_global_atomic_xor:
6528    case nir_intrinsic_global_atomic_exchange:
6529    case nir_intrinsic_global_atomic_comp_swap:
6530       visit_global_atomic(ctx, instr);
6531       break;
6532    case nir_intrinsic_ssbo_atomic_add:
6533    case nir_intrinsic_ssbo_atomic_imin:
6534    case nir_intrinsic_ssbo_atomic_umin:
6535    case nir_intrinsic_ssbo_atomic_imax:
6536    case nir_intrinsic_ssbo_atomic_umax:
6537    case nir_intrinsic_ssbo_atomic_and:
6538    case nir_intrinsic_ssbo_atomic_or:
6539    case nir_intrinsic_ssbo_atomic_xor:
6540    case nir_intrinsic_ssbo_atomic_exchange:
6541    case nir_intrinsic_ssbo_atomic_comp_swap:
6542       visit_atomic_ssbo(ctx, instr);
6543       break;
6544    case nir_intrinsic_load_scratch:
6545       visit_load_scratch(ctx, instr);
6546       break;
6547    case nir_intrinsic_store_scratch:
6548       visit_store_scratch(ctx, instr);
6549       break;
6550    case nir_intrinsic_get_buffer_size:
6551       visit_get_buffer_size(ctx, instr);
6552       break;
6553    case nir_intrinsic_control_barrier: {
6554       if (ctx->program->chip_class == GFX6 && ctx->shader->info.stage == MESA_SHADER_TESS_CTRL) {
6555          /* GFX6 only (thanks to a hw bug workaround):
6556           * The real barrier instruction isn’t needed, because an entire patch
6557           * always fits into a single wave.
6558           */
6559          break;
6560       }
6561
6562       if (ctx->shader->info.stage == MESA_SHADER_COMPUTE) {
6563          unsigned* bsize = ctx->program->info->cs.block_size;
6564          unsigned workgroup_size = bsize[0] * bsize[1] * bsize[2];
6565          if (workgroup_size > ctx->program->wave_size)
6566             bld.sopp(aco_opcode::s_barrier);
6567       } else if (ctx->shader->info.stage == MESA_SHADER_TESS_CTRL) {
6568          /* For each patch provided during rendering, n TCS shader invocations will be processed,
6569           * where n is the number of vertices in the output patch.
6570           */
6571          unsigned workgroup_size = ctx->tcs_num_patches * ctx->shader->info.tess.tcs_vertices_out;
6572          if (workgroup_size > ctx->program->wave_size)
6573             bld.sopp(aco_opcode::s_barrier);
6574       } else {
6575          /* We don't know the workgroup size, so always emit the s_barrier. */
6576          bld.sopp(aco_opcode::s_barrier);
6577       }
6578
6579       break;
6580    }
6581    case nir_intrinsic_memory_barrier_tcs_patch:
6582    case nir_intrinsic_group_memory_barrier:
6583    case nir_intrinsic_memory_barrier:
6584    case nir_intrinsic_memory_barrier_buffer:
6585    case nir_intrinsic_memory_barrier_image:
6586    case nir_intrinsic_memory_barrier_shared:
6587       emit_memory_barrier(ctx, instr);
6588       break;
6589    case nir_intrinsic_load_num_work_groups: {
6590       Temp dst = get_ssa_temp(ctx, &instr->dest.ssa);
6591       bld.copy(Definition(dst), Operand(get_arg(ctx, ctx->args->ac.num_work_groups)));
6592       emit_split_vector(ctx, dst, 3);
6593       break;
6594    }
6595    case nir_intrinsic_load_local_invocation_id: {
6596       Temp dst = get_ssa_temp(ctx, &instr->dest.ssa);
6597       bld.copy(Definition(dst), Operand(get_arg(ctx, ctx->args->ac.local_invocation_ids)));
6598       emit_split_vector(ctx, dst, 3);
6599       break;
6600    }
6601    case nir_intrinsic_load_work_group_id: {
6602       Temp dst = get_ssa_temp(ctx, &instr->dest.ssa);
6603       struct ac_arg *args = ctx->args->ac.workgroup_ids;
6604       bld.pseudo(aco_opcode::p_create_vector, Definition(dst),
6605                  args[0].used ? Operand(get_arg(ctx, args[0])) : Operand(0u),
6606                  args[1].used ? Operand(get_arg(ctx, args[1])) : Operand(0u),
6607                  args[2].used ? Operand(get_arg(ctx, args[2])) : Operand(0u));
6608       emit_split_vector(ctx, dst, 3);
6609       break;
6610    }
6611    case nir_intrinsic_load_local_invocation_index: {
6612       Temp id = emit_mbcnt(ctx, bld.def(v1));
6613
6614       /* The tg_size bits [6:11] contain the subgroup id,
6615        * we need this multiplied by the wave size, and then OR the thread id to it.
6616        */
6617       if (ctx->program->wave_size == 64) {
6618          /* After the s_and the bits are already multiplied by 64 (left shifted by 6) so we can just feed that to v_or */
6619          Temp tg_num = bld.sop2(aco_opcode::s_and_b32, bld.def(s1), bld.def(s1, scc), Operand(0xfc0u),
6620                                 get_arg(ctx, ctx->args->ac.tg_size));
6621          bld.vop2(aco_opcode::v_or_b32, Definition(get_ssa_temp(ctx, &instr->dest.ssa)), tg_num, id);
6622       } else {
6623          /* Extract the bit field and multiply the result by 32 (left shift by 5), then do the OR  */
6624          Temp tg_num = bld.sop2(aco_opcode::s_bfe_u32, bld.def(s1), bld.def(s1, scc),
6625                                 get_arg(ctx, ctx->args->ac.tg_size), Operand(0x6u | (0x6u << 16)));
6626          bld.vop3(aco_opcode::v_lshl_or_b32, Definition(get_ssa_temp(ctx, &instr->dest.ssa)), tg_num, Operand(0x5u), id);
6627       }
6628       break;
6629    }
6630    case nir_intrinsic_load_subgroup_id: {
6631       if (ctx->stage == compute_cs) {
6632          bld.sop2(aco_opcode::s_bfe_u32, Definition(get_ssa_temp(ctx, &instr->dest.ssa)), bld.def(s1, scc),
6633                   get_arg(ctx, ctx->args->ac.tg_size), Operand(0x6u | (0x6u << 16)));
6634       } else {
6635          bld.sop1(aco_opcode::s_mov_b32, Definition(get_ssa_temp(ctx, &instr->dest.ssa)), Operand(0x0u));
6636       }
6637       break;
6638    }
6639    case nir_intrinsic_load_subgroup_invocation: {
6640       emit_mbcnt(ctx, Definition(get_ssa_temp(ctx, &instr->dest.ssa)));
6641       break;
6642    }
6643    case nir_intrinsic_load_num_subgroups: {
6644       if (ctx->stage == compute_cs)
6645          bld.sop2(aco_opcode::s_and_b32, Definition(get_ssa_temp(ctx, &instr->dest.ssa)), bld.def(s1, scc), Operand(0x3fu),
6646                   get_arg(ctx, ctx->args->ac.tg_size));
6647       else
6648          bld.sop1(aco_opcode::s_mov_b32, Definition(get_ssa_temp(ctx, &instr->dest.ssa)), Operand(0x1u));
6649       break;
6650    }
6651    case nir_intrinsic_ballot: {
6652       Temp src = get_ssa_temp(ctx, instr->src[0].ssa);
6653       Temp dst = get_ssa_temp(ctx, &instr->dest.ssa);
6654       Definition tmp = bld.def(dst.regClass());
6655       Definition lanemask_tmp = dst.size() == bld.lm.size() ? tmp : bld.def(src.regClass());
6656       if (instr->src[0].ssa->bit_size == 1) {
6657          assert(src.regClass() == bld.lm);
6658          bld.sop2(Builder::s_and, lanemask_tmp, bld.def(s1, scc), Operand(exec, bld.lm), src);
6659       } else if (instr->src[0].ssa->bit_size == 32 && src.regClass() == v1) {
6660          bld.vopc(aco_opcode::v_cmp_lg_u32, lanemask_tmp, Operand(0u), src);
6661       } else if (instr->src[0].ssa->bit_size == 64 && src.regClass() == v2) {
6662          bld.vopc(aco_opcode::v_cmp_lg_u64, lanemask_tmp, Operand(0u), src);
6663       } else {
6664          fprintf(stderr, "Unimplemented NIR instr bit size: ");
6665          nir_print_instr(&instr->instr, stderr);
6666          fprintf(stderr, "\n");
6667       }
6668       if (dst.size() != bld.lm.size()) {
6669          /* Wave32 with ballot size set to 64 */
6670          bld.pseudo(aco_opcode::p_create_vector, Definition(tmp), lanemask_tmp.getTemp(), Operand(0u));
6671       }
6672       emit_wqm(ctx, tmp.getTemp(), dst);
6673       break;
6674    }
6675    case nir_intrinsic_shuffle:
6676    case nir_intrinsic_read_invocation: {
6677       Temp src = get_ssa_temp(ctx, instr->src[0].ssa);
6678       if (!ctx->divergent_vals[instr->src[0].ssa->index]) {
6679          emit_uniform_subgroup(ctx, instr, src);
6680       } else {
6681          Temp tid = get_ssa_temp(ctx, instr->src[1].ssa);
6682          if (instr->intrinsic == nir_intrinsic_read_invocation || !ctx->divergent_vals[instr->src[1].ssa->index])
6683             tid = bld.as_uniform(tid);
6684          Temp dst = get_ssa_temp(ctx, &instr->dest.ssa);
6685          if (src.regClass() == v1) {
6686             emit_wqm(ctx, emit_bpermute(ctx, bld, tid, src), dst);
6687          } else if (src.regClass() == v2) {
6688             Temp lo = bld.tmp(v1), hi = bld.tmp(v1);
6689             bld.pseudo(aco_opcode::p_split_vector, Definition(lo), Definition(hi), src);
6690             lo = emit_wqm(ctx, emit_bpermute(ctx, bld, tid, lo));
6691             hi = emit_wqm(ctx, emit_bpermute(ctx, bld, tid, hi));
6692             bld.pseudo(aco_opcode::p_create_vector, Definition(dst), lo, hi);
6693             emit_split_vector(ctx, dst, 2);
6694          } else if (instr->dest.ssa.bit_size == 1 && tid.regClass() == s1) {
6695             assert(src.regClass() == bld.lm);
6696             Temp tmp = bld.sopc(Builder::s_bitcmp1, bld.def(s1, scc), src, tid);
6697             bool_to_vector_condition(ctx, emit_wqm(ctx, tmp), dst);
6698          } else if (instr->dest.ssa.bit_size == 1 && tid.regClass() == v1) {
6699             assert(src.regClass() == bld.lm);
6700             Temp tmp;
6701             if (ctx->program->chip_class <= GFX7)
6702                tmp = bld.vop3(aco_opcode::v_lshr_b64, bld.def(v2), src, tid);
6703             else if (ctx->program->wave_size == 64)
6704                tmp = bld.vop3(aco_opcode::v_lshrrev_b64, bld.def(v2), tid, src);
6705             else
6706                tmp = bld.vop2_e64(aco_opcode::v_lshrrev_b32, bld.def(v1), tid, src);
6707             tmp = emit_extract_vector(ctx, tmp, 0, v1);
6708             tmp = bld.vop2(aco_opcode::v_and_b32, bld.def(v1), Operand(1u), tmp);
6709             emit_wqm(ctx, bld.vopc(aco_opcode::v_cmp_lg_u32, bld.def(bld.lm), Operand(0u), tmp), dst);
6710          } else {
6711             fprintf(stderr, "Unimplemented NIR instr bit size: ");
6712             nir_print_instr(&instr->instr, stderr);
6713             fprintf(stderr, "\n");
6714          }
6715       }
6716       break;
6717    }
6718    case nir_intrinsic_load_sample_id: {
6719       bld.vop3(aco_opcode::v_bfe_u32, Definition(get_ssa_temp(ctx, &instr->dest.ssa)),
6720                get_arg(ctx, ctx->args->ac.ancillary), Operand(8u), Operand(4u));
6721       break;
6722    }
6723    case nir_intrinsic_load_sample_mask_in: {
6724       visit_load_sample_mask_in(ctx, instr);
6725       break;
6726    }
6727    case nir_intrinsic_read_first_invocation: {
6728       Temp src = get_ssa_temp(ctx, instr->src[0].ssa);
6729       Temp dst = get_ssa_temp(ctx, &instr->dest.ssa);
6730       if (src.regClass() == v1) {
6731          emit_wqm(ctx,
6732                   bld.vop1(aco_opcode::v_readfirstlane_b32, bld.def(s1), src),
6733                   dst);
6734       } else if (src.regClass() == v2) {
6735          Temp lo = bld.tmp(v1), hi = bld.tmp(v1);
6736          bld.pseudo(aco_opcode::p_split_vector, Definition(lo), Definition(hi), src);
6737          lo = emit_wqm(ctx, bld.vop1(aco_opcode::v_readfirstlane_b32, bld.def(s1), lo));
6738          hi = emit_wqm(ctx, bld.vop1(aco_opcode::v_readfirstlane_b32, bld.def(s1), hi));
6739          bld.pseudo(aco_opcode::p_create_vector, Definition(dst), lo, hi);
6740          emit_split_vector(ctx, dst, 2);
6741       } else if (instr->dest.ssa.bit_size == 1) {
6742          assert(src.regClass() == bld.lm);
6743          Temp tmp = bld.sopc(Builder::s_bitcmp1, bld.def(s1, scc), src,
6744                              bld.sop1(Builder::s_ff1_i32, bld.def(s1), Operand(exec, bld.lm)));
6745          bool_to_vector_condition(ctx, emit_wqm(ctx, tmp), dst);
6746       } else if (src.regClass() == s1) {
6747          bld.sop1(aco_opcode::s_mov_b32, Definition(dst), src);
6748       } else if (src.regClass() == s2) {
6749          bld.pseudo(aco_opcode::p_create_vector, Definition(dst), src);
6750       } else {
6751          fprintf(stderr, "Unimplemented NIR instr bit size: ");
6752          nir_print_instr(&instr->instr, stderr);
6753          fprintf(stderr, "\n");
6754       }
6755       break;
6756    }
6757    case nir_intrinsic_vote_all: {
6758       Temp src = get_ssa_temp(ctx, instr->src[0].ssa);
6759       Temp dst = get_ssa_temp(ctx, &instr->dest.ssa);
6760       assert(src.regClass() == bld.lm);
6761       assert(dst.regClass() == bld.lm);
6762
6763       Temp tmp = bld.sop2(Builder::s_andn2, bld.def(bld.lm), bld.def(s1, scc), Operand(exec, bld.lm), src).def(1).getTemp();
6764       Temp cond = bool_to_vector_condition(ctx, emit_wqm(ctx, tmp));
6765       bld.sop1(Builder::s_not, Definition(dst), bld.def(s1, scc), cond);
6766       break;
6767    }
6768    case nir_intrinsic_vote_any: {
6769       Temp src = get_ssa_temp(ctx, instr->src[0].ssa);
6770       Temp dst = get_ssa_temp(ctx, &instr->dest.ssa);
6771       assert(src.regClass() == bld.lm);
6772       assert(dst.regClass() == bld.lm);
6773
6774       Temp tmp = bool_to_scalar_condition(ctx, src);
6775       bool_to_vector_condition(ctx, emit_wqm(ctx, tmp), dst);
6776       break;
6777    }
6778    case nir_intrinsic_reduce:
6779    case nir_intrinsic_inclusive_scan:
6780    case nir_intrinsic_exclusive_scan: {
6781       Temp src = get_ssa_temp(ctx, instr->src[0].ssa);
6782       Temp dst = get_ssa_temp(ctx, &instr->dest.ssa);
6783       nir_op op = (nir_op) nir_intrinsic_reduction_op(instr);
6784       unsigned cluster_size = instr->intrinsic == nir_intrinsic_reduce ?
6785          nir_intrinsic_cluster_size(instr) : 0;
6786       cluster_size = util_next_power_of_two(MIN2(cluster_size ? cluster_size : ctx->program->wave_size, ctx->program->wave_size));
6787
6788       if (!ctx->divergent_vals[instr->src[0].ssa->index] && (op == nir_op_ior || op == nir_op_iand)) {
6789          emit_uniform_subgroup(ctx, instr, src);
6790       } else if (instr->dest.ssa.bit_size == 1) {
6791          if (op == nir_op_imul || op == nir_op_umin || op == nir_op_imin)
6792             op = nir_op_iand;
6793          else if (op == nir_op_iadd)
6794             op = nir_op_ixor;
6795          else if (op == nir_op_umax || op == nir_op_imax)
6796             op = nir_op_ior;
6797          assert(op == nir_op_iand || op == nir_op_ior || op == nir_op_ixor);
6798
6799          switch (instr->intrinsic) {
6800          case nir_intrinsic_reduce:
6801             emit_wqm(ctx, emit_boolean_reduce(ctx, op, cluster_size, src), dst);
6802             break;
6803          case nir_intrinsic_exclusive_scan:
6804             emit_wqm(ctx, emit_boolean_exclusive_scan(ctx, op, src), dst);
6805             break;
6806          case nir_intrinsic_inclusive_scan:
6807             emit_wqm(ctx, emit_boolean_inclusive_scan(ctx, op, src), dst);
6808             break;
6809          default:
6810             assert(false);
6811          }
6812       } else if (cluster_size == 1) {
6813          bld.copy(Definition(dst), src);
6814       } else {
6815          src = as_vgpr(ctx, src);
6816
6817          ReduceOp reduce_op;
6818          switch (op) {
6819          #define CASE(name) case nir_op_##name: reduce_op = (src.regClass() == v1) ? name##32 : name##64; break;
6820             CASE(iadd)
6821             CASE(imul)
6822             CASE(fadd)
6823             CASE(fmul)
6824             CASE(imin)
6825             CASE(umin)
6826             CASE(fmin)
6827             CASE(imax)
6828             CASE(umax)
6829             CASE(fmax)
6830             CASE(iand)
6831             CASE(ior)
6832             CASE(ixor)
6833             default:
6834                unreachable("unknown reduction op");
6835          #undef CASE
6836          }
6837
6838          aco_opcode aco_op;
6839          switch (instr->intrinsic) {
6840             case nir_intrinsic_reduce: aco_op = aco_opcode::p_reduce; break;
6841             case nir_intrinsic_inclusive_scan: aco_op = aco_opcode::p_inclusive_scan; break;
6842             case nir_intrinsic_exclusive_scan: aco_op = aco_opcode::p_exclusive_scan; break;
6843             default:
6844                unreachable("unknown reduce intrinsic");
6845          }
6846
6847          aco_ptr<Pseudo_reduction_instruction> reduce{create_instruction<Pseudo_reduction_instruction>(aco_op, Format::PSEUDO_REDUCTION, 3, 5)};
6848          reduce->operands[0] = Operand(src);
6849          // filled in by aco_reduce_assign.cpp, used internally as part of the
6850          // reduce sequence
6851          assert(dst.size() == 1 || dst.size() == 2);
6852          reduce->operands[1] = Operand(RegClass(RegType::vgpr, dst.size()).as_linear());
6853          reduce->operands[2] = Operand(v1.as_linear());
6854
6855          Temp tmp_dst = bld.tmp(dst.regClass());
6856          reduce->definitions[0] = Definition(tmp_dst);
6857          reduce->definitions[1] = bld.def(ctx->program->lane_mask); // used internally
6858          reduce->definitions[2] = Definition();
6859          reduce->definitions[3] = Definition(scc, s1);
6860          reduce->definitions[4] = Definition();
6861          reduce->reduce_op = reduce_op;
6862          reduce->cluster_size = cluster_size;
6863          ctx->block->instructions.emplace_back(std::move(reduce));
6864
6865          emit_wqm(ctx, tmp_dst, dst);
6866       }
6867       break;
6868    }
6869    case nir_intrinsic_quad_broadcast: {
6870       Temp src = get_ssa_temp(ctx, instr->src[0].ssa);
6871       if (!ctx->divergent_vals[instr->dest.ssa.index]) {
6872          emit_uniform_subgroup(ctx, instr, src);
6873       } else {
6874          Temp dst = get_ssa_temp(ctx, &instr->dest.ssa);
6875          unsigned lane = nir_src_as_const_value(instr->src[1])->u32;
6876          uint32_t dpp_ctrl = dpp_quad_perm(lane, lane, lane, lane);
6877
6878          if (instr->dest.ssa.bit_size == 1) {
6879             assert(src.regClass() == bld.lm);
6880             assert(dst.regClass() == bld.lm);
6881             uint32_t half_mask = 0x11111111u << lane;
6882             Temp mask_tmp = bld.pseudo(aco_opcode::p_create_vector, bld.def(s2), Operand(half_mask), Operand(half_mask));
6883             Temp tmp = bld.tmp(bld.lm);
6884             bld.sop1(Builder::s_wqm, Definition(tmp),
6885                      bld.sop2(Builder::s_and, bld.def(bld.lm), bld.def(s1, scc), mask_tmp,
6886                               bld.sop2(Builder::s_and, bld.def(bld.lm), bld.def(s1, scc), src, Operand(exec, bld.lm))));
6887             emit_wqm(ctx, tmp, dst);
6888          } else if (instr->dest.ssa.bit_size == 32) {
6889             if (ctx->program->chip_class >= GFX8)
6890                emit_wqm(ctx, bld.vop1_dpp(aco_opcode::v_mov_b32, bld.def(v1), src, dpp_ctrl), dst);
6891             else
6892                emit_wqm(ctx, bld.ds(aco_opcode::ds_swizzle_b32, bld.def(v1), src, (1 << 15) | dpp_ctrl), dst);
6893          } else if (instr->dest.ssa.bit_size == 64) {
6894             Temp lo = bld.tmp(v1), hi = bld.tmp(v1);
6895             bld.pseudo(aco_opcode::p_split_vector, Definition(lo), Definition(hi), src);
6896             if (ctx->program->chip_class >= GFX8) {
6897                lo = emit_wqm(ctx, bld.vop1_dpp(aco_opcode::v_mov_b32, bld.def(v1), lo, dpp_ctrl));
6898                hi = emit_wqm(ctx, bld.vop1_dpp(aco_opcode::v_mov_b32, bld.def(v1), hi, dpp_ctrl));
6899             } else {
6900                lo = emit_wqm(ctx, bld.ds(aco_opcode::ds_swizzle_b32, bld.def(v1), lo, (1 << 15) | dpp_ctrl));
6901                hi = emit_wqm(ctx, bld.ds(aco_opcode::ds_swizzle_b32, bld.def(v1), hi, (1 << 15) | dpp_ctrl));
6902             }
6903             bld.pseudo(aco_opcode::p_create_vector, Definition(dst), lo, hi);
6904             emit_split_vector(ctx, dst, 2);
6905          } else {
6906             fprintf(stderr, "Unimplemented NIR instr bit size: ");
6907             nir_print_instr(&instr->instr, stderr);
6908             fprintf(stderr, "\n");
6909          }
6910       }
6911       break;
6912    }
6913    case nir_intrinsic_quad_swap_horizontal:
6914    case nir_intrinsic_quad_swap_vertical:
6915    case nir_intrinsic_quad_swap_diagonal:
6916    case nir_intrinsic_quad_swizzle_amd: {
6917       Temp src = get_ssa_temp(ctx, instr->src[0].ssa);
6918       if (!ctx->divergent_vals[instr->dest.ssa.index]) {
6919          emit_uniform_subgroup(ctx, instr, src);
6920          break;
6921       }
6922       uint16_t dpp_ctrl = 0;
6923       switch (instr->intrinsic) {
6924       case nir_intrinsic_quad_swap_horizontal:
6925          dpp_ctrl = dpp_quad_perm(1, 0, 3, 2);
6926          break;
6927       case nir_intrinsic_quad_swap_vertical:
6928          dpp_ctrl = dpp_quad_perm(2, 3, 0, 1);
6929          break;
6930       case nir_intrinsic_quad_swap_diagonal:
6931          dpp_ctrl = dpp_quad_perm(3, 2, 1, 0);
6932          break;
6933       case nir_intrinsic_quad_swizzle_amd:
6934          dpp_ctrl = nir_intrinsic_swizzle_mask(instr);
6935          break;
6936       default:
6937          break;
6938       }
6939       if (ctx->program->chip_class < GFX8)
6940          dpp_ctrl |= (1 << 15);
6941
6942       Temp dst = get_ssa_temp(ctx, &instr->dest.ssa);
6943       if (instr->dest.ssa.bit_size == 1) {
6944          assert(src.regClass() == bld.lm);
6945          src = bld.vop2_e64(aco_opcode::v_cndmask_b32, bld.def(v1), Operand(0u), Operand((uint32_t)-1), src);
6946          if (ctx->program->chip_class >= GFX8)
6947             src = bld.vop1_dpp(aco_opcode::v_mov_b32, bld.def(v1), src, dpp_ctrl);
6948          else
6949             src = bld.ds(aco_opcode::ds_swizzle_b32, bld.def(v1), src, dpp_ctrl);
6950          Temp tmp = bld.vopc(aco_opcode::v_cmp_lg_u32, bld.def(bld.lm), Operand(0u), src);
6951          emit_wqm(ctx, tmp, dst);
6952       } else if (instr->dest.ssa.bit_size == 32) {
6953          Temp tmp;
6954          if (ctx->program->chip_class >= GFX8)
6955             tmp = bld.vop1_dpp(aco_opcode::v_mov_b32, bld.def(v1), src, dpp_ctrl);
6956          else
6957             tmp = bld.ds(aco_opcode::ds_swizzle_b32, bld.def(v1), src, dpp_ctrl);
6958          emit_wqm(ctx, tmp, dst);
6959       } else if (instr->dest.ssa.bit_size == 64) {
6960          Temp lo = bld.tmp(v1), hi = bld.tmp(v1);
6961          bld.pseudo(aco_opcode::p_split_vector, Definition(lo), Definition(hi), src);
6962          if (ctx->program->chip_class >= GFX8) {
6963             lo = emit_wqm(ctx, bld.vop1_dpp(aco_opcode::v_mov_b32, bld.def(v1), lo, dpp_ctrl));
6964             hi = emit_wqm(ctx, bld.vop1_dpp(aco_opcode::v_mov_b32, bld.def(v1), hi, dpp_ctrl));
6965          } else {
6966             lo = emit_wqm(ctx, bld.ds(aco_opcode::ds_swizzle_b32, bld.def(v1), lo, dpp_ctrl));
6967             hi = emit_wqm(ctx, bld.ds(aco_opcode::ds_swizzle_b32, bld.def(v1), hi, dpp_ctrl));
6968          }
6969          bld.pseudo(aco_opcode::p_create_vector, Definition(dst), lo, hi);
6970          emit_split_vector(ctx, dst, 2);
6971       } else {
6972          fprintf(stderr, "Unimplemented NIR instr bit size: ");
6973          nir_print_instr(&instr->instr, stderr);
6974          fprintf(stderr, "\n");
6975       }
6976       break;
6977    }
6978    case nir_intrinsic_masked_swizzle_amd: {
6979       Temp src = get_ssa_temp(ctx, instr->src[0].ssa);
6980       if (!ctx->divergent_vals[instr->dest.ssa.index]) {
6981          emit_uniform_subgroup(ctx, instr, src);
6982          break;
6983       }
6984       Temp dst = get_ssa_temp(ctx, &instr->dest.ssa);
6985       uint32_t mask = nir_intrinsic_swizzle_mask(instr);
6986       if (dst.regClass() == v1) {
6987          emit_wqm(ctx,
6988                   bld.ds(aco_opcode::ds_swizzle_b32, bld.def(v1), src, mask, 0, false),
6989                   dst);
6990       } else if (dst.regClass() == v2) {
6991          Temp lo = bld.tmp(v1), hi = bld.tmp(v1);
6992          bld.pseudo(aco_opcode::p_split_vector, Definition(lo), Definition(hi), src);
6993          lo = emit_wqm(ctx, bld.ds(aco_opcode::ds_swizzle_b32, bld.def(v1), lo, mask, 0, false));
6994          hi = emit_wqm(ctx, bld.ds(aco_opcode::ds_swizzle_b32, bld.def(v1), hi, mask, 0, false));
6995          bld.pseudo(aco_opcode::p_create_vector, Definition(dst), lo, hi);
6996          emit_split_vector(ctx, dst, 2);
6997       } else {
6998          fprintf(stderr, "Unimplemented NIR instr bit size: ");
6999          nir_print_instr(&instr->instr, stderr);
7000          fprintf(stderr, "\n");
7001       }
7002       break;
7003    }
7004    case nir_intrinsic_write_invocation_amd: {
7005       Temp src = as_vgpr(ctx, get_ssa_temp(ctx, instr->src[0].ssa));
7006       Temp val = bld.as_uniform(get_ssa_temp(ctx, instr->src[1].ssa));
7007       Temp lane = bld.as_uniform(get_ssa_temp(ctx, instr->src[2].ssa));
7008       Temp dst = get_ssa_temp(ctx, &instr->dest.ssa);
7009       if (dst.regClass() == v1) {
7010          /* src2 is ignored for writelane. RA assigns the same reg for dst */
7011          emit_wqm(ctx, bld.writelane(bld.def(v1), val, lane, src), dst);
7012       } else if (dst.regClass() == v2) {
7013          Temp src_lo = bld.tmp(v1), src_hi = bld.tmp(v1);
7014          Temp val_lo = bld.tmp(s1), val_hi = bld.tmp(s1);
7015          bld.pseudo(aco_opcode::p_split_vector, Definition(src_lo), Definition(src_hi), src);
7016          bld.pseudo(aco_opcode::p_split_vector, Definition(val_lo), Definition(val_hi), val);
7017          Temp lo = emit_wqm(ctx, bld.writelane(bld.def(v1), val_lo, lane, src_hi));
7018          Temp hi = emit_wqm(ctx, bld.writelane(bld.def(v1), val_hi, lane, src_hi));
7019          bld.pseudo(aco_opcode::p_create_vector, Definition(dst), lo, hi);
7020          emit_split_vector(ctx, dst, 2);
7021       } else {
7022          fprintf(stderr, "Unimplemented NIR instr bit size: ");
7023          nir_print_instr(&instr->instr, stderr);
7024          fprintf(stderr, "\n");
7025       }
7026       break;
7027    }
7028    case nir_intrinsic_mbcnt_amd: {
7029       Temp src = get_ssa_temp(ctx, instr->src[0].ssa);
7030       RegClass rc = RegClass(src.type(), 1);
7031       Temp mask_lo = bld.tmp(rc), mask_hi = bld.tmp(rc);
7032       bld.pseudo(aco_opcode::p_split_vector, Definition(mask_lo), Definition(mask_hi), src);
7033       Temp dst = get_ssa_temp(ctx, &instr->dest.ssa);
7034       Temp wqm_tmp = emit_mbcnt(ctx, bld.def(v1), Operand(mask_lo), Operand(mask_hi));
7035       emit_wqm(ctx, wqm_tmp, dst);
7036       break;
7037    }
7038    case nir_intrinsic_load_helper_invocation: {
7039       Temp dst = get_ssa_temp(ctx, &instr->dest.ssa);
7040       bld.pseudo(aco_opcode::p_load_helper, Definition(dst));
7041       ctx->block->kind |= block_kind_needs_lowering;
7042       ctx->program->needs_exact = true;
7043       break;
7044    }
7045    case nir_intrinsic_is_helper_invocation: {
7046       Temp dst = get_ssa_temp(ctx, &instr->dest.ssa);
7047       bld.pseudo(aco_opcode::p_is_helper, Definition(dst));
7048       ctx->block->kind |= block_kind_needs_lowering;
7049       ctx->program->needs_exact = true;
7050       break;
7051    }
7052    case nir_intrinsic_demote:
7053       bld.pseudo(aco_opcode::p_demote_to_helper, Operand(-1u));
7054
7055       if (ctx->cf_info.loop_nest_depth || ctx->cf_info.parent_if.is_divergent)
7056          ctx->cf_info.exec_potentially_empty_discard = true;
7057       ctx->block->kind |= block_kind_uses_demote;
7058       ctx->program->needs_exact = true;
7059       break;
7060    case nir_intrinsic_demote_if: {
7061       Temp src = get_ssa_temp(ctx, instr->src[0].ssa);
7062       assert(src.regClass() == bld.lm);
7063       Temp cond = bld.sop2(Builder::s_and, bld.def(bld.lm), bld.def(s1, scc), src, Operand(exec, bld.lm));
7064       bld.pseudo(aco_opcode::p_demote_to_helper, cond);
7065
7066       if (ctx->cf_info.loop_nest_depth || ctx->cf_info.parent_if.is_divergent)
7067          ctx->cf_info.exec_potentially_empty_discard = true;
7068       ctx->block->kind |= block_kind_uses_demote;
7069       ctx->program->needs_exact = true;
7070       break;
7071    }
7072    case nir_intrinsic_first_invocation: {
7073       emit_wqm(ctx, bld.sop1(Builder::s_ff1_i32, bld.def(s1), Operand(exec, bld.lm)),
7074                get_ssa_temp(ctx, &instr->dest.ssa));
7075       break;
7076    }
7077    case nir_intrinsic_shader_clock:
7078       bld.smem(aco_opcode::s_memtime, Definition(get_ssa_temp(ctx, &instr->dest.ssa)), false);
7079       emit_split_vector(ctx, get_ssa_temp(ctx, &instr->dest.ssa), 2);
7080       break;
7081    case nir_intrinsic_load_vertex_id_zero_base: {
7082       Temp dst = get_ssa_temp(ctx, &instr->dest.ssa);
7083       bld.copy(Definition(dst), get_arg(ctx, ctx->args->ac.vertex_id));
7084       break;
7085    }
7086    case nir_intrinsic_load_first_vertex: {
7087       Temp dst = get_ssa_temp(ctx, &instr->dest.ssa);
7088       bld.copy(Definition(dst), get_arg(ctx, ctx->args->ac.base_vertex));
7089       break;
7090    }
7091    case nir_intrinsic_load_base_instance: {
7092       Temp dst = get_ssa_temp(ctx, &instr->dest.ssa);
7093       bld.copy(Definition(dst), get_arg(ctx, ctx->args->ac.start_instance));
7094       break;
7095    }
7096    case nir_intrinsic_load_instance_id: {
7097       Temp dst = get_ssa_temp(ctx, &instr->dest.ssa);
7098       bld.copy(Definition(dst), get_arg(ctx, ctx->args->ac.instance_id));
7099       break;
7100    }
7101    case nir_intrinsic_load_draw_id: {
7102       Temp dst = get_ssa_temp(ctx, &instr->dest.ssa);
7103       bld.copy(Definition(dst), get_arg(ctx, ctx->args->ac.draw_id));
7104       break;
7105    }
7106    case nir_intrinsic_load_invocation_id: {
7107       Temp dst = get_ssa_temp(ctx, &instr->dest.ssa);
7108
7109       if (ctx->shader->info.stage == MESA_SHADER_GEOMETRY) {
7110          if (ctx->options->chip_class >= GFX10)
7111             bld.vop2_e64(aco_opcode::v_and_b32, Definition(dst), Operand(127u), get_arg(ctx, ctx->args->ac.gs_invocation_id));
7112          else
7113             bld.copy(Definition(dst), get_arg(ctx, ctx->args->ac.gs_invocation_id));
7114       } else if (ctx->shader->info.stage == MESA_SHADER_TESS_CTRL) {
7115          bld.vop3(aco_opcode::v_bfe_u32, Definition(dst),
7116                   get_arg(ctx, ctx->args->ac.tcs_rel_ids), Operand(8u), Operand(5u));
7117       } else {
7118          unreachable("Unsupported stage for load_invocation_id");
7119       }
7120
7121       break;
7122    }
7123    case nir_intrinsic_load_primitive_id: {
7124       Temp dst = get_ssa_temp(ctx, &instr->dest.ssa);
7125
7126       switch (ctx->shader->info.stage) {
7127       case MESA_SHADER_GEOMETRY:
7128          bld.copy(Definition(dst), get_arg(ctx, ctx->args->ac.gs_prim_id));
7129          break;
7130       case MESA_SHADER_TESS_CTRL:
7131          bld.copy(Definition(dst), get_arg(ctx, ctx->args->ac.tcs_patch_id));
7132          break;
7133       case MESA_SHADER_TESS_EVAL:
7134          bld.copy(Definition(dst), get_arg(ctx, ctx->args->ac.tes_patch_id));
7135          break;
7136       default:
7137          unreachable("Unimplemented shader stage for nir_intrinsic_load_primitive_id");
7138       }
7139
7140       break;
7141    }
7142    case nir_intrinsic_load_patch_vertices_in: {
7143       assert(ctx->shader->info.stage == MESA_SHADER_TESS_CTRL ||
7144              ctx->shader->info.stage == MESA_SHADER_TESS_EVAL);
7145
7146       Temp dst = get_ssa_temp(ctx, &instr->dest.ssa);
7147       bld.copy(Definition(dst), Operand(ctx->args->options->key.tcs.input_vertices));
7148       break;
7149    }
7150    case nir_intrinsic_emit_vertex_with_counter: {
7151       visit_emit_vertex_with_counter(ctx, instr);
7152       break;
7153    }
7154    case nir_intrinsic_end_primitive_with_counter: {
7155       unsigned stream = nir_intrinsic_stream_id(instr);
7156       bld.sopp(aco_opcode::s_sendmsg, bld.m0(ctx->gs_wave_id), -1, sendmsg_gs(true, false, stream));
7157       break;
7158    }
7159    case nir_intrinsic_set_vertex_count: {
7160       /* unused, the HW keeps track of this for us */
7161       break;
7162    }
7163    default:
7164       fprintf(stderr, "Unimplemented intrinsic instr: ");
7165       nir_print_instr(&instr->instr, stderr);
7166       fprintf(stderr, "\n");
7167       abort();
7168
7169       break;
7170    }
7171 }
7172
7173
7174 void tex_fetch_ptrs(isel_context *ctx, nir_tex_instr *instr,
7175                     Temp *res_ptr, Temp *samp_ptr, Temp *fmask_ptr,
7176                     enum glsl_base_type *stype)
7177 {
7178    nir_deref_instr *texture_deref_instr = NULL;
7179    nir_deref_instr *sampler_deref_instr = NULL;
7180    int plane = -1;
7181
7182    for (unsigned i = 0; i < instr->num_srcs; i++) {
7183       switch (instr->src[i].src_type) {
7184       case nir_tex_src_texture_deref:
7185          texture_deref_instr = nir_src_as_deref(instr->src[i].src);
7186          break;
7187       case nir_tex_src_sampler_deref:
7188          sampler_deref_instr = nir_src_as_deref(instr->src[i].src);
7189          break;
7190       case nir_tex_src_plane:
7191          plane = nir_src_as_int(instr->src[i].src);
7192          break;
7193       default:
7194          break;
7195       }
7196    }
7197
7198    *stype = glsl_get_sampler_result_type(texture_deref_instr->type);
7199
7200    if (!sampler_deref_instr)
7201       sampler_deref_instr = texture_deref_instr;
7202
7203    if (plane >= 0) {
7204       assert(instr->op != nir_texop_txf_ms &&
7205              instr->op != nir_texop_samples_identical);
7206       assert(instr->sampler_dim  != GLSL_SAMPLER_DIM_BUF);
7207       *res_ptr = get_sampler_desc(ctx, texture_deref_instr, (aco_descriptor_type)(ACO_DESC_PLANE_0 + plane), instr, false, false);
7208    } else if (instr->sampler_dim  == GLSL_SAMPLER_DIM_BUF) {
7209       *res_ptr = get_sampler_desc(ctx, texture_deref_instr, ACO_DESC_BUFFER, instr, false, false);
7210    } else if (instr->op == nir_texop_fragment_mask_fetch) {
7211       *res_ptr = get_sampler_desc(ctx, texture_deref_instr, ACO_DESC_FMASK, instr, false, false);
7212    } else {
7213       *res_ptr = get_sampler_desc(ctx, texture_deref_instr, ACO_DESC_IMAGE, instr, false, false);
7214    }
7215    if (samp_ptr) {
7216       *samp_ptr = get_sampler_desc(ctx, sampler_deref_instr, ACO_DESC_SAMPLER, instr, false, false);
7217
7218       if (instr->sampler_dim < GLSL_SAMPLER_DIM_RECT && ctx->options->chip_class < GFX8) {
7219          /* fix sampler aniso on SI/CI: samp[0] = samp[0] & img[7] */
7220          Builder bld(ctx->program, ctx->block);
7221
7222          /* to avoid unnecessary moves, we split and recombine sampler and image */
7223          Temp img[8] = {bld.tmp(s1), bld.tmp(s1), bld.tmp(s1), bld.tmp(s1),
7224                         bld.tmp(s1), bld.tmp(s1), bld.tmp(s1), bld.tmp(s1)};
7225          Temp samp[4] = {bld.tmp(s1), bld.tmp(s1), bld.tmp(s1), bld.tmp(s1)};
7226          bld.pseudo(aco_opcode::p_split_vector, Definition(img[0]), Definition(img[1]),
7227                     Definition(img[2]), Definition(img[3]), Definition(img[4]),
7228                     Definition(img[5]), Definition(img[6]), Definition(img[7]), *res_ptr);
7229          bld.pseudo(aco_opcode::p_split_vector, Definition(samp[0]), Definition(samp[1]),
7230                     Definition(samp[2]), Definition(samp[3]), *samp_ptr);
7231
7232          samp[0] = bld.sop2(aco_opcode::s_and_b32, bld.def(s1), bld.def(s1, scc), samp[0], img[7]);
7233          *res_ptr = bld.pseudo(aco_opcode::p_create_vector, bld.def(s8),
7234                                img[0], img[1], img[2], img[3],
7235                                img[4], img[5], img[6], img[7]);
7236          *samp_ptr = bld.pseudo(aco_opcode::p_create_vector, bld.def(s4),
7237                                 samp[0], samp[1], samp[2], samp[3]);
7238       }
7239    }
7240    if (fmask_ptr && (instr->op == nir_texop_txf_ms ||
7241                      instr->op == nir_texop_samples_identical))
7242       *fmask_ptr = get_sampler_desc(ctx, texture_deref_instr, ACO_DESC_FMASK, instr, false, false);
7243 }
7244
7245 void build_cube_select(isel_context *ctx, Temp ma, Temp id, Temp deriv,
7246                        Temp *out_ma, Temp *out_sc, Temp *out_tc)
7247 {
7248    Builder bld(ctx->program, ctx->block);
7249
7250    Temp deriv_x = emit_extract_vector(ctx, deriv, 0, v1);
7251    Temp deriv_y = emit_extract_vector(ctx, deriv, 1, v1);
7252    Temp deriv_z = emit_extract_vector(ctx, deriv, 2, v1);
7253
7254    Operand neg_one(0xbf800000u);
7255    Operand one(0x3f800000u);
7256    Operand two(0x40000000u);
7257    Operand four(0x40800000u);
7258
7259    Temp is_ma_positive = bld.vopc(aco_opcode::v_cmp_le_f32, bld.hint_vcc(bld.def(bld.lm)), Operand(0u), ma);
7260    Temp sgn_ma = bld.vop2_e64(aco_opcode::v_cndmask_b32, bld.def(v1), neg_one, one, is_ma_positive);
7261    Temp neg_sgn_ma = bld.vop2(aco_opcode::v_sub_f32, bld.def(v1), Operand(0u), sgn_ma);
7262
7263    Temp is_ma_z = bld.vopc(aco_opcode::v_cmp_le_f32, bld.hint_vcc(bld.def(bld.lm)), four, id);
7264    Temp is_ma_y = bld.vopc(aco_opcode::v_cmp_le_f32, bld.def(bld.lm), two, id);
7265    is_ma_y = bld.sop2(Builder::s_andn2, bld.hint_vcc(bld.def(bld.lm)), is_ma_y, is_ma_z);
7266    Temp is_not_ma_x = bld.sop2(aco_opcode::s_or_b64, bld.hint_vcc(bld.def(bld.lm)), bld.def(s1, scc), is_ma_z, is_ma_y);
7267
7268    // select sc
7269    Temp tmp = bld.vop2(aco_opcode::v_cndmask_b32, bld.def(v1), deriv_z, deriv_x, is_not_ma_x);
7270    Temp sgn = bld.vop2_e64(aco_opcode::v_cndmask_b32, bld.def(v1),
7271                        bld.vop2(aco_opcode::v_cndmask_b32, bld.def(v1), neg_sgn_ma, sgn_ma, is_ma_z),
7272                        one, is_ma_y);
7273    *out_sc = bld.vop2(aco_opcode::v_mul_f32, bld.def(v1), tmp, sgn);
7274
7275    // select tc
7276    tmp = bld.vop2(aco_opcode::v_cndmask_b32, bld.def(v1), deriv_y, deriv_z, is_ma_y);
7277    sgn = bld.vop2(aco_opcode::v_cndmask_b32, bld.def(v1), neg_one, sgn_ma, is_ma_y);
7278    *out_tc = bld.vop2(aco_opcode::v_mul_f32, bld.def(v1), tmp, sgn);
7279
7280    // select ma
7281    tmp = bld.vop2(aco_opcode::v_cndmask_b32, bld.def(v1),
7282                   bld.vop2(aco_opcode::v_cndmask_b32, bld.def(v1), deriv_x, deriv_y, is_ma_y),
7283                   deriv_z, is_ma_z);
7284    tmp = bld.vop2(aco_opcode::v_and_b32, bld.def(v1), Operand(0x7fffffffu), tmp);
7285    *out_ma = bld.vop2(aco_opcode::v_mul_f32, bld.def(v1), two, tmp);
7286 }
7287
7288 void prepare_cube_coords(isel_context *ctx, std::vector<Temp>& coords, Temp* ddx, Temp* ddy, bool is_deriv, bool is_array)
7289 {
7290    Builder bld(ctx->program, ctx->block);
7291    Temp ma, tc, sc, id;
7292
7293    if (is_array) {
7294       coords[3] = bld.vop1(aco_opcode::v_rndne_f32, bld.def(v1), coords[3]);
7295
7296       // see comment in ac_prepare_cube_coords()
7297       if (ctx->options->chip_class <= GFX8)
7298          coords[3] = bld.vop2(aco_opcode::v_max_f32, bld.def(v1), Operand(0u), coords[3]);
7299    }
7300
7301    ma = bld.vop3(aco_opcode::v_cubema_f32, bld.def(v1), coords[0], coords[1], coords[2]);
7302
7303    aco_ptr<VOP3A_instruction> vop3a{create_instruction<VOP3A_instruction>(aco_opcode::v_rcp_f32, asVOP3(Format::VOP1), 1, 1)};
7304    vop3a->operands[0] = Operand(ma);
7305    vop3a->abs[0] = true;
7306    Temp invma = bld.tmp(v1);
7307    vop3a->definitions[0] = Definition(invma);
7308    ctx->block->instructions.emplace_back(std::move(vop3a));
7309
7310    sc = bld.vop3(aco_opcode::v_cubesc_f32, bld.def(v1), coords[0], coords[1], coords[2]);
7311    if (!is_deriv)
7312       sc = bld.vop2(aco_opcode::v_madak_f32, bld.def(v1), sc, invma, Operand(0x3fc00000u/*1.5*/));
7313
7314    tc = bld.vop3(aco_opcode::v_cubetc_f32, bld.def(v1), coords[0], coords[1], coords[2]);
7315    if (!is_deriv)
7316       tc = bld.vop2(aco_opcode::v_madak_f32, bld.def(v1), tc, invma, Operand(0x3fc00000u/*1.5*/));
7317
7318    id = bld.vop3(aco_opcode::v_cubeid_f32, bld.def(v1), coords[0], coords[1], coords[2]);
7319
7320    if (is_deriv) {
7321       sc = bld.vop2(aco_opcode::v_mul_f32, bld.def(v1), sc, invma);
7322       tc = bld.vop2(aco_opcode::v_mul_f32, bld.def(v1), tc, invma);
7323
7324       for (unsigned i = 0; i < 2; i++) {
7325          // see comment in ac_prepare_cube_coords()
7326          Temp deriv_ma;
7327          Temp deriv_sc, deriv_tc;
7328          build_cube_select(ctx, ma, id, i ? *ddy : *ddx,
7329                            &deriv_ma, &deriv_sc, &deriv_tc);
7330
7331          deriv_ma = bld.vop2(aco_opcode::v_mul_f32, bld.def(v1), deriv_ma, invma);
7332
7333          Temp x = bld.vop2(aco_opcode::v_sub_f32, bld.def(v1),
7334                                bld.vop2(aco_opcode::v_mul_f32, bld.def(v1), deriv_sc, invma),
7335                                bld.vop2(aco_opcode::v_mul_f32, bld.def(v1), deriv_ma, sc));
7336          Temp y = bld.vop2(aco_opcode::v_sub_f32, bld.def(v1),
7337                                bld.vop2(aco_opcode::v_mul_f32, bld.def(v1), deriv_tc, invma),
7338                                bld.vop2(aco_opcode::v_mul_f32, bld.def(v1), deriv_ma, tc));
7339          *(i ? ddy : ddx) = bld.pseudo(aco_opcode::p_create_vector, bld.def(v2), x, y);
7340       }
7341
7342       sc = bld.vop2(aco_opcode::v_add_f32, bld.def(v1), Operand(0x3fc00000u/*1.5*/), sc);
7343       tc = bld.vop2(aco_opcode::v_add_f32, bld.def(v1), Operand(0x3fc00000u/*1.5*/), tc);
7344    }
7345
7346    if (is_array)
7347       id = bld.vop2(aco_opcode::v_madmk_f32, bld.def(v1), coords[3], id, Operand(0x41000000u/*8.0*/));
7348    coords.resize(3);
7349    coords[0] = sc;
7350    coords[1] = tc;
7351    coords[2] = id;
7352 }
7353
7354 void get_const_vec(nir_ssa_def *vec, nir_const_value *cv[4])
7355 {
7356    if (vec->parent_instr->type != nir_instr_type_alu)
7357       return;
7358    nir_alu_instr *vec_instr = nir_instr_as_alu(vec->parent_instr);
7359    if (vec_instr->op != nir_op_vec(vec->num_components))
7360       return;
7361
7362    for (unsigned i = 0; i < vec->num_components; i++) {
7363       cv[i] = vec_instr->src[i].swizzle[0] == 0 ?
7364               nir_src_as_const_value(vec_instr->src[i].src) : NULL;
7365    }
7366 }
7367
7368 void visit_tex(isel_context *ctx, nir_tex_instr *instr)
7369 {
7370    Builder bld(ctx->program, ctx->block);
7371    bool has_bias = false, has_lod = false, level_zero = false, has_compare = false,
7372         has_offset = false, has_ddx = false, has_ddy = false, has_derivs = false, has_sample_index = false;
7373    Temp resource, sampler, fmask_ptr, bias = Temp(), compare = Temp(), sample_index = Temp(),
7374         lod = Temp(), offset = Temp(), ddx = Temp(), ddy = Temp();
7375    std::vector<Temp> coords;
7376    std::vector<Temp> derivs;
7377    nir_const_value *sample_index_cv = NULL;
7378    nir_const_value *const_offset[4] = {NULL, NULL, NULL, NULL};
7379    enum glsl_base_type stype;
7380    tex_fetch_ptrs(ctx, instr, &resource, &sampler, &fmask_ptr, &stype);
7381
7382    bool tg4_integer_workarounds = ctx->options->chip_class <= GFX8 && instr->op == nir_texop_tg4 &&
7383                                   (stype == GLSL_TYPE_UINT || stype == GLSL_TYPE_INT);
7384    bool tg4_integer_cube_workaround = tg4_integer_workarounds &&
7385                                       instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE;
7386
7387    for (unsigned i = 0; i < instr->num_srcs; i++) {
7388       switch (instr->src[i].src_type) {
7389       case nir_tex_src_coord: {
7390          Temp coord = get_ssa_temp(ctx, instr->src[i].src.ssa);
7391          for (unsigned i = 0; i < coord.size(); i++)
7392             coords.emplace_back(emit_extract_vector(ctx, coord, i, v1));
7393          break;
7394       }
7395       case nir_tex_src_bias:
7396          if (instr->op == nir_texop_txb) {
7397             bias = get_ssa_temp(ctx, instr->src[i].src.ssa);
7398             has_bias = true;
7399          }
7400          break;
7401       case nir_tex_src_lod: {
7402          nir_const_value *val = nir_src_as_const_value(instr->src[i].src);
7403
7404          if (val && val->f32 <= 0.0) {
7405             level_zero = true;
7406          } else {
7407             lod = get_ssa_temp(ctx, instr->src[i].src.ssa);
7408             has_lod = true;
7409          }
7410          break;
7411       }
7412       case nir_tex_src_comparator:
7413          if (instr->is_shadow) {
7414             compare = get_ssa_temp(ctx, instr->src[i].src.ssa);
7415             has_compare = true;
7416          }
7417          break;
7418       case nir_tex_src_offset:
7419          offset = get_ssa_temp(ctx, instr->src[i].src.ssa);
7420          get_const_vec(instr->src[i].src.ssa, const_offset);
7421          has_offset = true;
7422          break;
7423       case nir_tex_src_ddx:
7424          ddx = get_ssa_temp(ctx, instr->src[i].src.ssa);
7425          has_ddx = true;
7426          break;
7427       case nir_tex_src_ddy:
7428          ddy = get_ssa_temp(ctx, instr->src[i].src.ssa);
7429          has_ddy = true;
7430          break;
7431       case nir_tex_src_ms_index:
7432          sample_index = get_ssa_temp(ctx, instr->src[i].src.ssa);
7433          sample_index_cv = nir_src_as_const_value(instr->src[i].src);
7434          has_sample_index = true;
7435          break;
7436       case nir_tex_src_texture_offset:
7437       case nir_tex_src_sampler_offset:
7438       default:
7439          break;
7440       }
7441    }
7442
7443    if (instr->op == nir_texop_txs && instr->sampler_dim == GLSL_SAMPLER_DIM_BUF)
7444       return get_buffer_size(ctx, resource, get_ssa_temp(ctx, &instr->dest.ssa), true);
7445
7446    if (instr->op == nir_texop_texture_samples) {
7447       Temp dword3 = emit_extract_vector(ctx, resource, 3, s1);
7448
7449       Temp samples_log2 = bld.sop2(aco_opcode::s_bfe_u32, bld.def(s1), bld.def(s1, scc), dword3, Operand(16u | 4u<<16));
7450       Temp samples = bld.sop2(aco_opcode::s_lshl_b32, bld.def(s1), bld.def(s1, scc), Operand(1u), samples_log2);
7451       Temp type = bld.sop2(aco_opcode::s_bfe_u32, bld.def(s1), bld.def(s1, scc), dword3, Operand(28u | 4u<<16 /* offset=28, width=4 */));
7452       Temp is_msaa = bld.sopc(aco_opcode::s_cmp_ge_u32, bld.def(s1, scc), type, Operand(14u));
7453
7454       bld.sop2(aco_opcode::s_cselect_b32, Definition(get_ssa_temp(ctx, &instr->dest.ssa)),
7455                samples, Operand(1u), bld.scc(is_msaa));
7456       return;
7457    }
7458
7459    if (has_offset && instr->op != nir_texop_txf && instr->op != nir_texop_txf_ms) {
7460       aco_ptr<Instruction> tmp_instr;
7461       Temp acc, pack = Temp();
7462
7463       uint32_t pack_const = 0;
7464       for (unsigned i = 0; i < offset.size(); i++) {
7465          if (!const_offset[i])
7466             continue;
7467          pack_const |= (const_offset[i]->u32 & 0x3Fu) << (8u * i);
7468       }
7469
7470       if (offset.type() == RegType::sgpr) {
7471          for (unsigned i = 0; i < offset.size(); i++) {
7472             if (const_offset[i])
7473                continue;
7474
7475             acc = emit_extract_vector(ctx, offset, i, s1);
7476             acc = bld.sop2(aco_opcode::s_and_b32, bld.def(s1), bld.def(s1, scc), acc, Operand(0x3Fu));
7477
7478             if (i) {
7479                acc = bld.sop2(aco_opcode::s_lshl_b32, bld.def(s1), bld.def(s1, scc), acc, Operand(8u * i));
7480             }
7481
7482             if (pack == Temp()) {
7483                pack = acc;
7484             } else {
7485                pack = bld.sop2(aco_opcode::s_or_b32, bld.def(s1), bld.def(s1, scc), pack, acc);
7486             }
7487          }
7488
7489          if (pack_const && pack != Temp())
7490             pack = bld.sop2(aco_opcode::s_or_b32, bld.def(s1), bld.def(s1, scc), Operand(pack_const), pack);
7491       } else {
7492          for (unsigned i = 0; i < offset.size(); i++) {
7493             if (const_offset[i])
7494                continue;
7495
7496             acc = emit_extract_vector(ctx, offset, i, v1);
7497             acc = bld.vop2(aco_opcode::v_and_b32, bld.def(v1), Operand(0x3Fu), acc);
7498
7499             if (i) {
7500                acc = bld.vop2(aco_opcode::v_lshlrev_b32, bld.def(v1), Operand(8u * i), acc);
7501             }
7502
7503             if (pack == Temp()) {
7504                pack = acc;
7505             } else {
7506                pack = bld.vop2(aco_opcode::v_or_b32, bld.def(v1), pack, acc);
7507             }
7508          }
7509
7510          if (pack_const && pack != Temp())
7511             pack = bld.sop2(aco_opcode::v_or_b32, bld.def(v1), Operand(pack_const), pack);
7512       }
7513       if (pack_const && pack == Temp())
7514          offset = bld.vop1(aco_opcode::v_mov_b32, bld.def(v1), Operand(pack_const));
7515       else if (pack == Temp())
7516          has_offset = false;
7517       else
7518          offset = pack;
7519    }
7520
7521    if (instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE && instr->coord_components)
7522       prepare_cube_coords(ctx, coords, &ddx, &ddy, instr->op == nir_texop_txd, instr->is_array && instr->op != nir_texop_lod);
7523
7524    /* pack derivatives */
7525    if (has_ddx || has_ddy) {
7526       if (instr->sampler_dim == GLSL_SAMPLER_DIM_1D && ctx->options->chip_class == GFX9) {
7527          assert(has_ddx && has_ddy && ddx.size() == 1 && ddy.size() == 1);
7528          Temp zero = bld.copy(bld.def(v1), Operand(0u));
7529          derivs = {ddy, zero, ddy, zero};
7530       } else {
7531          for (unsigned i = 0; has_ddx && i < ddx.size(); i++)
7532             derivs.emplace_back(emit_extract_vector(ctx, ddx, i, v1));
7533          for (unsigned i = 0; has_ddy && i < ddy.size(); i++)
7534             derivs.emplace_back(emit_extract_vector(ctx, ddy, i, v1));
7535       }
7536       has_derivs = true;
7537    }
7538
7539    if (instr->coord_components > 1 &&
7540        instr->sampler_dim == GLSL_SAMPLER_DIM_1D &&
7541        instr->is_array &&
7542        instr->op != nir_texop_txf)
7543       coords[1] = bld.vop1(aco_opcode::v_rndne_f32, bld.def(v1), coords[1]);
7544
7545    if (instr->coord_components > 2 &&
7546       (instr->sampler_dim == GLSL_SAMPLER_DIM_2D ||
7547        instr->sampler_dim == GLSL_SAMPLER_DIM_MS ||
7548        instr->sampler_dim == GLSL_SAMPLER_DIM_SUBPASS ||
7549        instr->sampler_dim == GLSL_SAMPLER_DIM_SUBPASS_MS) &&
7550        instr->is_array &&
7551        instr->op != nir_texop_txf &&
7552        instr->op != nir_texop_txf_ms &&
7553        instr->op != nir_texop_fragment_fetch &&
7554        instr->op != nir_texop_fragment_mask_fetch)
7555       coords[2] = bld.vop1(aco_opcode::v_rndne_f32, bld.def(v1), coords[2]);
7556
7557    if (ctx->options->chip_class == GFX9 &&
7558        instr->sampler_dim == GLSL_SAMPLER_DIM_1D &&
7559        instr->op != nir_texop_lod && instr->coord_components) {
7560       assert(coords.size() > 0 && coords.size() < 3);
7561
7562       coords.insert(std::next(coords.begin()), bld.copy(bld.def(v1), instr->op == nir_texop_txf ?
7563                                                                      Operand((uint32_t) 0) :
7564                                                                      Operand((uint32_t) 0x3f000000)));
7565    }
7566
7567    bool da = should_declare_array(ctx, instr->sampler_dim, instr->is_array);
7568
7569    if (instr->op == nir_texop_samples_identical)
7570       resource = fmask_ptr;
7571
7572    else if ((instr->sampler_dim == GLSL_SAMPLER_DIM_MS ||
7573              instr->sampler_dim == GLSL_SAMPLER_DIM_SUBPASS_MS) &&
7574             instr->op != nir_texop_txs &&
7575             instr->op != nir_texop_fragment_fetch &&
7576             instr->op != nir_texop_fragment_mask_fetch) {
7577       assert(has_sample_index);
7578       Operand op(sample_index);
7579       if (sample_index_cv)
7580          op = Operand(sample_index_cv->u32);
7581       sample_index = adjust_sample_index_using_fmask(ctx, da, coords, op, fmask_ptr);
7582    }
7583
7584    if (has_offset && (instr->op == nir_texop_txf || instr->op == nir_texop_txf_ms)) {
7585       for (unsigned i = 0; i < std::min(offset.size(), instr->coord_components); i++) {
7586          Temp off = emit_extract_vector(ctx, offset, i, v1);
7587          coords[i] = bld.vadd32(bld.def(v1), coords[i], off);
7588       }
7589       has_offset = false;
7590    }
7591
7592    /* Build tex instruction */
7593    unsigned dmask = nir_ssa_def_components_read(&instr->dest.ssa);
7594    unsigned dim = ctx->options->chip_class >= GFX10 && instr->sampler_dim != GLSL_SAMPLER_DIM_BUF
7595                   ? ac_get_sampler_dim(ctx->options->chip_class, instr->sampler_dim, instr->is_array)
7596                   : 0;
7597    Temp dst = get_ssa_temp(ctx, &instr->dest.ssa);
7598    Temp tmp_dst = dst;
7599
7600    /* gather4 selects the component by dmask and always returns vec4 */
7601    if (instr->op == nir_texop_tg4) {
7602       assert(instr->dest.ssa.num_components == 4);
7603       if (instr->is_shadow)
7604          dmask = 1;
7605       else
7606          dmask = 1 << instr->component;
7607       if (tg4_integer_cube_workaround || dst.type() == RegType::sgpr)
7608          tmp_dst = bld.tmp(v4);
7609    } else if (instr->op == nir_texop_samples_identical) {
7610       tmp_dst = bld.tmp(v1);
7611    } else if (util_bitcount(dmask) != instr->dest.ssa.num_components || dst.type() == RegType::sgpr) {
7612       tmp_dst = bld.tmp(RegClass(RegType::vgpr, util_bitcount(dmask)));
7613    }
7614
7615    aco_ptr<MIMG_instruction> tex;
7616    if (instr->op == nir_texop_txs || instr->op == nir_texop_query_levels) {
7617       if (!has_lod)
7618          lod = bld.vop1(aco_opcode::v_mov_b32, bld.def(v1), Operand(0u));
7619
7620       bool div_by_6 = instr->op == nir_texop_txs &&
7621                       instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE &&
7622                       instr->is_array &&
7623                       (dmask & (1 << 2));
7624       if (tmp_dst.id() == dst.id() && div_by_6)
7625          tmp_dst = bld.tmp(tmp_dst.regClass());
7626
7627       tex.reset(create_instruction<MIMG_instruction>(aco_opcode::image_get_resinfo, Format::MIMG, 3, 1));
7628       tex->operands[0] = Operand(resource);
7629       tex->operands[1] = Operand(s4); /* no sampler */
7630       tex->operands[2] = Operand(as_vgpr(ctx,lod));
7631       if (ctx->options->chip_class == GFX9 &&
7632           instr->op == nir_texop_txs &&
7633           instr->sampler_dim == GLSL_SAMPLER_DIM_1D &&
7634           instr->is_array) {
7635          tex->dmask = (dmask & 0x1) | ((dmask & 0x2) << 1);
7636       } else if (instr->op == nir_texop_query_levels) {
7637          tex->dmask = 1 << 3;
7638       } else {
7639          tex->dmask = dmask;
7640       }
7641       tex->da = da;
7642       tex->definitions[0] = Definition(tmp_dst);
7643       tex->dim = dim;
7644       tex->can_reorder = true;
7645       ctx->block->instructions.emplace_back(std::move(tex));
7646
7647       if (div_by_6) {
7648          /* divide 3rd value by 6 by multiplying with magic number */
7649          emit_split_vector(ctx, tmp_dst, tmp_dst.size());
7650          Temp c = bld.copy(bld.def(s1), Operand((uint32_t) 0x2AAAAAAB));
7651          Temp by_6 = bld.vop3(aco_opcode::v_mul_hi_i32, bld.def(v1), emit_extract_vector(ctx, tmp_dst, 2, v1), c);
7652          assert(instr->dest.ssa.num_components == 3);
7653          Temp tmp = dst.type() == RegType::vgpr ? dst : bld.tmp(v3);
7654          tmp_dst = bld.pseudo(aco_opcode::p_create_vector, Definition(tmp),
7655                               emit_extract_vector(ctx, tmp_dst, 0, v1),
7656                               emit_extract_vector(ctx, tmp_dst, 1, v1),
7657                               by_6);
7658
7659       }
7660
7661       expand_vector(ctx, tmp_dst, dst, instr->dest.ssa.num_components, dmask);
7662       return;
7663    }
7664
7665    Temp tg4_compare_cube_wa64 = Temp();
7666
7667    if (tg4_integer_workarounds) {
7668       tex.reset(create_instruction<MIMG_instruction>(aco_opcode::image_get_resinfo, Format::MIMG, 3, 1));
7669       tex->operands[0] = Operand(resource);
7670       tex->operands[1] = Operand(s4); /* no sampler */
7671       tex->operands[2] = bld.vop1(aco_opcode::v_mov_b32, bld.def(v1), Operand(0u));
7672       tex->dim = dim;
7673       tex->dmask = 0x3;
7674       tex->da = da;
7675       Temp size = bld.tmp(v2);
7676       tex->definitions[0] = Definition(size);
7677       tex->can_reorder = true;
7678       ctx->block->instructions.emplace_back(std::move(tex));
7679       emit_split_vector(ctx, size, size.size());
7680
7681       Temp half_texel[2];
7682       for (unsigned i = 0; i < 2; i++) {
7683          half_texel[i] = emit_extract_vector(ctx, size, i, v1);
7684          half_texel[i] = bld.vop1(aco_opcode::v_cvt_f32_i32, bld.def(v1), half_texel[i]);
7685          half_texel[i] = bld.vop1(aco_opcode::v_rcp_iflag_f32, bld.def(v1), half_texel[i]);
7686          half_texel[i] = bld.vop2(aco_opcode::v_mul_f32, bld.def(v1), Operand(0xbf000000/*-0.5*/), half_texel[i]);
7687       }
7688
7689       Temp new_coords[2] = {
7690          bld.vop2(aco_opcode::v_add_f32, bld.def(v1), coords[0], half_texel[0]),
7691          bld.vop2(aco_opcode::v_add_f32, bld.def(v1), coords[1], half_texel[1])
7692       };
7693
7694       if (tg4_integer_cube_workaround) {
7695          // see comment in ac_nir_to_llvm.c's lower_gather4_integer()
7696          Temp desc[resource.size()];
7697          aco_ptr<Instruction> split{create_instruction<Pseudo_instruction>(aco_opcode::p_split_vector,
7698                                                                            Format::PSEUDO, 1, resource.size())};
7699          split->operands[0] = Operand(resource);
7700          for (unsigned i = 0; i < resource.size(); i++) {
7701             desc[i] = bld.tmp(s1);
7702             split->definitions[i] = Definition(desc[i]);
7703          }
7704          ctx->block->instructions.emplace_back(std::move(split));
7705
7706          Temp dfmt = bld.sop2(aco_opcode::s_bfe_u32, bld.def(s1), bld.def(s1, scc), desc[1], Operand(20u | (6u << 16)));
7707          Temp compare_cube_wa = bld.sopc(aco_opcode::s_cmp_eq_u32, bld.def(s1, scc), dfmt,
7708                                          Operand((uint32_t)V_008F14_IMG_DATA_FORMAT_8_8_8_8));
7709
7710          Temp nfmt;
7711          if (stype == GLSL_TYPE_UINT) {
7712             nfmt = bld.sop2(aco_opcode::s_cselect_b32, bld.def(s1),
7713                             Operand((uint32_t)V_008F14_IMG_NUM_FORMAT_USCALED),
7714                             Operand((uint32_t)V_008F14_IMG_NUM_FORMAT_UINT),
7715                             bld.scc(compare_cube_wa));
7716          } else {
7717             nfmt = bld.sop2(aco_opcode::s_cselect_b32, bld.def(s1),
7718                             Operand((uint32_t)V_008F14_IMG_NUM_FORMAT_SSCALED),
7719                             Operand((uint32_t)V_008F14_IMG_NUM_FORMAT_SINT),
7720                             bld.scc(compare_cube_wa));
7721          }
7722          tg4_compare_cube_wa64 = bld.tmp(bld.lm);
7723          bool_to_vector_condition(ctx, compare_cube_wa, tg4_compare_cube_wa64);
7724
7725          nfmt = bld.sop2(aco_opcode::s_lshl_b32, bld.def(s1), bld.def(s1, scc), nfmt, Operand(26u));
7726
7727          desc[1] = bld.sop2(aco_opcode::s_and_b32, bld.def(s1), bld.def(s1, scc), desc[1],
7728                             Operand((uint32_t)C_008F14_NUM_FORMAT));
7729          desc[1] = bld.sop2(aco_opcode::s_or_b32, bld.def(s1), bld.def(s1, scc), desc[1], nfmt);
7730
7731          aco_ptr<Instruction> vec{create_instruction<Pseudo_instruction>(aco_opcode::p_create_vector,
7732                                                                          Format::PSEUDO, resource.size(), 1)};
7733          for (unsigned i = 0; i < resource.size(); i++)
7734             vec->operands[i] = Operand(desc[i]);
7735          resource = bld.tmp(resource.regClass());
7736          vec->definitions[0] = Definition(resource);
7737          ctx->block->instructions.emplace_back(std::move(vec));
7738
7739          new_coords[0] = bld.vop2(aco_opcode::v_cndmask_b32, bld.def(v1),
7740                                   new_coords[0], coords[0], tg4_compare_cube_wa64);
7741          new_coords[1] = bld.vop2(aco_opcode::v_cndmask_b32, bld.def(v1),
7742                                   new_coords[1], coords[1], tg4_compare_cube_wa64);
7743       }
7744       coords[0] = new_coords[0];
7745       coords[1] = new_coords[1];
7746    }
7747
7748    if (instr->sampler_dim == GLSL_SAMPLER_DIM_BUF) {
7749       //FIXME: if (ctx->abi->gfx9_stride_size_workaround) return ac_build_buffer_load_format_gfx9_safe()
7750
7751       assert(coords.size() == 1);
7752       unsigned last_bit = util_last_bit(nir_ssa_def_components_read(&instr->dest.ssa));
7753       aco_opcode op;
7754       switch (last_bit) {
7755       case 1:
7756          op = aco_opcode::buffer_load_format_x; break;
7757       case 2:
7758          op = aco_opcode::buffer_load_format_xy; break;
7759       case 3:
7760          op = aco_opcode::buffer_load_format_xyz; break;
7761       case 4:
7762          op = aco_opcode::buffer_load_format_xyzw; break;
7763       default:
7764          unreachable("Tex instruction loads more than 4 components.");
7765       }
7766
7767       /* if the instruction return value matches exactly the nir dest ssa, we can use it directly */
7768       if (last_bit == instr->dest.ssa.num_components && dst.type() == RegType::vgpr)
7769          tmp_dst = dst;
7770       else
7771          tmp_dst = bld.tmp(RegType::vgpr, last_bit);
7772
7773       aco_ptr<MUBUF_instruction> mubuf{create_instruction<MUBUF_instruction>(op, Format::MUBUF, 3, 1)};
7774       mubuf->operands[0] = Operand(resource);
7775       mubuf->operands[1] = Operand(coords[0]);
7776       mubuf->operands[2] = Operand((uint32_t) 0);
7777       mubuf->definitions[0] = Definition(tmp_dst);
7778       mubuf->idxen = true;
7779       mubuf->can_reorder = true;
7780       ctx->block->instructions.emplace_back(std::move(mubuf));
7781
7782       expand_vector(ctx, tmp_dst, dst, instr->dest.ssa.num_components, (1 << last_bit) - 1);
7783       return;
7784    }
7785
7786    /* gather MIMG address components */
7787    std::vector<Temp> args;
7788    if (has_offset)
7789       args.emplace_back(offset);
7790    if (has_bias)
7791       args.emplace_back(bias);
7792    if (has_compare)
7793       args.emplace_back(compare);
7794    if (has_derivs)
7795       args.insert(args.end(), derivs.begin(), derivs.end());
7796
7797    args.insert(args.end(), coords.begin(), coords.end());
7798    if (has_sample_index)
7799       args.emplace_back(sample_index);
7800    if (has_lod)
7801       args.emplace_back(lod);
7802
7803    Temp arg = bld.tmp(RegClass(RegType::vgpr, args.size()));
7804    aco_ptr<Instruction> vec{create_instruction<Pseudo_instruction>(aco_opcode::p_create_vector, Format::PSEUDO, args.size(), 1)};
7805    vec->definitions[0] = Definition(arg);
7806    for (unsigned i = 0; i < args.size(); i++)
7807       vec->operands[i] = Operand(args[i]);
7808    ctx->block->instructions.emplace_back(std::move(vec));
7809
7810
7811    if (instr->op == nir_texop_txf ||
7812        instr->op == nir_texop_txf_ms ||
7813        instr->op == nir_texop_samples_identical ||
7814        instr->op == nir_texop_fragment_fetch ||
7815        instr->op == nir_texop_fragment_mask_fetch) {
7816       aco_opcode op = level_zero || instr->sampler_dim == GLSL_SAMPLER_DIM_MS || instr->sampler_dim == GLSL_SAMPLER_DIM_SUBPASS_MS ? aco_opcode::image_load : aco_opcode::image_load_mip;
7817       tex.reset(create_instruction<MIMG_instruction>(op, Format::MIMG, 3, 1));
7818       tex->operands[0] = Operand(resource);
7819       tex->operands[1] = Operand(s4); /* no sampler */
7820       tex->operands[2] = Operand(arg);
7821       tex->dim = dim;
7822       tex->dmask = dmask;
7823       tex->unrm = true;
7824       tex->da = da;
7825       tex->definitions[0] = Definition(tmp_dst);
7826       tex->can_reorder = true;
7827       ctx->block->instructions.emplace_back(std::move(tex));
7828
7829       if (instr->op == nir_texop_samples_identical) {
7830          assert(dmask == 1 && dst.regClass() == v1);
7831          assert(dst.id() != tmp_dst.id());
7832
7833          Temp tmp = bld.tmp(bld.lm);
7834          bld.vopc(aco_opcode::v_cmp_eq_u32, Definition(tmp), Operand(0u), tmp_dst).def(0).setHint(vcc);
7835          bld.vop2_e64(aco_opcode::v_cndmask_b32, Definition(dst), Operand(0u), Operand((uint32_t)-1), tmp);
7836
7837       } else {
7838          expand_vector(ctx, tmp_dst, dst, instr->dest.ssa.num_components, dmask);
7839       }
7840       return;
7841    }
7842
7843    // TODO: would be better to do this by adding offsets, but needs the opcodes ordered.
7844    aco_opcode opcode = aco_opcode::image_sample;
7845    if (has_offset) { /* image_sample_*_o */
7846       if (has_compare) {
7847          opcode = aco_opcode::image_sample_c_o;
7848          if (has_derivs)
7849             opcode = aco_opcode::image_sample_c_d_o;
7850          if (has_bias)
7851             opcode = aco_opcode::image_sample_c_b_o;
7852          if (level_zero)
7853             opcode = aco_opcode::image_sample_c_lz_o;
7854          if (has_lod)
7855             opcode = aco_opcode::image_sample_c_l_o;
7856       } else {
7857          opcode = aco_opcode::image_sample_o;
7858          if (has_derivs)
7859             opcode = aco_opcode::image_sample_d_o;
7860          if (has_bias)
7861             opcode = aco_opcode::image_sample_b_o;
7862          if (level_zero)
7863             opcode = aco_opcode::image_sample_lz_o;
7864          if (has_lod)
7865             opcode = aco_opcode::image_sample_l_o;
7866       }
7867    } else { /* no offset */
7868       if (has_compare) {
7869          opcode = aco_opcode::image_sample_c;
7870          if (has_derivs)
7871             opcode = aco_opcode::image_sample_c_d;
7872          if (has_bias)
7873             opcode = aco_opcode::image_sample_c_b;
7874          if (level_zero)
7875             opcode = aco_opcode::image_sample_c_lz;
7876          if (has_lod)
7877             opcode = aco_opcode::image_sample_c_l;
7878       } else {
7879          opcode = aco_opcode::image_sample;
7880          if (has_derivs)
7881             opcode = aco_opcode::image_sample_d;
7882          if (has_bias)
7883             opcode = aco_opcode::image_sample_b;
7884          if (level_zero)
7885             opcode = aco_opcode::image_sample_lz;
7886          if (has_lod)
7887             opcode = aco_opcode::image_sample_l;
7888       }
7889    }
7890
7891    if (instr->op == nir_texop_tg4) {
7892       if (has_offset) {
7893          opcode = aco_opcode::image_gather4_lz_o;
7894          if (has_compare)
7895             opcode = aco_opcode::image_gather4_c_lz_o;
7896       } else {
7897          opcode = aco_opcode::image_gather4_lz;
7898          if (has_compare)
7899             opcode = aco_opcode::image_gather4_c_lz;
7900       }
7901    } else if (instr->op == nir_texop_lod) {
7902       opcode = aco_opcode::image_get_lod;
7903    }
7904
7905    /* we don't need the bias, sample index, compare value or offset to be
7906     * computed in WQM but if the p_create_vector copies the coordinates, then it
7907     * needs to be in WQM */
7908    if (ctx->stage == fragment_fs &&
7909        !has_derivs && !has_lod && !level_zero &&
7910        instr->sampler_dim != GLSL_SAMPLER_DIM_MS &&
7911        instr->sampler_dim != GLSL_SAMPLER_DIM_SUBPASS_MS)
7912       arg = emit_wqm(ctx, arg, bld.tmp(arg.regClass()), true);
7913
7914    tex.reset(create_instruction<MIMG_instruction>(opcode, Format::MIMG, 3, 1));
7915    tex->operands[0] = Operand(resource);
7916    tex->operands[1] = Operand(sampler);
7917    tex->operands[2] = Operand(arg);
7918    tex->dim = dim;
7919    tex->dmask = dmask;
7920    tex->da = da;
7921    tex->definitions[0] = Definition(tmp_dst);
7922    tex->can_reorder = true;
7923    ctx->block->instructions.emplace_back(std::move(tex));
7924
7925    if (tg4_integer_cube_workaround) {
7926       assert(tmp_dst.id() != dst.id());
7927       assert(tmp_dst.size() == dst.size() && dst.size() == 4);
7928
7929       emit_split_vector(ctx, tmp_dst, tmp_dst.size());
7930       Temp val[4];
7931       for (unsigned i = 0; i < dst.size(); i++) {
7932          val[i] = emit_extract_vector(ctx, tmp_dst, i, v1);
7933          Temp cvt_val;
7934          if (stype == GLSL_TYPE_UINT)
7935             cvt_val = bld.vop1(aco_opcode::v_cvt_u32_f32, bld.def(v1), val[i]);
7936          else
7937             cvt_val = bld.vop1(aco_opcode::v_cvt_i32_f32, bld.def(v1), val[i]);
7938          val[i] = bld.vop2(aco_opcode::v_cndmask_b32, bld.def(v1), val[i], cvt_val, tg4_compare_cube_wa64);
7939       }
7940       Temp tmp = dst.regClass() == v4 ? dst : bld.tmp(v4);
7941       tmp_dst = bld.pseudo(aco_opcode::p_create_vector, Definition(tmp),
7942                            val[0], val[1], val[2], val[3]);
7943    }
7944    unsigned mask = instr->op == nir_texop_tg4 ? 0xF : dmask;
7945    expand_vector(ctx, tmp_dst, dst, instr->dest.ssa.num_components, mask);
7946
7947 }
7948
7949
7950 Operand get_phi_operand(isel_context *ctx, nir_ssa_def *ssa)
7951 {
7952    Temp tmp = get_ssa_temp(ctx, ssa);
7953    if (ssa->parent_instr->type == nir_instr_type_ssa_undef)
7954       return Operand(tmp.regClass());
7955    else
7956       return Operand(tmp);
7957 }
7958
7959 void visit_phi(isel_context *ctx, nir_phi_instr *instr)
7960 {
7961    aco_ptr<Pseudo_instruction> phi;
7962    Temp dst = get_ssa_temp(ctx, &instr->dest.ssa);
7963    assert(instr->dest.ssa.bit_size != 1 || dst.regClass() == ctx->program->lane_mask);
7964
7965    bool logical = !dst.is_linear() || ctx->divergent_vals[instr->dest.ssa.index];
7966    logical |= ctx->block->kind & block_kind_merge;
7967    aco_opcode opcode = logical ? aco_opcode::p_phi : aco_opcode::p_linear_phi;
7968
7969    /* we want a sorted list of sources, since the predecessor list is also sorted */
7970    std::map<unsigned, nir_ssa_def*> phi_src;
7971    nir_foreach_phi_src(src, instr)
7972       phi_src[src->pred->index] = src->src.ssa;
7973
7974    std::vector<unsigned>& preds = logical ? ctx->block->logical_preds : ctx->block->linear_preds;
7975    unsigned num_operands = 0;
7976    Operand operands[std::max(exec_list_length(&instr->srcs), (unsigned)preds.size())];
7977    unsigned num_defined = 0;
7978    unsigned cur_pred_idx = 0;
7979    for (std::pair<unsigned, nir_ssa_def *> src : phi_src) {
7980       if (cur_pred_idx < preds.size()) {
7981          /* handle missing preds (IF merges with discard/break) and extra preds (loop exit with discard) */
7982          unsigned block = ctx->cf_info.nir_to_aco[src.first];
7983          unsigned skipped = 0;
7984          while (cur_pred_idx + skipped < preds.size() && preds[cur_pred_idx + skipped] != block)
7985             skipped++;
7986          if (cur_pred_idx + skipped < preds.size()) {
7987             for (unsigned i = 0; i < skipped; i++)
7988                operands[num_operands++] = Operand(dst.regClass());
7989             cur_pred_idx += skipped;
7990          } else {
7991             continue;
7992          }
7993       }
7994       cur_pred_idx++;
7995       Operand op = get_phi_operand(ctx, src.second);
7996       operands[num_operands++] = op;
7997       num_defined += !op.isUndefined();
7998    }
7999    /* handle block_kind_continue_or_break at loop exit blocks */
8000    while (cur_pred_idx++ < preds.size())
8001       operands[num_operands++] = Operand(dst.regClass());
8002
8003    if (num_defined == 0) {
8004       Builder bld(ctx->program, ctx->block);
8005       if (dst.regClass() == s1) {
8006          bld.sop1(aco_opcode::s_mov_b32, Definition(dst), Operand(0u));
8007       } else if (dst.regClass() == v1) {
8008          bld.vop1(aco_opcode::v_mov_b32, Definition(dst), Operand(0u));
8009       } else {
8010          aco_ptr<Pseudo_instruction> vec{create_instruction<Pseudo_instruction>(aco_opcode::p_create_vector, Format::PSEUDO, dst.size(), 1)};
8011          for (unsigned i = 0; i < dst.size(); i++)
8012             vec->operands[i] = Operand(0u);
8013          vec->definitions[0] = Definition(dst);
8014          ctx->block->instructions.emplace_back(std::move(vec));
8015       }
8016       return;
8017    }
8018
8019    /* we can use a linear phi in some cases if one src is undef */
8020    if (dst.is_linear() && ctx->block->kind & block_kind_merge && num_defined == 1) {
8021       phi.reset(create_instruction<Pseudo_instruction>(aco_opcode::p_linear_phi, Format::PSEUDO, num_operands, 1));
8022
8023       Block *linear_else = &ctx->program->blocks[ctx->block->linear_preds[1]];
8024       Block *invert = &ctx->program->blocks[linear_else->linear_preds[0]];
8025       assert(invert->kind & block_kind_invert);
8026
8027       unsigned then_block = invert->linear_preds[0];
8028
8029       Block* insert_block = NULL;
8030       for (unsigned i = 0; i < num_operands; i++) {
8031          Operand op = operands[i];
8032          if (op.isUndefined())
8033             continue;
8034          insert_block = ctx->block->logical_preds[i] == then_block ? invert : ctx->block;
8035          phi->operands[0] = op;
8036          break;
8037       }
8038       assert(insert_block); /* should be handled by the "num_defined == 0" case above */
8039       phi->operands[1] = Operand(dst.regClass());
8040       phi->definitions[0] = Definition(dst);
8041       insert_block->instructions.emplace(insert_block->instructions.begin(), std::move(phi));
8042       return;
8043    }
8044
8045    /* try to scalarize vector phis */
8046    if (instr->dest.ssa.bit_size != 1 && dst.size() > 1) {
8047       // TODO: scalarize linear phis on divergent ifs
8048       bool can_scalarize = (opcode == aco_opcode::p_phi || !(ctx->block->kind & block_kind_merge));
8049       std::array<Temp, NIR_MAX_VEC_COMPONENTS> new_vec;
8050       for (unsigned i = 0; can_scalarize && (i < num_operands); i++) {
8051          Operand src = operands[i];
8052          if (src.isTemp() && ctx->allocated_vec.find(src.tempId()) == ctx->allocated_vec.end())
8053             can_scalarize = false;
8054       }
8055       if (can_scalarize) {
8056          unsigned num_components = instr->dest.ssa.num_components;
8057          assert(dst.size() % num_components == 0);
8058          RegClass rc = RegClass(dst.type(), dst.size() / num_components);
8059
8060          aco_ptr<Pseudo_instruction> vec{create_instruction<Pseudo_instruction>(aco_opcode::p_create_vector, Format::PSEUDO, num_components, 1)};
8061          for (unsigned k = 0; k < num_components; k++) {
8062             phi.reset(create_instruction<Pseudo_instruction>(opcode, Format::PSEUDO, num_operands, 1));
8063             for (unsigned i = 0; i < num_operands; i++) {
8064                Operand src = operands[i];
8065                phi->operands[i] = src.isTemp() ? Operand(ctx->allocated_vec[src.tempId()][k]) : Operand(rc);
8066             }
8067             Temp phi_dst = {ctx->program->allocateId(), rc};
8068             phi->definitions[0] = Definition(phi_dst);
8069             ctx->block->instructions.emplace(ctx->block->instructions.begin(), std::move(phi));
8070             new_vec[k] = phi_dst;
8071             vec->operands[k] = Operand(phi_dst);
8072          }
8073          vec->definitions[0] = Definition(dst);
8074          ctx->block->instructions.emplace_back(std::move(vec));
8075          ctx->allocated_vec.emplace(dst.id(), new_vec);
8076          return;
8077       }
8078    }
8079
8080    phi.reset(create_instruction<Pseudo_instruction>(opcode, Format::PSEUDO, num_operands, 1));
8081    for (unsigned i = 0; i < num_operands; i++)
8082       phi->operands[i] = operands[i];
8083    phi->definitions[0] = Definition(dst);
8084    ctx->block->instructions.emplace(ctx->block->instructions.begin(), std::move(phi));
8085 }
8086
8087
8088 void visit_undef(isel_context *ctx, nir_ssa_undef_instr *instr)
8089 {
8090    Temp dst = get_ssa_temp(ctx, &instr->def);
8091
8092    assert(dst.type() == RegType::sgpr);
8093
8094    if (dst.size() == 1) {
8095       Builder(ctx->program, ctx->block).copy(Definition(dst), Operand(0u));
8096    } else {
8097       aco_ptr<Pseudo_instruction> vec{create_instruction<Pseudo_instruction>(aco_opcode::p_create_vector, Format::PSEUDO, dst.size(), 1)};
8098       for (unsigned i = 0; i < dst.size(); i++)
8099          vec->operands[i] = Operand(0u);
8100       vec->definitions[0] = Definition(dst);
8101       ctx->block->instructions.emplace_back(std::move(vec));
8102    }
8103 }
8104
8105 void visit_jump(isel_context *ctx, nir_jump_instr *instr)
8106 {
8107    Builder bld(ctx->program, ctx->block);
8108    Block *logical_target;
8109    append_logical_end(ctx->block);
8110    unsigned idx = ctx->block->index;
8111
8112    switch (instr->type) {
8113    case nir_jump_break:
8114       logical_target = ctx->cf_info.parent_loop.exit;
8115       add_logical_edge(idx, logical_target);
8116       ctx->block->kind |= block_kind_break;
8117
8118       if (!ctx->cf_info.parent_if.is_divergent &&
8119           !ctx->cf_info.parent_loop.has_divergent_continue) {
8120          /* uniform break - directly jump out of the loop */
8121          ctx->block->kind |= block_kind_uniform;
8122          ctx->cf_info.has_branch = true;
8123          bld.branch(aco_opcode::p_branch);
8124          add_linear_edge(idx, logical_target);
8125          return;
8126       }
8127       ctx->cf_info.parent_loop.has_divergent_branch = true;
8128       ctx->cf_info.nir_to_aco[instr->instr.block->index] = ctx->block->index;
8129       break;
8130    case nir_jump_continue:
8131       logical_target = &ctx->program->blocks[ctx->cf_info.parent_loop.header_idx];
8132       add_logical_edge(idx, logical_target);
8133       ctx->block->kind |= block_kind_continue;
8134
8135       if (ctx->cf_info.parent_if.is_divergent) {
8136          /* for potential uniform breaks after this continue,
8137             we must ensure that they are handled correctly */
8138          ctx->cf_info.parent_loop.has_divergent_continue = true;
8139          ctx->cf_info.parent_loop.has_divergent_branch = true;
8140          ctx->cf_info.nir_to_aco[instr->instr.block->index] = ctx->block->index;
8141       } else {
8142          /* uniform continue - directly jump to the loop header */
8143          ctx->block->kind |= block_kind_uniform;
8144          ctx->cf_info.has_branch = true;
8145          bld.branch(aco_opcode::p_branch);
8146          add_linear_edge(idx, logical_target);
8147          return;
8148       }
8149       break;
8150    default:
8151       fprintf(stderr, "Unknown NIR jump instr: ");
8152       nir_print_instr(&instr->instr, stderr);
8153       fprintf(stderr, "\n");
8154       abort();
8155    }
8156
8157    if (ctx->cf_info.parent_if.is_divergent && !ctx->cf_info.exec_potentially_empty_break) {
8158       ctx->cf_info.exec_potentially_empty_break = true;
8159       ctx->cf_info.exec_potentially_empty_break_depth = ctx->cf_info.loop_nest_depth;
8160    }
8161
8162    /* remove critical edges from linear CFG */
8163    bld.branch(aco_opcode::p_branch);
8164    Block* break_block = ctx->program->create_and_insert_block();
8165    break_block->loop_nest_depth = ctx->cf_info.loop_nest_depth;
8166    break_block->kind |= block_kind_uniform;
8167    add_linear_edge(idx, break_block);
8168    /* the loop_header pointer might be invalidated by this point */
8169    if (instr->type == nir_jump_continue)
8170       logical_target = &ctx->program->blocks[ctx->cf_info.parent_loop.header_idx];
8171    add_linear_edge(break_block->index, logical_target);
8172    bld.reset(break_block);
8173    bld.branch(aco_opcode::p_branch);
8174
8175    Block* continue_block = ctx->program->create_and_insert_block();
8176    continue_block->loop_nest_depth = ctx->cf_info.loop_nest_depth;
8177    add_linear_edge(idx, continue_block);
8178    append_logical_start(continue_block);
8179    ctx->block = continue_block;
8180    return;
8181 }
8182
8183 void visit_block(isel_context *ctx, nir_block *block)
8184 {
8185    nir_foreach_instr(instr, block) {
8186       switch (instr->type) {
8187       case nir_instr_type_alu:
8188          visit_alu_instr(ctx, nir_instr_as_alu(instr));
8189          break;
8190       case nir_instr_type_load_const:
8191          visit_load_const(ctx, nir_instr_as_load_const(instr));
8192          break;
8193       case nir_instr_type_intrinsic:
8194          visit_intrinsic(ctx, nir_instr_as_intrinsic(instr));
8195          break;
8196       case nir_instr_type_tex:
8197          visit_tex(ctx, nir_instr_as_tex(instr));
8198          break;
8199       case nir_instr_type_phi:
8200          visit_phi(ctx, nir_instr_as_phi(instr));
8201          break;
8202       case nir_instr_type_ssa_undef:
8203          visit_undef(ctx, nir_instr_as_ssa_undef(instr));
8204          break;
8205       case nir_instr_type_deref:
8206          break;
8207       case nir_instr_type_jump:
8208          visit_jump(ctx, nir_instr_as_jump(instr));
8209          break;
8210       default:
8211          fprintf(stderr, "Unknown NIR instr type: ");
8212          nir_print_instr(instr, stderr);
8213          fprintf(stderr, "\n");
8214          //abort();
8215       }
8216    }
8217
8218    if (!ctx->cf_info.parent_loop.has_divergent_branch)
8219       ctx->cf_info.nir_to_aco[block->index] = ctx->block->index;
8220 }
8221
8222
8223
8224 static void visit_loop(isel_context *ctx, nir_loop *loop)
8225 {
8226    //TODO: we might want to wrap the loop around a branch if exec_potentially_empty=true
8227    append_logical_end(ctx->block);
8228    ctx->block->kind |= block_kind_loop_preheader | block_kind_uniform;
8229    Builder bld(ctx->program, ctx->block);
8230    bld.branch(aco_opcode::p_branch);
8231    unsigned loop_preheader_idx = ctx->block->index;
8232
8233    Block loop_exit = Block();
8234    loop_exit.loop_nest_depth = ctx->cf_info.loop_nest_depth;
8235    loop_exit.kind |= (block_kind_loop_exit | (ctx->block->kind & block_kind_top_level));
8236
8237    Block* loop_header = ctx->program->create_and_insert_block();
8238    loop_header->loop_nest_depth = ctx->cf_info.loop_nest_depth + 1;
8239    loop_header->kind |= block_kind_loop_header;
8240    add_edge(loop_preheader_idx, loop_header);
8241    ctx->block = loop_header;
8242
8243    /* emit loop body */
8244    unsigned loop_header_idx = loop_header->index;
8245    loop_info_RAII loop_raii(ctx, loop_header_idx, &loop_exit);
8246    append_logical_start(ctx->block);
8247    visit_cf_list(ctx, &loop->body);
8248
8249    //TODO: what if a loop ends with a unconditional or uniformly branched continue and this branch is never taken?
8250    if (!ctx->cf_info.has_branch) {
8251       append_logical_end(ctx->block);
8252       if (ctx->cf_info.exec_potentially_empty_discard || ctx->cf_info.exec_potentially_empty_break) {
8253          /* Discards can result in code running with an empty exec mask.
8254           * This would result in divergent breaks not ever being taken. As a
8255           * workaround, break the loop when the loop mask is empty instead of
8256           * always continuing. */
8257          ctx->block->kind |= (block_kind_continue_or_break | block_kind_uniform);
8258          unsigned block_idx = ctx->block->index;
8259
8260          /* create helper blocks to avoid critical edges */
8261          Block *break_block = ctx->program->create_and_insert_block();
8262          break_block->loop_nest_depth = ctx->cf_info.loop_nest_depth;
8263          break_block->kind = block_kind_uniform;
8264          bld.reset(break_block);
8265          bld.branch(aco_opcode::p_branch);
8266          add_linear_edge(block_idx, break_block);
8267          add_linear_edge(break_block->index, &loop_exit);
8268
8269          Block *continue_block = ctx->program->create_and_insert_block();
8270          continue_block->loop_nest_depth = ctx->cf_info.loop_nest_depth;
8271          continue_block->kind = block_kind_uniform;
8272          bld.reset(continue_block);
8273          bld.branch(aco_opcode::p_branch);
8274          add_linear_edge(block_idx, continue_block);
8275          add_linear_edge(continue_block->index, &ctx->program->blocks[loop_header_idx]);
8276
8277          if (!ctx->cf_info.parent_loop.has_divergent_branch)
8278             add_logical_edge(block_idx, &ctx->program->blocks[loop_header_idx]);
8279          ctx->block = &ctx->program->blocks[block_idx];
8280       } else {
8281          ctx->block->kind |= (block_kind_continue | block_kind_uniform);
8282          if (!ctx->cf_info.parent_loop.has_divergent_branch)
8283             add_edge(ctx->block->index, &ctx->program->blocks[loop_header_idx]);
8284          else
8285             add_linear_edge(ctx->block->index, &ctx->program->blocks[loop_header_idx]);
8286       }
8287
8288       bld.reset(ctx->block);
8289       bld.branch(aco_opcode::p_branch);
8290    }
8291
8292    /* fixup phis in loop header from unreachable blocks */
8293    if (ctx->cf_info.has_branch || ctx->cf_info.parent_loop.has_divergent_branch) {
8294       bool linear = ctx->cf_info.has_branch;
8295       bool logical = ctx->cf_info.has_branch || ctx->cf_info.parent_loop.has_divergent_branch;
8296       for (aco_ptr<Instruction>& instr : ctx->program->blocks[loop_header_idx].instructions) {
8297          if ((logical && instr->opcode == aco_opcode::p_phi) ||
8298              (linear && instr->opcode == aco_opcode::p_linear_phi)) {
8299             /* the last operand should be the one that needs to be removed */
8300             instr->operands.pop_back();
8301          } else if (!is_phi(instr)) {
8302             break;
8303          }
8304       }
8305    }
8306
8307    ctx->cf_info.has_branch = false;
8308
8309    // TODO: if the loop has not a single exit, we must add one °°
8310    /* emit loop successor block */
8311    ctx->block = ctx->program->insert_block(std::move(loop_exit));
8312    append_logical_start(ctx->block);
8313
8314    #if 0
8315    // TODO: check if it is beneficial to not branch on continues
8316    /* trim linear phis in loop header */
8317    for (auto&& instr : loop_entry->instructions) {
8318       if (instr->opcode == aco_opcode::p_linear_phi) {
8319          aco_ptr<Pseudo_instruction> new_phi{create_instruction<Pseudo_instruction>(aco_opcode::p_linear_phi, Format::PSEUDO, loop_entry->linear_predecessors.size(), 1)};
8320          new_phi->definitions[0] = instr->definitions[0];
8321          for (unsigned i = 0; i < new_phi->operands.size(); i++)
8322             new_phi->operands[i] = instr->operands[i];
8323          /* check that the remaining operands are all the same */
8324          for (unsigned i = new_phi->operands.size(); i < instr->operands.size(); i++)
8325             assert(instr->operands[i].tempId() == instr->operands.back().tempId());
8326          instr.swap(new_phi);
8327       } else if (instr->opcode == aco_opcode::p_phi) {
8328          continue;
8329       } else {
8330          break;
8331       }
8332    }
8333    #endif
8334 }
8335
8336 static void begin_divergent_if_then(isel_context *ctx, if_context *ic, Temp cond)
8337 {
8338    ic->cond = cond;
8339
8340    append_logical_end(ctx->block);
8341    ctx->block->kind |= block_kind_branch;
8342
8343    /* branch to linear then block */
8344    assert(cond.regClass() == ctx->program->lane_mask);
8345    aco_ptr<Pseudo_branch_instruction> branch;
8346    branch.reset(create_instruction<Pseudo_branch_instruction>(aco_opcode::p_cbranch_z, Format::PSEUDO_BRANCH, 1, 0));
8347    branch->operands[0] = Operand(cond);
8348    ctx->block->instructions.push_back(std::move(branch));
8349
8350    ic->BB_if_idx = ctx->block->index;
8351    ic->BB_invert = Block();
8352    ic->BB_invert.loop_nest_depth = ctx->cf_info.loop_nest_depth;
8353    /* Invert blocks are intentionally not marked as top level because they
8354     * are not part of the logical cfg. */
8355    ic->BB_invert.kind |= block_kind_invert;
8356    ic->BB_endif = Block();
8357    ic->BB_endif.loop_nest_depth = ctx->cf_info.loop_nest_depth;
8358    ic->BB_endif.kind |= (block_kind_merge | (ctx->block->kind & block_kind_top_level));
8359
8360    ic->exec_potentially_empty_discard_old = ctx->cf_info.exec_potentially_empty_discard;
8361    ic->exec_potentially_empty_break_old = ctx->cf_info.exec_potentially_empty_break;
8362    ic->exec_potentially_empty_break_depth_old = ctx->cf_info.exec_potentially_empty_break_depth;
8363    ic->divergent_old = ctx->cf_info.parent_if.is_divergent;
8364    ctx->cf_info.parent_if.is_divergent = true;
8365
8366    /* divergent branches use cbranch_execz */
8367    ctx->cf_info.exec_potentially_empty_discard = false;
8368    ctx->cf_info.exec_potentially_empty_break = false;
8369    ctx->cf_info.exec_potentially_empty_break_depth = UINT16_MAX;
8370
8371    /** emit logical then block */
8372    Block* BB_then_logical = ctx->program->create_and_insert_block();
8373    BB_then_logical->loop_nest_depth = ctx->cf_info.loop_nest_depth;
8374    add_edge(ic->BB_if_idx, BB_then_logical);
8375    ctx->block = BB_then_logical;
8376    append_logical_start(BB_then_logical);
8377 }
8378
8379 static void begin_divergent_if_else(isel_context *ctx, if_context *ic)
8380 {
8381    Block *BB_then_logical = ctx->block;
8382    append_logical_end(BB_then_logical);
8383     /* branch from logical then block to invert block */
8384    aco_ptr<Pseudo_branch_instruction> branch;
8385    branch.reset(create_instruction<Pseudo_branch_instruction>(aco_opcode::p_branch, Format::PSEUDO_BRANCH, 0, 0));
8386    BB_then_logical->instructions.emplace_back(std::move(branch));
8387    add_linear_edge(BB_then_logical->index, &ic->BB_invert);
8388    if (!ctx->cf_info.parent_loop.has_divergent_branch)
8389       add_logical_edge(BB_then_logical->index, &ic->BB_endif);
8390    BB_then_logical->kind |= block_kind_uniform;
8391    assert(!ctx->cf_info.has_branch);
8392    ic->then_branch_divergent = ctx->cf_info.parent_loop.has_divergent_branch;
8393    ctx->cf_info.parent_loop.has_divergent_branch = false;
8394
8395    /** emit linear then block */
8396    Block* BB_then_linear = ctx->program->create_and_insert_block();
8397    BB_then_linear->loop_nest_depth = ctx->cf_info.loop_nest_depth;
8398    BB_then_linear->kind |= block_kind_uniform;
8399    add_linear_edge(ic->BB_if_idx, BB_then_linear);
8400    /* branch from linear then block to invert block */
8401    branch.reset(create_instruction<Pseudo_branch_instruction>(aco_opcode::p_branch, Format::PSEUDO_BRANCH, 0, 0));
8402    BB_then_linear->instructions.emplace_back(std::move(branch));
8403    add_linear_edge(BB_then_linear->index, &ic->BB_invert);
8404
8405    /** emit invert merge block */
8406    ctx->block = ctx->program->insert_block(std::move(ic->BB_invert));
8407    ic->invert_idx = ctx->block->index;
8408
8409    /* branch to linear else block (skip else) */
8410    branch.reset(create_instruction<Pseudo_branch_instruction>(aco_opcode::p_cbranch_nz, Format::PSEUDO_BRANCH, 1, 0));
8411    branch->operands[0] = Operand(ic->cond);
8412    ctx->block->instructions.push_back(std::move(branch));
8413
8414    ic->exec_potentially_empty_discard_old |= ctx->cf_info.exec_potentially_empty_discard;
8415    ic->exec_potentially_empty_break_old |= ctx->cf_info.exec_potentially_empty_break;
8416    ic->exec_potentially_empty_break_depth_old =
8417       std::min(ic->exec_potentially_empty_break_depth_old, ctx->cf_info.exec_potentially_empty_break_depth);
8418    /* divergent branches use cbranch_execz */
8419    ctx->cf_info.exec_potentially_empty_discard = false;
8420    ctx->cf_info.exec_potentially_empty_break = false;
8421    ctx->cf_info.exec_potentially_empty_break_depth = UINT16_MAX;
8422
8423    /** emit logical else block */
8424    Block* BB_else_logical = ctx->program->create_and_insert_block();
8425    BB_else_logical->loop_nest_depth = ctx->cf_info.loop_nest_depth;
8426    add_logical_edge(ic->BB_if_idx, BB_else_logical);
8427    add_linear_edge(ic->invert_idx, BB_else_logical);
8428    ctx->block = BB_else_logical;
8429    append_logical_start(BB_else_logical);
8430 }
8431
8432 static void end_divergent_if(isel_context *ctx, if_context *ic)
8433 {
8434    Block *BB_else_logical = ctx->block;
8435    append_logical_end(BB_else_logical);
8436
8437    /* branch from logical else block to endif block */
8438    aco_ptr<Pseudo_branch_instruction> branch;
8439    branch.reset(create_instruction<Pseudo_branch_instruction>(aco_opcode::p_branch, Format::PSEUDO_BRANCH, 0, 0));
8440    BB_else_logical->instructions.emplace_back(std::move(branch));
8441    add_linear_edge(BB_else_logical->index, &ic->BB_endif);
8442    if (!ctx->cf_info.parent_loop.has_divergent_branch)
8443       add_logical_edge(BB_else_logical->index, &ic->BB_endif);
8444    BB_else_logical->kind |= block_kind_uniform;
8445
8446    assert(!ctx->cf_info.has_branch);
8447    ctx->cf_info.parent_loop.has_divergent_branch &= ic->then_branch_divergent;
8448
8449
8450    /** emit linear else block */
8451    Block* BB_else_linear = ctx->program->create_and_insert_block();
8452    BB_else_linear->loop_nest_depth = ctx->cf_info.loop_nest_depth;
8453    BB_else_linear->kind |= block_kind_uniform;
8454    add_linear_edge(ic->invert_idx, BB_else_linear);
8455
8456    /* branch from linear else block to endif block */
8457    branch.reset(create_instruction<Pseudo_branch_instruction>(aco_opcode::p_branch, Format::PSEUDO_BRANCH, 0, 0));
8458    BB_else_linear->instructions.emplace_back(std::move(branch));
8459    add_linear_edge(BB_else_linear->index, &ic->BB_endif);
8460
8461
8462    /** emit endif merge block */
8463    ctx->block = ctx->program->insert_block(std::move(ic->BB_endif));
8464    append_logical_start(ctx->block);
8465
8466
8467    ctx->cf_info.parent_if.is_divergent = ic->divergent_old;
8468    ctx->cf_info.exec_potentially_empty_discard |= ic->exec_potentially_empty_discard_old;
8469    ctx->cf_info.exec_potentially_empty_break |= ic->exec_potentially_empty_break_old;
8470    ctx->cf_info.exec_potentially_empty_break_depth =
8471       std::min(ic->exec_potentially_empty_break_depth_old, ctx->cf_info.exec_potentially_empty_break_depth);
8472    if (ctx->cf_info.loop_nest_depth == ctx->cf_info.exec_potentially_empty_break_depth &&
8473        !ctx->cf_info.parent_if.is_divergent) {
8474       ctx->cf_info.exec_potentially_empty_break = false;
8475       ctx->cf_info.exec_potentially_empty_break_depth = UINT16_MAX;
8476    }
8477    /* uniform control flow never has an empty exec-mask */
8478    if (!ctx->cf_info.loop_nest_depth && !ctx->cf_info.parent_if.is_divergent) {
8479       ctx->cf_info.exec_potentially_empty_discard = false;
8480       ctx->cf_info.exec_potentially_empty_break = false;
8481       ctx->cf_info.exec_potentially_empty_break_depth = UINT16_MAX;
8482    }
8483 }
8484
8485 static void visit_if(isel_context *ctx, nir_if *if_stmt)
8486 {
8487    Temp cond = get_ssa_temp(ctx, if_stmt->condition.ssa);
8488    Builder bld(ctx->program, ctx->block);
8489    aco_ptr<Pseudo_branch_instruction> branch;
8490
8491    if (!ctx->divergent_vals[if_stmt->condition.ssa->index]) { /* uniform condition */
8492       /**
8493        * Uniform conditionals are represented in the following way*) :
8494        *
8495        * The linear and logical CFG:
8496        *                        BB_IF
8497        *                        /    \
8498        *       BB_THEN (logical)      BB_ELSE (logical)
8499        *                        \    /
8500        *                        BB_ENDIF
8501        *
8502        * *) Exceptions may be due to break and continue statements within loops
8503        *    If a break/continue happens within uniform control flow, it branches
8504        *    to the loop exit/entry block. Otherwise, it branches to the next
8505        *    merge block.
8506        **/
8507       append_logical_end(ctx->block);
8508       ctx->block->kind |= block_kind_uniform;
8509
8510       /* emit branch */
8511       assert(cond.regClass() == bld.lm);
8512       // TODO: in a post-RA optimizer, we could check if the condition is in VCC and omit this instruction
8513       cond = bool_to_scalar_condition(ctx, cond);
8514
8515       branch.reset(create_instruction<Pseudo_branch_instruction>(aco_opcode::p_cbranch_z, Format::PSEUDO_BRANCH, 1, 0));
8516       branch->operands[0] = Operand(cond);
8517       branch->operands[0].setFixed(scc);
8518       ctx->block->instructions.emplace_back(std::move(branch));
8519
8520       unsigned BB_if_idx = ctx->block->index;
8521       Block BB_endif = Block();
8522       BB_endif.loop_nest_depth = ctx->cf_info.loop_nest_depth;
8523       BB_endif.kind |= ctx->block->kind & block_kind_top_level;
8524
8525       /** emit then block */
8526       Block* BB_then = ctx->program->create_and_insert_block();
8527       BB_then->loop_nest_depth = ctx->cf_info.loop_nest_depth;
8528       add_edge(BB_if_idx, BB_then);
8529       append_logical_start(BB_then);
8530       ctx->block = BB_then;
8531       visit_cf_list(ctx, &if_stmt->then_list);
8532       BB_then = ctx->block;
8533       bool then_branch = ctx->cf_info.has_branch;
8534       bool then_branch_divergent = ctx->cf_info.parent_loop.has_divergent_branch;
8535
8536       if (!then_branch) {
8537          append_logical_end(BB_then);
8538          /* branch from then block to endif block */
8539          branch.reset(create_instruction<Pseudo_branch_instruction>(aco_opcode::p_branch, Format::PSEUDO_BRANCH, 0, 0));
8540          BB_then->instructions.emplace_back(std::move(branch));
8541          add_linear_edge(BB_then->index, &BB_endif);
8542          if (!then_branch_divergent)
8543             add_logical_edge(BB_then->index, &BB_endif);
8544          BB_then->kind |= block_kind_uniform;
8545       }
8546
8547       ctx->cf_info.has_branch = false;
8548       ctx->cf_info.parent_loop.has_divergent_branch = false;
8549
8550       /** emit else block */
8551       Block* BB_else = ctx->program->create_and_insert_block();
8552       BB_else->loop_nest_depth = ctx->cf_info.loop_nest_depth;
8553       add_edge(BB_if_idx, BB_else);
8554       append_logical_start(BB_else);
8555       ctx->block = BB_else;
8556       visit_cf_list(ctx, &if_stmt->else_list);
8557       BB_else = ctx->block;
8558
8559       if (!ctx->cf_info.has_branch) {
8560          append_logical_end(BB_else);
8561          /* branch from then block to endif block */
8562          branch.reset(create_instruction<Pseudo_branch_instruction>(aco_opcode::p_branch, Format::PSEUDO_BRANCH, 0, 0));
8563          BB_else->instructions.emplace_back(std::move(branch));
8564          add_linear_edge(BB_else->index, &BB_endif);
8565          if (!ctx->cf_info.parent_loop.has_divergent_branch)
8566             add_logical_edge(BB_else->index, &BB_endif);
8567          BB_else->kind |= block_kind_uniform;
8568       }
8569
8570       ctx->cf_info.has_branch &= then_branch;
8571       ctx->cf_info.parent_loop.has_divergent_branch &= then_branch_divergent;
8572
8573       /** emit endif merge block */
8574       if (!ctx->cf_info.has_branch) {
8575          ctx->block = ctx->program->insert_block(std::move(BB_endif));
8576          append_logical_start(ctx->block);
8577       }
8578    } else { /* non-uniform condition */
8579       /**
8580        * To maintain a logical and linear CFG without critical edges,
8581        * non-uniform conditionals are represented in the following way*) :
8582        *
8583        * The linear CFG:
8584        *                        BB_IF
8585        *                        /    \
8586        *       BB_THEN (logical)      BB_THEN (linear)
8587        *                        \    /
8588        *                        BB_INVERT (linear)
8589        *                        /    \
8590        *       BB_ELSE (logical)      BB_ELSE (linear)
8591        *                        \    /
8592        *                        BB_ENDIF
8593        *
8594        * The logical CFG:
8595        *                        BB_IF
8596        *                        /    \
8597        *       BB_THEN (logical)      BB_ELSE (logical)
8598        *                        \    /
8599        *                        BB_ENDIF
8600        *
8601        * *) Exceptions may be due to break and continue statements within loops
8602        **/
8603
8604       if_context ic;
8605
8606       begin_divergent_if_then(ctx, &ic, cond);
8607       visit_cf_list(ctx, &if_stmt->then_list);
8608
8609       begin_divergent_if_else(ctx, &ic);
8610       visit_cf_list(ctx, &if_stmt->else_list);
8611
8612       end_divergent_if(ctx, &ic);
8613    }
8614 }
8615
8616 static void visit_cf_list(isel_context *ctx,
8617                           struct exec_list *list)
8618 {
8619    foreach_list_typed(nir_cf_node, node, node, list) {
8620       switch (node->type) {
8621       case nir_cf_node_block:
8622          visit_block(ctx, nir_cf_node_as_block(node));
8623          break;
8624       case nir_cf_node_if:
8625          visit_if(ctx, nir_cf_node_as_if(node));
8626          break;
8627       case nir_cf_node_loop:
8628          visit_loop(ctx, nir_cf_node_as_loop(node));
8629          break;
8630       default:
8631          unreachable("unimplemented cf list type");
8632       }
8633    }
8634 }
8635
8636 static void export_vs_varying(isel_context *ctx, int slot, bool is_pos, int *next_pos)
8637 {
8638    int offset = ctx->program->info->vs.outinfo.vs_output_param_offset[slot];
8639    uint64_t mask = ctx->outputs.mask[slot];
8640    if (!is_pos && !mask)
8641       return;
8642    if (!is_pos && offset == AC_EXP_PARAM_UNDEFINED)
8643       return;
8644    aco_ptr<Export_instruction> exp{create_instruction<Export_instruction>(aco_opcode::exp, Format::EXP, 4, 0)};
8645    exp->enabled_mask = mask;
8646    for (unsigned i = 0; i < 4; ++i) {
8647       if (mask & (1 << i))
8648          exp->operands[i] = Operand(ctx->outputs.outputs[slot][i]);
8649       else
8650          exp->operands[i] = Operand(v1);
8651    }
8652    /* Navi10-14 skip POS0 exports if EXEC=0 and DONE=0, causing a hang.
8653     * Setting valid_mask=1 prevents it and has no other effect.
8654     */
8655    exp->valid_mask = ctx->options->chip_class >= GFX10 && is_pos && *next_pos == 0;
8656    exp->done = false;
8657    exp->compressed = false;
8658    if (is_pos)
8659       exp->dest = V_008DFC_SQ_EXP_POS + (*next_pos)++;
8660    else
8661       exp->dest = V_008DFC_SQ_EXP_PARAM + offset;
8662    ctx->block->instructions.emplace_back(std::move(exp));
8663 }
8664
8665 static void export_vs_psiz_layer_viewport(isel_context *ctx, int *next_pos)
8666 {
8667    aco_ptr<Export_instruction> exp{create_instruction<Export_instruction>(aco_opcode::exp, Format::EXP, 4, 0)};
8668    exp->enabled_mask = 0;
8669    for (unsigned i = 0; i < 4; ++i)
8670       exp->operands[i] = Operand(v1);
8671    if (ctx->outputs.mask[VARYING_SLOT_PSIZ]) {
8672       exp->operands[0] = Operand(ctx->outputs.outputs[VARYING_SLOT_PSIZ][0]);
8673       exp->enabled_mask |= 0x1;
8674    }
8675    if (ctx->outputs.mask[VARYING_SLOT_LAYER]) {
8676       exp->operands[2] = Operand(ctx->outputs.outputs[VARYING_SLOT_LAYER][0]);
8677       exp->enabled_mask |= 0x4;
8678    }
8679    if (ctx->outputs.mask[VARYING_SLOT_VIEWPORT]) {
8680       if (ctx->options->chip_class < GFX9) {
8681          exp->operands[3] = Operand(ctx->outputs.outputs[VARYING_SLOT_VIEWPORT][0]);
8682          exp->enabled_mask |= 0x8;
8683       } else {
8684          Builder bld(ctx->program, ctx->block);
8685
8686          Temp out = bld.vop2(aco_opcode::v_lshlrev_b32, bld.def(v1), Operand(16u),
8687                              Operand(ctx->outputs.outputs[VARYING_SLOT_VIEWPORT][0]));
8688          if (exp->operands[2].isTemp())
8689             out = bld.vop2(aco_opcode::v_or_b32, bld.def(v1), Operand(out), exp->operands[2]);
8690
8691          exp->operands[2] = Operand(out);
8692          exp->enabled_mask |= 0x4;
8693       }
8694    }
8695    exp->valid_mask = ctx->options->chip_class >= GFX10 && *next_pos == 0;
8696    exp->done = false;
8697    exp->compressed = false;
8698    exp->dest = V_008DFC_SQ_EXP_POS + (*next_pos)++;
8699    ctx->block->instructions.emplace_back(std::move(exp));
8700 }
8701
8702 static void create_vs_exports(isel_context *ctx)
8703 {
8704    radv_vs_output_info *outinfo = &ctx->program->info->vs.outinfo;
8705
8706    if (outinfo->export_prim_id) {
8707       ctx->outputs.mask[VARYING_SLOT_PRIMITIVE_ID] |= 0x1;
8708       ctx->outputs.outputs[VARYING_SLOT_PRIMITIVE_ID][0] = get_arg(ctx, ctx->args->vs_prim_id);
8709    }
8710
8711    if (ctx->options->key.has_multiview_view_index) {
8712       ctx->outputs.mask[VARYING_SLOT_LAYER] |= 0x1;
8713       ctx->outputs.outputs[VARYING_SLOT_LAYER][0] = as_vgpr(ctx, get_arg(ctx, ctx->args->ac.view_index));
8714    }
8715
8716    /* the order these position exports are created is important */
8717    int next_pos = 0;
8718    export_vs_varying(ctx, VARYING_SLOT_POS, true, &next_pos);
8719    if (outinfo->writes_pointsize || outinfo->writes_layer || outinfo->writes_viewport_index) {
8720       export_vs_psiz_layer_viewport(ctx, &next_pos);
8721    }
8722    if (ctx->num_clip_distances + ctx->num_cull_distances > 0)
8723       export_vs_varying(ctx, VARYING_SLOT_CLIP_DIST0, true, &next_pos);
8724    if (ctx->num_clip_distances + ctx->num_cull_distances > 4)
8725       export_vs_varying(ctx, VARYING_SLOT_CLIP_DIST1, true, &next_pos);
8726
8727    if (ctx->export_clip_dists) {
8728       if (ctx->num_clip_distances + ctx->num_cull_distances > 0)
8729          export_vs_varying(ctx, VARYING_SLOT_CLIP_DIST0, false, &next_pos);
8730       if (ctx->num_clip_distances + ctx->num_cull_distances > 4)
8731          export_vs_varying(ctx, VARYING_SLOT_CLIP_DIST1, false, &next_pos);
8732    }
8733
8734    for (unsigned i = 0; i <= VARYING_SLOT_VAR31; ++i) {
8735       if (i < VARYING_SLOT_VAR0 && i != VARYING_SLOT_LAYER &&
8736           i != VARYING_SLOT_PRIMITIVE_ID)
8737          continue;
8738
8739       export_vs_varying(ctx, i, false, NULL);
8740    }
8741 }
8742
8743 static void export_fs_mrt_z(isel_context *ctx)
8744 {
8745    Builder bld(ctx->program, ctx->block);
8746    unsigned enabled_channels = 0;
8747    bool compr = false;
8748    Operand values[4];
8749
8750    for (unsigned i = 0; i < 4; ++i) {
8751       values[i] = Operand(v1);
8752    }
8753
8754    /* Both stencil and sample mask only need 16-bits. */
8755    if (!ctx->program->info->ps.writes_z &&
8756        (ctx->program->info->ps.writes_stencil ||
8757         ctx->program->info->ps.writes_sample_mask)) {
8758       compr = true; /* COMPR flag */
8759
8760       if (ctx->program->info->ps.writes_stencil) {
8761          /* Stencil should be in X[23:16]. */
8762          values[0] = Operand(ctx->outputs.outputs[FRAG_RESULT_STENCIL][0]);
8763          values[0] = bld.vop2(aco_opcode::v_lshlrev_b32, bld.def(v1), Operand(16u), values[0]);
8764          enabled_channels |= 0x3;
8765       }
8766
8767       if (ctx->program->info->ps.writes_sample_mask) {
8768          /* SampleMask should be in Y[15:0]. */
8769          values[1] = Operand(ctx->outputs.outputs[FRAG_RESULT_SAMPLE_MASK][0]);
8770          enabled_channels |= 0xc;
8771      }
8772    } else {
8773       if (ctx->program->info->ps.writes_z) {
8774          values[0] = Operand(ctx->outputs.outputs[FRAG_RESULT_DEPTH][0]);
8775          enabled_channels |= 0x1;
8776       }
8777
8778       if (ctx->program->info->ps.writes_stencil) {
8779          values[1] = Operand(ctx->outputs.outputs[FRAG_RESULT_STENCIL][0]);
8780          enabled_channels |= 0x2;
8781       }
8782
8783       if (ctx->program->info->ps.writes_sample_mask) {
8784          values[2] = Operand(ctx->outputs.outputs[FRAG_RESULT_SAMPLE_MASK][0]);
8785          enabled_channels |= 0x4;
8786       }
8787    }
8788
8789    /* GFX6 (except OLAND and HAINAN) has a bug that it only looks at the X
8790     * writemask component.
8791     */
8792    if (ctx->options->chip_class == GFX6 &&
8793        ctx->options->family != CHIP_OLAND &&
8794        ctx->options->family != CHIP_HAINAN) {
8795             enabled_channels |= 0x1;
8796    }
8797
8798    bld.exp(aco_opcode::exp, values[0], values[1], values[2], values[3],
8799            enabled_channels, V_008DFC_SQ_EXP_MRTZ, compr);
8800 }
8801
8802 static void export_fs_mrt_color(isel_context *ctx, int slot)
8803 {
8804    Builder bld(ctx->program, ctx->block);
8805    unsigned write_mask = ctx->outputs.mask[slot];
8806    Operand values[4];
8807
8808    for (unsigned i = 0; i < 4; ++i) {
8809       if (write_mask & (1 << i)) {
8810          values[i] = Operand(ctx->outputs.outputs[slot][i]);
8811       } else {
8812          values[i] = Operand(v1);
8813       }
8814    }
8815
8816    unsigned target, col_format;
8817    unsigned enabled_channels = 0;
8818    aco_opcode compr_op = (aco_opcode)0;
8819
8820    slot -= FRAG_RESULT_DATA0;
8821    target = V_008DFC_SQ_EXP_MRT + slot;
8822    col_format = (ctx->options->key.fs.col_format >> (4 * slot)) & 0xf;
8823
8824    bool is_int8 = (ctx->options->key.fs.is_int8 >> slot) & 1;
8825    bool is_int10 = (ctx->options->key.fs.is_int10 >> slot) & 1;
8826
8827    switch (col_format)
8828    {
8829    case V_028714_SPI_SHADER_ZERO:
8830       enabled_channels = 0; /* writemask */
8831       target = V_008DFC_SQ_EXP_NULL;
8832       break;
8833
8834    case V_028714_SPI_SHADER_32_R:
8835       enabled_channels = 1;
8836       break;
8837
8838    case V_028714_SPI_SHADER_32_GR:
8839       enabled_channels = 0x3;
8840       break;
8841
8842    case V_028714_SPI_SHADER_32_AR:
8843       if (ctx->options->chip_class >= GFX10) {
8844          /* Special case: on GFX10, the outputs are different for 32_AR */
8845          enabled_channels = 0x3;
8846          values[1] = values[3];
8847          values[3] = Operand(v1);
8848       } else {
8849          enabled_channels = 0x9;
8850       }
8851       break;
8852
8853    case V_028714_SPI_SHADER_FP16_ABGR:
8854       enabled_channels = 0x5;
8855       compr_op = aco_opcode::v_cvt_pkrtz_f16_f32;
8856       break;
8857
8858    case V_028714_SPI_SHADER_UNORM16_ABGR:
8859       enabled_channels = 0x5;
8860       compr_op = aco_opcode::v_cvt_pknorm_u16_f32;
8861       break;
8862
8863    case V_028714_SPI_SHADER_SNORM16_ABGR:
8864       enabled_channels = 0x5;
8865       compr_op = aco_opcode::v_cvt_pknorm_i16_f32;
8866       break;
8867
8868    case V_028714_SPI_SHADER_UINT16_ABGR: {
8869       enabled_channels = 0x5;
8870       compr_op = aco_opcode::v_cvt_pk_u16_u32;
8871       if (is_int8 || is_int10) {
8872          /* clamp */
8873          uint32_t max_rgb = is_int8 ? 255 : is_int10 ? 1023 : 0;
8874          Temp max_rgb_val = bld.copy(bld.def(s1), Operand(max_rgb));
8875
8876          for (unsigned i = 0; i < 4; i++) {
8877             if ((write_mask >> i) & 1) {
8878                values[i] = bld.vop2(aco_opcode::v_min_u32, bld.def(v1),
8879                                     i == 3 && is_int10 ? Operand(3u) : Operand(max_rgb_val),
8880                                     values[i]);
8881             }
8882          }
8883       }
8884       break;
8885    }
8886
8887    case V_028714_SPI_SHADER_SINT16_ABGR:
8888       enabled_channels = 0x5;
8889       compr_op = aco_opcode::v_cvt_pk_i16_i32;
8890       if (is_int8 || is_int10) {
8891          /* clamp */
8892          uint32_t max_rgb = is_int8 ? 127 : is_int10 ? 511 : 0;
8893          uint32_t min_rgb = is_int8 ? -128 :is_int10 ? -512 : 0;
8894          Temp max_rgb_val = bld.copy(bld.def(s1), Operand(max_rgb));
8895          Temp min_rgb_val = bld.copy(bld.def(s1), Operand(min_rgb));
8896
8897          for (unsigned i = 0; i < 4; i++) {
8898             if ((write_mask >> i) & 1) {
8899                values[i] = bld.vop2(aco_opcode::v_min_i32, bld.def(v1),
8900                                     i == 3 && is_int10 ? Operand(1u) : Operand(max_rgb_val),
8901                                     values[i]);
8902                values[i] = bld.vop2(aco_opcode::v_max_i32, bld.def(v1),
8903                                     i == 3 && is_int10 ? Operand(-2u) : Operand(min_rgb_val),
8904                                     values[i]);
8905             }
8906          }
8907       }
8908       break;
8909
8910    case V_028714_SPI_SHADER_32_ABGR:
8911       enabled_channels = 0xF;
8912       break;
8913
8914    default:
8915       break;
8916    }
8917
8918    if (target == V_008DFC_SQ_EXP_NULL)
8919       return;
8920
8921    if ((bool) compr_op) {
8922       for (int i = 0; i < 2; i++) {
8923          /* check if at least one of the values to be compressed is enabled */
8924          unsigned enabled = (write_mask >> (i*2) | write_mask >> (i*2+1)) & 0x1;
8925          if (enabled) {
8926             enabled_channels |= enabled << (i*2);
8927             values[i] = bld.vop3(compr_op, bld.def(v1),
8928                                  values[i*2].isUndefined() ? Operand(0u) : values[i*2],
8929                                  values[i*2+1].isUndefined() ? Operand(0u): values[i*2+1]);
8930          } else {
8931             values[i] = Operand(v1);
8932          }
8933       }
8934       values[2] = Operand(v1);
8935       values[3] = Operand(v1);
8936    } else {
8937       for (int i = 0; i < 4; i++)
8938          values[i] = enabled_channels & (1 << i) ? values[i] : Operand(v1);
8939    }
8940
8941    bld.exp(aco_opcode::exp, values[0], values[1], values[2], values[3],
8942            enabled_channels, target, (bool) compr_op);
8943 }
8944
8945 static void create_fs_exports(isel_context *ctx)
8946 {
8947    /* Export depth, stencil and sample mask. */
8948    if (ctx->outputs.mask[FRAG_RESULT_DEPTH] ||
8949        ctx->outputs.mask[FRAG_RESULT_STENCIL] ||
8950        ctx->outputs.mask[FRAG_RESULT_SAMPLE_MASK]) {
8951       export_fs_mrt_z(ctx);
8952    }
8953
8954    /* Export all color render targets. */
8955    for (unsigned i = FRAG_RESULT_DATA0; i < FRAG_RESULT_DATA7 + 1; ++i) {
8956       if (ctx->outputs.mask[i])
8957          export_fs_mrt_color(ctx, i);
8958    }
8959 }
8960
8961 static void emit_stream_output(isel_context *ctx,
8962                                Temp const *so_buffers,
8963                                Temp const *so_write_offset,
8964                                const struct radv_stream_output *output)
8965 {
8966    unsigned num_comps = util_bitcount(output->component_mask);
8967    unsigned writemask = (1 << num_comps) - 1;
8968    unsigned loc = output->location;
8969    unsigned buf = output->buffer;
8970
8971    assert(num_comps && num_comps <= 4);
8972    if (!num_comps || num_comps > 4)
8973       return;
8974
8975    unsigned start = ffs(output->component_mask) - 1;
8976
8977    Temp out[4];
8978    bool all_undef = true;
8979    assert(ctx->stage == vertex_vs || ctx->stage == gs_copy_vs);
8980    for (unsigned i = 0; i < num_comps; i++) {
8981       out[i] = ctx->outputs.outputs[loc][start + i];
8982       all_undef = all_undef && !out[i].id();
8983    }
8984    if (all_undef)
8985       return;
8986
8987    while (writemask) {
8988       int start, count;
8989       u_bit_scan_consecutive_range(&writemask, &start, &count);
8990       if (count == 3 && ctx->options->chip_class == GFX6) {
8991          /* GFX6 doesn't support storing vec3, split it. */
8992          writemask |= 1u << (start + 2);
8993          count = 2;
8994       }
8995
8996       unsigned offset = output->offset + start * 4;
8997
8998       Temp write_data = {ctx->program->allocateId(), RegClass(RegType::vgpr, count)};
8999       aco_ptr<Pseudo_instruction> vec{create_instruction<Pseudo_instruction>(aco_opcode::p_create_vector, Format::PSEUDO, count, 1)};
9000       for (int i = 0; i < count; ++i)
9001          vec->operands[i] = (ctx->outputs.mask[loc] & 1 << (start + i)) ? Operand(out[start + i]) : Operand(0u);
9002       vec->definitions[0] = Definition(write_data);
9003       ctx->block->instructions.emplace_back(std::move(vec));
9004
9005       aco_opcode opcode;
9006       switch (count) {
9007       case 1:
9008          opcode = aco_opcode::buffer_store_dword;
9009          break;
9010       case 2:
9011          opcode = aco_opcode::buffer_store_dwordx2;
9012          break;
9013       case 3:
9014          opcode = aco_opcode::buffer_store_dwordx3;
9015          break;
9016       case 4:
9017          opcode = aco_opcode::buffer_store_dwordx4;
9018          break;
9019       default:
9020          unreachable("Unsupported dword count.");
9021       }
9022
9023       aco_ptr<MUBUF_instruction> store{create_instruction<MUBUF_instruction>(opcode, Format::MUBUF, 4, 0)};
9024       store->operands[0] = Operand(so_buffers[buf]);
9025       store->operands[1] = Operand(so_write_offset[buf]);
9026       store->operands[2] = Operand((uint32_t) 0);
9027       store->operands[3] = Operand(write_data);
9028       if (offset > 4095) {
9029          /* Don't think this can happen in RADV, but maybe GL? It's easy to do this anyway. */
9030          Builder bld(ctx->program, ctx->block);
9031          store->operands[0] = bld.vadd32(bld.def(v1), Operand(offset), Operand(so_write_offset[buf]));
9032       } else {
9033          store->offset = offset;
9034       }
9035       store->offen = true;
9036       store->glc = true;
9037       store->dlc = false;
9038       store->slc = true;
9039       store->can_reorder = true;
9040       ctx->block->instructions.emplace_back(std::move(store));
9041    }
9042 }
9043
9044 static void emit_streamout(isel_context *ctx, unsigned stream)
9045 {
9046    Builder bld(ctx->program, ctx->block);
9047
9048    Temp so_buffers[4];
9049    Temp buf_ptr = convert_pointer_to_64_bit(ctx, get_arg(ctx, ctx->args->streamout_buffers));
9050    for (unsigned i = 0; i < 4; i++) {
9051       unsigned stride = ctx->program->info->so.strides[i];
9052       if (!stride)
9053          continue;
9054
9055       Operand off = bld.copy(bld.def(s1), Operand(i * 16u));
9056       so_buffers[i] = bld.smem(aco_opcode::s_load_dwordx4, bld.def(s4), buf_ptr, off);
9057    }
9058
9059    Temp so_vtx_count = bld.sop2(aco_opcode::s_bfe_u32, bld.def(s1), bld.def(s1, scc),
9060                                 get_arg(ctx, ctx->args->streamout_config), Operand(0x70010u));
9061
9062    Temp tid = emit_mbcnt(ctx, bld.def(v1));
9063
9064    Temp can_emit = bld.vopc(aco_opcode::v_cmp_gt_i32, bld.def(bld.lm), so_vtx_count, tid);
9065
9066    if_context ic;
9067    begin_divergent_if_then(ctx, &ic, can_emit);
9068
9069    bld.reset(ctx->block);
9070
9071    Temp so_write_index = bld.vadd32(bld.def(v1), get_arg(ctx, ctx->args->streamout_write_idx), tid);
9072
9073    Temp so_write_offset[4];
9074
9075    for (unsigned i = 0; i < 4; i++) {
9076       unsigned stride = ctx->program->info->so.strides[i];
9077       if (!stride)
9078          continue;
9079
9080       if (stride == 1) {
9081          Temp offset = bld.sop2(aco_opcode::s_add_i32, bld.def(s1), bld.def(s1, scc),
9082                                 get_arg(ctx, ctx->args->streamout_write_idx),
9083                                 get_arg(ctx, ctx->args->streamout_offset[i]));
9084          Temp new_offset = bld.vadd32(bld.def(v1), offset, tid);
9085
9086          so_write_offset[i] = bld.vop2(aco_opcode::v_lshlrev_b32, bld.def(v1), Operand(2u), new_offset);
9087       } else {
9088          Temp offset = bld.v_mul_imm(bld.def(v1), so_write_index, stride * 4u);
9089          Temp offset2 = bld.sop2(aco_opcode::s_mul_i32, bld.def(s1), Operand(4u),
9090                                  get_arg(ctx, ctx->args->streamout_offset[i]));
9091          so_write_offset[i] = bld.vadd32(bld.def(v1), offset, offset2);
9092       }
9093    }
9094
9095    for (unsigned i = 0; i < ctx->program->info->so.num_outputs; i++) {
9096       struct radv_stream_output *output =
9097          &ctx->program->info->so.outputs[i];
9098       if (stream != output->stream)
9099          continue;
9100
9101       emit_stream_output(ctx, so_buffers, so_write_offset, output);
9102    }
9103
9104    begin_divergent_if_else(ctx, &ic);
9105    end_divergent_if(ctx, &ic);
9106 }
9107
9108 } /* end namespace */
9109
9110 void split_arguments(isel_context *ctx, Pseudo_instruction *startpgm)
9111 {
9112    /* Split all arguments except for the first (ring_offsets) and the last
9113     * (exec) so that the dead channels don't stay live throughout the program.
9114     */
9115    for (int i = 1; i < startpgm->definitions.size() - 1; i++) {
9116       if (startpgm->definitions[i].regClass().size() > 1) {
9117          emit_split_vector(ctx, startpgm->definitions[i].getTemp(),
9118                            startpgm->definitions[i].regClass().size());
9119       }
9120    }
9121 }
9122
9123 void handle_bc_optimize(isel_context *ctx)
9124 {
9125    /* needed when SPI_PS_IN_CONTROL.BC_OPTIMIZE_DISABLE is set to 0 */
9126    Builder bld(ctx->program, ctx->block);
9127    uint32_t spi_ps_input_ena = ctx->program->config->spi_ps_input_ena;
9128    bool uses_center = G_0286CC_PERSP_CENTER_ENA(spi_ps_input_ena) || G_0286CC_LINEAR_CENTER_ENA(spi_ps_input_ena);
9129    bool uses_centroid = G_0286CC_PERSP_CENTROID_ENA(spi_ps_input_ena) || G_0286CC_LINEAR_CENTROID_ENA(spi_ps_input_ena);
9130    ctx->persp_centroid = get_arg(ctx, ctx->args->ac.persp_centroid);
9131    ctx->linear_centroid = get_arg(ctx, ctx->args->ac.linear_centroid);
9132    if (uses_center && uses_centroid) {
9133       Temp sel = bld.vopc_e64(aco_opcode::v_cmp_lt_i32, bld.hint_vcc(bld.def(bld.lm)),
9134                               get_arg(ctx, ctx->args->ac.prim_mask), Operand(0u));
9135
9136       if (G_0286CC_PERSP_CENTROID_ENA(spi_ps_input_ena)) {
9137          Temp new_coord[2];
9138          for (unsigned i = 0; i < 2; i++) {
9139             Temp persp_centroid = emit_extract_vector(ctx, get_arg(ctx, ctx->args->ac.persp_centroid), i, v1);
9140             Temp persp_center = emit_extract_vector(ctx, get_arg(ctx, ctx->args->ac.persp_center), i, v1);
9141             new_coord[i] = bld.vop2(aco_opcode::v_cndmask_b32, bld.def(v1),
9142                                     persp_centroid, persp_center, sel);
9143          }
9144          ctx->persp_centroid = bld.tmp(v2);
9145          bld.pseudo(aco_opcode::p_create_vector, Definition(ctx->persp_centroid),
9146                     Operand(new_coord[0]), Operand(new_coord[1]));
9147          emit_split_vector(ctx, ctx->persp_centroid, 2);
9148       }
9149
9150       if (G_0286CC_LINEAR_CENTROID_ENA(spi_ps_input_ena)) {
9151          Temp new_coord[2];
9152          for (unsigned i = 0; i < 2; i++) {
9153             Temp linear_centroid = emit_extract_vector(ctx, get_arg(ctx, ctx->args->ac.linear_centroid), i, v1);
9154             Temp linear_center = emit_extract_vector(ctx, get_arg(ctx, ctx->args->ac.linear_center), i, v1);
9155             new_coord[i] = bld.vop2(aco_opcode::v_cndmask_b32, bld.def(v1),
9156                                     linear_centroid, linear_center, sel);
9157          }
9158          ctx->linear_centroid = bld.tmp(v2);
9159          bld.pseudo(aco_opcode::p_create_vector, Definition(ctx->linear_centroid),
9160                     Operand(new_coord[0]), Operand(new_coord[1]));
9161          emit_split_vector(ctx, ctx->linear_centroid, 2);
9162       }
9163    }
9164 }
9165
9166 void setup_fp_mode(isel_context *ctx, nir_shader *shader)
9167 {
9168    Program *program = ctx->program;
9169
9170    unsigned float_controls = shader->info.float_controls_execution_mode;
9171
9172    program->next_fp_mode.preserve_signed_zero_inf_nan32 =
9173       float_controls & FLOAT_CONTROLS_SIGNED_ZERO_INF_NAN_PRESERVE_FP32;
9174    program->next_fp_mode.preserve_signed_zero_inf_nan16_64 =
9175       float_controls & (FLOAT_CONTROLS_SIGNED_ZERO_INF_NAN_PRESERVE_FP16 |
9176                         FLOAT_CONTROLS_SIGNED_ZERO_INF_NAN_PRESERVE_FP64);
9177
9178    program->next_fp_mode.must_flush_denorms32 =
9179       float_controls & FLOAT_CONTROLS_DENORM_FLUSH_TO_ZERO_FP32;
9180    program->next_fp_mode.must_flush_denorms16_64 =
9181       float_controls & (FLOAT_CONTROLS_DENORM_FLUSH_TO_ZERO_FP16 |
9182                         FLOAT_CONTROLS_DENORM_FLUSH_TO_ZERO_FP64);
9183
9184    program->next_fp_mode.care_about_round32 =
9185       float_controls & (FLOAT_CONTROLS_ROUNDING_MODE_RTZ_FP32 | FLOAT_CONTROLS_ROUNDING_MODE_RTE_FP32);
9186
9187    program->next_fp_mode.care_about_round16_64 =
9188       float_controls & (FLOAT_CONTROLS_ROUNDING_MODE_RTZ_FP16 | FLOAT_CONTROLS_ROUNDING_MODE_RTZ_FP64 |
9189                         FLOAT_CONTROLS_ROUNDING_MODE_RTE_FP16 | FLOAT_CONTROLS_ROUNDING_MODE_RTE_FP64);
9190
9191    /* default to preserving fp16 and fp64 denorms, since it's free */
9192    if (program->next_fp_mode.must_flush_denorms16_64)
9193       program->next_fp_mode.denorm16_64 = 0;
9194    else
9195       program->next_fp_mode.denorm16_64 = fp_denorm_keep;
9196
9197    /* preserving fp32 denorms is expensive, so only do it if asked */
9198    if (float_controls & FLOAT_CONTROLS_DENORM_PRESERVE_FP32)
9199       program->next_fp_mode.denorm32 = fp_denorm_keep;
9200    else
9201       program->next_fp_mode.denorm32 = 0;
9202
9203    if (float_controls & FLOAT_CONTROLS_ROUNDING_MODE_RTZ_FP32)
9204       program->next_fp_mode.round32 = fp_round_tz;
9205    else
9206       program->next_fp_mode.round32 = fp_round_ne;
9207
9208    if (float_controls & (FLOAT_CONTROLS_ROUNDING_MODE_RTZ_FP16 | FLOAT_CONTROLS_ROUNDING_MODE_RTZ_FP64))
9209       program->next_fp_mode.round16_64 = fp_round_tz;
9210    else
9211       program->next_fp_mode.round16_64 = fp_round_ne;
9212
9213    ctx->block->fp_mode = program->next_fp_mode;
9214 }
9215
9216 void cleanup_cfg(Program *program)
9217 {
9218    /* create linear_succs/logical_succs */
9219    for (Block& BB : program->blocks) {
9220       for (unsigned idx : BB.linear_preds)
9221          program->blocks[idx].linear_succs.emplace_back(BB.index);
9222       for (unsigned idx : BB.logical_preds)
9223          program->blocks[idx].logical_succs.emplace_back(BB.index);
9224    }
9225 }
9226
9227 void select_program(Program *program,
9228                     unsigned shader_count,
9229                     struct nir_shader *const *shaders,
9230                     ac_shader_config* config,
9231                     struct radv_shader_args *args)
9232 {
9233    isel_context ctx = setup_isel_context(program, shader_count, shaders, config, args, false);
9234
9235    for (unsigned i = 0; i < shader_count; i++) {
9236       nir_shader *nir = shaders[i];
9237       init_context(&ctx, nir);
9238
9239       setup_fp_mode(&ctx, nir);
9240
9241       if (!i) {
9242          /* needs to be after init_context() for FS */
9243          Pseudo_instruction *startpgm = add_startpgm(&ctx);
9244          append_logical_start(ctx.block);
9245          split_arguments(&ctx, startpgm);
9246       }
9247
9248       if_context ic;
9249       if (shader_count >= 2) {
9250          Builder bld(ctx.program, ctx.block);
9251          Temp count = bld.sop2(aco_opcode::s_bfe_u32, bld.def(s1), bld.def(s1, scc), get_arg(&ctx, args->merged_wave_info), Operand((8u << 16) | (i * 8u)));
9252          Temp thread_id = emit_mbcnt(&ctx, bld.def(v1));
9253          Temp cond = bld.vopc(aco_opcode::v_cmp_gt_u32, bld.hint_vcc(bld.def(bld.lm)), count, thread_id);
9254
9255          begin_divergent_if_then(&ctx, &ic, cond);
9256       }
9257
9258       if (i) {
9259          Builder bld(ctx.program, ctx.block);
9260
9261          bld.barrier(aco_opcode::p_memory_barrier_shared);
9262          bld.sopp(aco_opcode::s_barrier);
9263
9264          if (ctx.stage == vertex_geometry_gs) {
9265             ctx.gs_wave_id = bld.sop2(aco_opcode::s_bfe_u32, bld.def(s1, m0), bld.def(s1, scc), get_arg(&ctx, args->merged_wave_info), Operand((8u << 16) | 16u));
9266          }
9267       } else if (ctx.stage == geometry_gs)
9268          ctx.gs_wave_id = get_arg(&ctx, args->gs_wave_id);
9269
9270       if (ctx.stage == fragment_fs)
9271          handle_bc_optimize(&ctx);
9272
9273       nir_function_impl *func = nir_shader_get_entrypoint(nir);
9274       visit_cf_list(&ctx, &func->body);
9275
9276       if (ctx.program->info->so.num_outputs && ctx.stage == vertex_vs)
9277          emit_streamout(&ctx, 0);
9278
9279       if (ctx.stage == vertex_vs) {
9280          create_vs_exports(&ctx);
9281       } else if (nir->info.stage == MESA_SHADER_GEOMETRY) {
9282          Builder bld(ctx.program, ctx.block);
9283          bld.barrier(aco_opcode::p_memory_barrier_gs_data);
9284          bld.sopp(aco_opcode::s_sendmsg, bld.m0(ctx.gs_wave_id), -1, sendmsg_gs_done(false, false, 0));
9285       }
9286
9287       if (ctx.stage == fragment_fs)
9288          create_fs_exports(&ctx);
9289
9290       if (shader_count >= 2) {
9291          begin_divergent_if_else(&ctx, &ic);
9292          end_divergent_if(&ctx, &ic);
9293       }
9294
9295       ralloc_free(ctx.divergent_vals);
9296    }
9297
9298    program->config->float_mode = program->blocks[0].fp_mode.val;
9299
9300    append_logical_end(ctx.block);
9301    ctx.block->kind |= block_kind_uniform | block_kind_export_end;
9302    Builder bld(ctx.program, ctx.block);
9303    if (ctx.program->wb_smem_l1_on_end)
9304       bld.smem(aco_opcode::s_dcache_wb, false);
9305    bld.sopp(aco_opcode::s_endpgm);
9306
9307    cleanup_cfg(program);
9308 }
9309
9310 void select_gs_copy_shader(Program *program, struct nir_shader *gs_shader,
9311                            ac_shader_config* config,
9312                            struct radv_shader_args *args)
9313 {
9314    isel_context ctx = setup_isel_context(program, 1, &gs_shader, config, args, true);
9315
9316    program->next_fp_mode.preserve_signed_zero_inf_nan32 = false;
9317    program->next_fp_mode.preserve_signed_zero_inf_nan16_64 = false;
9318    program->next_fp_mode.must_flush_denorms32 = false;
9319    program->next_fp_mode.must_flush_denorms16_64 = false;
9320    program->next_fp_mode.care_about_round32 = false;
9321    program->next_fp_mode.care_about_round16_64 = false;
9322    program->next_fp_mode.denorm16_64 = fp_denorm_keep;
9323    program->next_fp_mode.denorm32 = 0;
9324    program->next_fp_mode.round32 = fp_round_ne;
9325    program->next_fp_mode.round16_64 = fp_round_ne;
9326    ctx.block->fp_mode = program->next_fp_mode;
9327
9328    add_startpgm(&ctx);
9329    append_logical_start(ctx.block);
9330
9331    Builder bld(ctx.program, ctx.block);
9332
9333    Temp gsvs_ring = bld.smem(aco_opcode::s_load_dwordx4, bld.def(s4), program->private_segment_buffer, Operand(RING_GSVS_VS * 16u));
9334
9335    Operand stream_id(0u);
9336    if (args->shader_info->so.num_outputs)
9337       stream_id = bld.sop2(aco_opcode::s_bfe_u32, bld.def(s1), bld.def(s1, scc),
9338                            get_arg(&ctx, ctx.args->streamout_config), Operand(0x20018u));
9339
9340    Temp vtx_offset = bld.vop2(aco_opcode::v_lshlrev_b32, bld.def(v1), Operand(2u), get_arg(&ctx, ctx.args->ac.vertex_id));
9341
9342    std::stack<Block> endif_blocks;
9343
9344    for (unsigned stream = 0; stream < 4; stream++) {
9345       if (stream_id.isConstant() && stream != stream_id.constantValue())
9346          continue;
9347
9348       unsigned num_components = args->shader_info->gs.num_stream_output_components[stream];
9349       if (stream > 0 && (!num_components || !args->shader_info->so.num_outputs))
9350          continue;
9351
9352       memset(ctx.outputs.mask, 0, sizeof(ctx.outputs.mask));
9353
9354       unsigned BB_if_idx = ctx.block->index;
9355       Block BB_endif = Block();
9356       if (!stream_id.isConstant()) {
9357          /* begin IF */
9358          Temp cond = bld.sopc(aco_opcode::s_cmp_eq_u32, bld.def(s1, scc), stream_id, Operand(stream));
9359          append_logical_end(ctx.block);
9360          ctx.block->kind |= block_kind_uniform;
9361          bld.branch(aco_opcode::p_cbranch_z, cond);
9362
9363          BB_endif.kind |= ctx.block->kind & block_kind_top_level;
9364
9365          ctx.block = ctx.program->create_and_insert_block();
9366          add_edge(BB_if_idx, ctx.block);
9367          bld.reset(ctx.block);
9368          append_logical_start(ctx.block);
9369       }
9370
9371       unsigned offset = 0;
9372       for (unsigned i = 0; i <= VARYING_SLOT_VAR31; ++i) {
9373          if (args->shader_info->gs.output_streams[i] != stream)
9374             continue;
9375
9376          unsigned output_usage_mask = args->shader_info->gs.output_usage_mask[i];
9377          unsigned length = util_last_bit(output_usage_mask);
9378          for (unsigned j = 0; j < length; ++j) {
9379             if (!(output_usage_mask & (1 << j)))
9380                continue;
9381
9382             unsigned const_offset = offset * args->shader_info->gs.vertices_out * 16 * 4;
9383             Temp voffset = vtx_offset;
9384             if (const_offset >= 4096u) {
9385                voffset = bld.vadd32(bld.def(v1), Operand(const_offset / 4096u * 4096u), voffset);
9386                const_offset %= 4096u;
9387             }
9388
9389             aco_ptr<MUBUF_instruction> mubuf{create_instruction<MUBUF_instruction>(aco_opcode::buffer_load_dword, Format::MUBUF, 3, 1)};
9390             mubuf->definitions[0] = bld.def(v1);
9391             mubuf->operands[0] = Operand(gsvs_ring);
9392             mubuf->operands[1] = Operand(voffset);
9393             mubuf->operands[2] = Operand(0u);
9394             mubuf->offen = true;
9395             mubuf->offset = const_offset;
9396             mubuf->glc = true;
9397             mubuf->slc = true;
9398             mubuf->dlc = args->options->chip_class >= GFX10;
9399             mubuf->barrier = barrier_none;
9400             mubuf->can_reorder = true;
9401
9402             ctx.outputs.mask[i] |= 1 << j;
9403             ctx.outputs.outputs[i][j] = mubuf->definitions[0].getTemp();
9404
9405             bld.insert(std::move(mubuf));
9406
9407             offset++;
9408          }
9409       }
9410
9411       if (args->shader_info->so.num_outputs) {
9412          emit_streamout(&ctx, stream);
9413          bld.reset(ctx.block);
9414       }
9415
9416       if (stream == 0) {
9417          create_vs_exports(&ctx);
9418          ctx.block->kind |= block_kind_export_end;
9419       }
9420
9421       if (!stream_id.isConstant()) {
9422          append_logical_end(ctx.block);
9423
9424          /* branch from then block to endif block */
9425          bld.branch(aco_opcode::p_branch);
9426          add_edge(ctx.block->index, &BB_endif);
9427          ctx.block->kind |= block_kind_uniform;
9428
9429          /* emit else block */
9430          ctx.block = ctx.program->create_and_insert_block();
9431          add_edge(BB_if_idx, ctx.block);
9432          bld.reset(ctx.block);
9433          append_logical_start(ctx.block);
9434
9435          endif_blocks.push(std::move(BB_endif));
9436       }
9437    }
9438
9439    while (!endif_blocks.empty()) {
9440       Block BB_endif = std::move(endif_blocks.top());
9441       endif_blocks.pop();
9442
9443       Block *BB_else = ctx.block;
9444
9445       append_logical_end(BB_else);
9446       /* branch from else block to endif block */
9447       bld.branch(aco_opcode::p_branch);
9448       add_edge(BB_else->index, &BB_endif);
9449       BB_else->kind |= block_kind_uniform;
9450
9451       /** emit endif merge block */
9452       ctx.block = program->insert_block(std::move(BB_endif));
9453       bld.reset(ctx.block);
9454       append_logical_start(ctx.block);
9455    }
9456
9457    program->config->float_mode = program->blocks[0].fp_mode.val;
9458
9459    append_logical_end(ctx.block);
9460    ctx.block->kind |= block_kind_uniform;
9461    bld.sopp(aco_opcode::s_endpgm);
9462
9463    cleanup_cfg(program);
9464 }
9465 }